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[88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:03 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 1/6] dt-bindings: regulator: qcom,spmi-regulator: Convert to dtschema Date: Tue, 17 May 2022 13:59:55 +0200 Message-Id: <20220517120000.71048-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the bindings of Qualcomm SPMI regulators to DT schema. Signed-off-by: Robert Marko --- I am aware that syscon alone is not really acceptable, its converted directly from the old text bindings. There is also the issue of some MSM8994, MSM8996 and APQ8096 devices using '#address-cells', '#size-cells', some even defining reg property for regulators. Any advice on how to solve these issues is appreciated. Changes in v2: * Remove the forgotten text bindings * Move allOf after patternProperties * Use my private email as the maintainer email --- .../regulator/qcom,spmi-regulator.txt | 347 ------------------ .../regulator/qcom,spmi-regulator.yaml | 176 +++++++++ 2 files changed, 176 insertions(+), 347 deletions(-) delete mode 100644 Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt create mode 100644 Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt deleted file mode 100644 index c2a39b121b1b..000000000000 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt +++ /dev/null @@ -1,347 +0,0 @@ -Qualcomm SPMI Regulators - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,pm8004-regulators" - "qcom,pm8005-regulators" - "qcom,pm8226-regulators" - "qcom,pm8841-regulators" - "qcom,pm8916-regulators" - "qcom,pm8941-regulators" - "qcom,pm8950-regulators" - "qcom,pm8994-regulators" - "qcom,pmi8994-regulators" - "qcom,pm660-regulators" - "qcom,pm660l-regulators" - "qcom,pms405-regulators" - -- interrupts: - Usage: optional - Value type: - Definition: List of OCP interrupts. - -- interrupt-names: - Usage: required if 'interrupts' property present - Value type: - Definition: List of strings defining the names of the - interrupts in the 'interrupts' property 1-to-1. - Supported values are "ocp-", where - corresponds to a voltage switch - type regulator. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: - Usage: optional (pm8841 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_l1_l3-supply: -- vdd_l2-supply: -- vdd_l4_l5_l6-supply: -- vdd_l7-supply: -- vdd_l8_l11_l14_l15_l16-supply: -- vdd_l9_l10_l12_l13_l17_l18-supply: - Usage: optional (pm8916 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_l1_l3-supply: -- vdd_l2_lvs_1_2_3-supply: -- vdd_l4_l11-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l14_l15-supply: -- vdd_l8_l16_l18_19-supply: -- vdd_l9_l10_l17_l22-supply: -- vdd_l13_l20_l23_l24-supply: -- vdd_l21-supply: -- vin_5vs-supply: - Usage: optional (pm8941 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_l1_l19-supply: -- vdd_l2_l23-supply: -- vdd_l3-supply: -- vdd_l4_l5_l6_l7_l16-supply: -- vdd_l8_l11_l12_l17_l22-supply: -- vdd_l9_l10_l13_l14_l15_l18-supply: -- vdd_l20-supply: -- vdd_l21-supply: - Usage: optional (pm8950 only) - Value type: - Definition: reference to regulator supplying the input pin, as - described in the data sheet - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: -- vdd_s6-supply: -- vdd_s7-supply: -- vdd_s8-supply: -- vdd_s9-supply: -- vdd_s10-supply: -- vdd_s11-supply: -- vdd_s12-supply: -- vdd_l1-supply: -- vdd_l2_l26_l28-supply: -- vdd_l3_l11-supply: -- vdd_l4_l27_l31-supply: -- vdd_l5_l7-supply: -- vdd_l6_l12_l32-supply: -- vdd_l8_l16_l30-supply: -- vdd_l9_l10_l18_l22-supply: -- vdd_l13_l19_l23_l24-supply: -- vdd_l14_l15-supply: -- vdd_l17_l29-supply: -- vdd_l20_l21-supply: -- vdd_l25-supply: -- vdd_lvs_1_2-supply: - Usage: optional (pm8994 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_l1-supply: - Usage: optional (pmi8994 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_l1_l6_l7-supply: -- vdd_l2_l3-supply: -- vdd_l5-supply: -- vdd_l8_l9_l10_l11_l12_l13_l14-supply: -- vdd_l15_l16_l17_l18_l19-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s5-supply: -- vdd_s6-supply: - Usage: optional (pm660 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_l1_l9_l10-supply: -- vdd_l2-supply: -- vdd_l3_l5_l7_l8-supply: -- vdd_l4_l6-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply: - Usage: optional (pm660l only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- vdd_l1_l2-supply: -- vdd_l3_l8-supply: -- vdd_l4-supply: -- vdd_l5_l6-supply: -- vdd_l10_l11_l12_l13-supply: -- vdd_l7-supply: -- vdd_l9-supply: -- vdd_s1-supply: -- vdd_s2-supply: -- vdd_s3-supply: -- vdd_s4-supply: -- vdd_s5-supply - Usage: optional (pms405 only) - Value type: - Definition: Reference to regulator supplying the input pin, as - described in the data sheet. - -- qcom,saw-reg: - Usage: optional - Value type: - Description: Reference to syscon node defining the SAW registers. - - -The regulator node houses sub-nodes for each regulator within the device. Each -sub-node is identified using the node's name, with valid values listed for each -of the PMICs below. - -pm8004: - s2, s5 - -pm8005: - s1, s2, s3, s4 - -pm8841: - s1, s2, s3, s4, s5, s6, s7, s8 - -pm8916: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18 - -pm8941: - s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, - l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2, lvs3, - 5vs1, 5vs2 - -pm8994: - s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, - l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, - l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 - -pmi8994: - s1, s2, s3, l1 - -The content of each sub-node is defined by the standard binding for regulators - -see regulator.txt - with additional custom properties described below: - -- regulator-initial-mode: - Usage: optional - Value type: - Description: 2 = Set initial mode to auto mode (automatically select - between HPM and LPM); not available on boost type - regulators. - - 1 = Set initial mode to high power mode (HPM), also referred - to as NPM. HPM consumes more ground current than LPM, but - it can source significantly higher load current. HPM is not - available on boost type regulators. For voltage switch type - regulators, HPM implies that over current protection and - soft start are active all the time. - - 0 = Set initial mode to low power mode (LPM). - -- qcom,ocp-max-retries: - Usage: optional - Value type: - Description: Maximum number of times to try toggling a voltage switch - off and back on as a result of consecutive over current - events. - -- qcom,ocp-retry-delay: - Usage: optional - Value type: - Description: Time to delay in milliseconds between each voltage switch - toggle after an over current event takes place. - -- qcom,pin-ctrl-enable: - Usage: optional - Value type: - Description: Bit mask specifying which hardware pins should be used to - enable the regulator, if any; supported bits are: - 0 = ignore all hardware enable signals - BIT(0) = follow HW0_EN signal - BIT(1) = follow HW1_EN signal - BIT(2) = follow HW2_EN signal - BIT(3) = follow HW3_EN signal - -- qcom,pin-ctrl-hpm: - Usage: optional - Value type: - Description: Bit mask specifying which hardware pins should be used to - force the regulator into high power mode, if any; - supported bits are: - 0 = ignore all hardware enable signals - BIT(0) = follow HW0_EN signal - BIT(1) = follow HW1_EN signal - BIT(2) = follow HW2_EN signal - BIT(3) = follow HW3_EN signal - BIT(4) = follow PMIC awake state - -- qcom,vs-soft-start-strength: - Usage: optional - Value type: - Description: This property sets the soft start strength for voltage - switch type regulators; supported values are: - 0 = 0.05 uA - 1 = 0.25 uA - 2 = 0.55 uA - 3 = 0.75 uA - -- qcom,saw-slave: - Usage: optional - Value type: - Description: SAW controlled gang slave. Will not be configured. - -- qcom,saw-leader: - Usage: optional - Value type: - Description: SAW controlled gang leader. Will be configured as - SAW regulator. - -Example: - - regulators { - compatible = "qcom,pm8941-regulators"; - vdd_l1_l3-supply = <&s1>; - - s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - }; - - ... - - l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1300000>; - }; - - .... - }; - -Example 2: - - saw3: syscon@9A10000 { - compatible = "syscon"; - reg = <0x9A10000 0x1000>; - }; - - ... - - spm-regulators { - compatible = "qcom,pm8994-regulators"; - qcom,saw-reg = <&saw3>; - s8 { - qcom,saw-slave; - }; - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - pm8994_s11_saw: s11 { - qcom,saw-leader; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1140000>; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml new file mode 100644 index 000000000000..5c747c832529 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,spmi-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI Regulators + +maintainers: + - Robert Marko + +properties: + compatible: + enum: + - qcom,pm660-regulators + - qcom,pm660l-regulators + - qcom,pm8004-regulators + - qcom,pm8005-regulators + - qcom,pm8226-regulators + - qcom,pm8841-regulators + - qcom,pm8916-regulators + - qcom,pm8941-regulators + - qcom,pm8950-regulators + - qcom,pm8994-regulators + - qcom,pmi8994-regulators + - qcom,pms405-regulators + + qcom,saw-reg: + description: Reference to syscon node defining the SAW registers + $ref: "/schemas/types.yaml#/definitions/phandle" + +patternProperties: + ".*-supply$": + description: Input supply phandle(s) for this node + $ref: "/schemas/types.yaml#/definitions/phandle" + + "^((s|l|lvs|5vs)[0-9]*)$": + description: List of regulators and its properties + $ref: regulator.yaml# + + properties: + qcom,ocp-max-retries: + description: + Maximum number of times to try toggling a voltage switch off and + back on as a result of consecutive over current events + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,ocp-retry-delay: + description: + Time to delay in milliseconds between each voltage switch toggle + after an over current event takes place + $ref: "/schemas/types.yaml#/definitions/uint32" + + qcom,pin-ctrl-enable: + description: + Bit mask specifying which hardware pins should be used to enable the + regulator, if any. + Supported bits are + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 15 + + qcom,pin-ctrl-hpm: + description: + Bit mask specifying which hardware pins should be used to force the + regulator into high power mode, if any. + Supported bits are + 0 = ignore all hardware enable signals + BIT(0) = follow HW0_EN signal + BIT(1) = follow HW1_EN signal + BIT(2) = follow HW2_EN signal + BIT(3) = follow HW3_EN signal + BIT(4) = follow PMIC awake state + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 31 + + qcom,vs-soft-start-strength: + description: + This property sets the soft start strength for voltage switch type + regulators. + Supported values are + 0 = 0.05 uA + 1 = 0.25 uA + 2 = 0.55 uA + 3 = 0.75 uA + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3 + + qcom,saw-slave: + description: SAW controlled gang slave. Will not be configured. + type: boolean + + qcom,saw-leader: + description: + SAW controlled gang leader. Will be configured as SAW regulator. + type: boolean + + unevaluatedProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8941-regulators + then: + properties: + interrupts: + items: + - description: Over-current protection interrupt for 5V S1 + - description: Over-current protection interrupt for 5V S2 + interrupt-names: + items: + - const: ocp-5vs1 + - const: ocp-5vs2 + +unevaluatedProperties: false + +required: + - compatible + +examples: + - | + regulators { + compatible = "qcom,pm8941-regulators"; + vdd_l1_l3-supply = <&s1>; + + s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + }; + + l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + }; + + - | + saw3: syscon@9a10000 { + compatible = "syscon"; + reg = <0x9a10000 0x1000>; + }; + + regulators { + compatible = "qcom,pm8994-regulators"; + qcom,saw-reg = <&saw3>; + + s8 { + qcom,saw-slave; + }; + + s9 { + qcom,saw-slave; + }; + + s10 { + qcom,saw-slave; + }; + + pm8994_s11_saw: s11 { + qcom,saw-leader; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1140000>; + }; + }; +... From patchwork Tue May 17 11:59:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B113C433EF for ; Tue, 17 May 2022 12:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345679AbiEQMAp (ORCPT ); Tue, 17 May 2022 08:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345698AbiEQMAJ (ORCPT ); Tue, 17 May 2022 08:00:09 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80DC14C438; Tue, 17 May 2022 05:00:06 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id p26so5860196eds.5; Tue, 17 May 2022 05:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oIDUTK5KnimKV7JPutWUmQpjQBhC0JH0W89/0KDYnjU=; b=RQCz9EbIFBKO/NOfhXlfo4Q7TvDzKZ7H7v4R/cNmC+z4puIALw2lhYHwQBhoLjnLbR Ndjq20lDO3NwP0RwxjtLVogUH7KFgcARDSxN3iBtameSx2RZi0Wh1aq6RKtnkq/Spl06 XE5sRBl3nq8pdk9PfdoML96Nprl3ww+pEW478UnctxZ3U1v2Ae5xzJJxVGdqg15cTJdP 29Zpcwb9feZFy+NXvVZr7nD2KPzOPYE4GqYPPkLG+cb5FX3i1VyXUvSenrsnQzBoGBlA 16CxSVZfQyf4c18zjoT3KmfFZUrhRHNyhTgdlLGZUHbTtSZVdiW5YG+pLnXxRjJ2dd76 IIVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oIDUTK5KnimKV7JPutWUmQpjQBhC0JH0W89/0KDYnjU=; b=JdsqUrz7+PFK9S6/jk91HEu+cK1hn1bNaX/mliBpNyz60/t/3UMeACfaWgqcsF5wmA kBFivN5aVGG6s65dB7PdzeHG0oBReJYLpaJiXR8irKMpVvnZaQwZ6kIKUiG1TyuonTrF 2/s7iBBpKWF+6jwLnrOtWw9t8MX6k0TPktI9OeBL0i7t1t/b5nzNXwPZNrvKUq8PY3ko F4oKwyHiXWDXh3egGexuOR8hqbmXGQmoeLWzb5HrEYHmQfxti6Hy10OV9Zs24iGAgfwk bUQyiiOyZK4TvflSfDRui3I7qvX4vK1DvJx/Kph9yyO0gNxhrSAzRyyBzG2Vctrkmq0C sfJA== X-Gm-Message-State: AOAM532545Ibidlg8V8ZplKA79ewSm8MN/Z4qEIt0PPy7lri46kYWTMr fLjcINlInpF8dPWcyAIfCrM= X-Google-Smtp-Source: ABdhPJyDRt/3ywLm3HpJw0qfsNJeUCoRwrcCtPK6mz7pj68/AwsGEti4Otcb/RnNx7gSnhGljzOwBw== X-Received: by 2002:a50:ed8b:0:b0:42a:a7e0:f889 with SMTP id h11-20020a50ed8b000000b0042aa7e0f889mr13997868edr.79.1652788804933; Tue, 17 May 2022 05:00:04 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:04 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 2/6] regulator: qcom_spmi: add support for HT_P150 Date: Tue, 17 May 2022 13:59:56 +0200 Message-Id: <20220517120000.71048-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220517120000.71048-1-robimarko@gmail.com> References: <20220517120000.71048-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout found in PMP8074 and PMS405 PMIC-s. Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V but the actual MAX output voltage depends on the exact LDO in each of the PMIC-s. It has a max current of 150mA, voltage step of 8mV. Signed-off-by: Robert Marko --- drivers/regulator/qcom_spmi-regulator.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 02bfce981150..38bbc70241ae 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -164,6 +164,7 @@ enum spmi_regulator_subtype { SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, + SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, }; enum spmi_common_regulator_registers { @@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_ranges[] = { SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), }; +static struct spmi_voltage_range ht_p150_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000), +}; + static DEFINE_SPMI_SET_POINTS(pldo); static DEFINE_SPMI_SET_POINTS(nldo1); static DEFINE_SPMI_SET_POINTS(nldo2); @@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660); static DEFINE_SPMI_SET_POINTS(ht_lvpldo); static DEFINE_SPMI_SET_POINTS(ht_nldo); static DEFINE_SPMI_SET_POINTS(hfs430); +static DEFINE_SPMI_SET_POINTS(ht_p150); static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, int len) @@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_hfs430_ops = { static const struct spmi_regulator_mapping supported_regulators[] = { /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ + SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), From patchwork Tue May 17 11:59:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE222C433EF for ; Tue, 17 May 2022 12:00:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345898AbiEQMAf (ORCPT ); Tue, 17 May 2022 08:00:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343758AbiEQMAN (ORCPT ); Tue, 17 May 2022 08:00:13 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 644554C7BB; Tue, 17 May 2022 05:00:07 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id i9so2992394edr.8; Tue, 17 May 2022 05:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ooYOi4l5nQa47D/Eah2WC+R7MerVr/2GEpfrRHxpbMA=; b=Rz+2p3JKDR+LdtBba/c+Ac/6pGd9TQdiVpse9+imTRFwhjQLUkaJ6FGMgxK6wBtGy5 1XjK03HrIl7K1CN43snO2OZXbKBcDNooi0yZ/QXCYYYhC5S0rrBXXsLPT7J0+78VQRs7 JDU4xW8daSCst+PYuLHJC2S27xamh7aigmuGENg/zoLQHizilFLVswuBFd7ZmBknm/3i mQAWLzgwZG80zYdUxoE1H9fk1xBQOfApCX30spsJXxXYzAIK2zkSGIyFC8nNr3SntpWU oxfhmHttqwgIh7pxqCow/J6dIHhsD01C5Q62i3aqczggn1IlW+thFK4E3G3/rDaGX3u2 NyQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ooYOi4l5nQa47D/Eah2WC+R7MerVr/2GEpfrRHxpbMA=; b=fsUnMsAtVIYxuafZ6MBjOF61ahjT/2KRHCoqJ7y42XDMYxIxeKR0Fw/7YyAv+TG/e/ rPV/YPW14Y14E20kVLwiAcWOOPThgW9GzbIoKdUtXNvPr6aDf2v6QMOwqZ80vx7A0jCR IiGKYhj4+DYwwQ+0MYlnCZIqNpCqMAHAkmhzkd2YHwxWTpQDQ71CTXf55hG9ND/dHF3y 29KRpwXI8d1ACTNUm0+t0Yagaz02ShPSf9eePf5mG6wlCIHWyehMbXLZ5M+zTMXSV03R obrwvtHyZhb7KEHDpB31bl1CTE8gzIlBsoT7ykwA0PBUAnWqsV5fU5JDvWWu1xZIn1Gx k7lg== X-Gm-Message-State: AOAM532QuFcLkB63aTdflL5Ht9fAwSAtqpyrE0wQhvrxPZnX3g/dLKo2 z5V6niNDS4uT4D8uz5VmJL31PAVAMOiWxw== X-Google-Smtp-Source: ABdhPJxo9vL9nnCYYerUvqY0tYnOcWm/jA8rwxXqEm5mkWDvisQFpPgEq7Dxps/NSmqam2HBYhBsSQ== X-Received: by 2002:a50:a68e:0:b0:42a:c9ae:469 with SMTP id e14-20020a50a68e000000b0042ac9ae0469mr2199445edc.202.1652788806011; Tue, 17 May 2022 05:00:06 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:05 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 3/6] dt-bindings: regulator: qcom,spmi-regulator: add PMP8074 PMIC Date: Tue, 17 May 2022 13:59:57 +0200 Message-Id: <20220517120000.71048-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220517120000.71048-1-robimarko@gmail.com> References: <20220517120000.71048-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the PMP8074 PMIC compatible. Signed-off-by: Robert Marko --- .../devicetree/bindings/regulator/qcom,spmi-regulator.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml index 5c747c832529..4c7c693a48ab 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.yaml @@ -23,6 +23,7 @@ properties: - qcom,pm8950-regulators - qcom,pm8994-regulators - qcom,pmi8994-regulators + - qcom,pmp8074-regulators - qcom,pms405-regulators qcom,saw-reg: From patchwork Tue May 17 11:59:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 673EEC43217 for ; Tue, 17 May 2022 12:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345598AbiEQMAo (ORCPT ); Tue, 17 May 2022 08:00:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345713AbiEQMAT (ORCPT ); Tue, 17 May 2022 08:00:19 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 821234C43C; Tue, 17 May 2022 05:00:08 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id ch13so34137891ejb.12; Tue, 17 May 2022 05:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DzxGK66oNP5EqUefEbuvx65uQZvfKjOjhE65FjoDOMc=; b=O1XqqJDdR2eKJn/3+OmYQ8rAWfD4lpv59KEyW9LqI5Xv3yM95R0odaM6rY6AJ8Wzf7 gthXPzyZjbt/tmmUwoYQsxPZtYHjG0bp/WPjm+Eqo9IOjT+pzF107RMGE7ePVstiUK04 8e+XwrfEQeAeFooHrsV49qZuAr80wGOvxNey1OIaUjVM6mOEPxI99SSivwIppHcjKc2j FayCvvMFnOo/+TZYHJ1fFRZGw2/9zjVKC9Mho6wJtml0b4McXU2kFzOeKcaLaJ4xBZb2 6dj6W9PMBZI0Rpe7BOZ0ghzLxX2KHdNaH+QvTYnJT6q5RqIcesTwLvZ5p97f7+wevmsh UiJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DzxGK66oNP5EqUefEbuvx65uQZvfKjOjhE65FjoDOMc=; b=US+fAqdhoAoEmzfzpLWbE3Eu0mWq9hycjQu0zqO672y91KbGV389nYS+SXuWQdPnF2 lj0EJTGGw+NNwdDcTpnQOZNZXVhJim0IZLEGK46C2TKUU2MvkVsvLt7p0lCl1mfNSxHJ zKnt5pbDqpXvo5BhjXlB+Z1r/VcHM7dfel8U4JGT1BKueKFUHhXzxqE4RgroSdpRmILK M19Rid/BDgzfosEAr96p+ELdwwcZH5HcV6bdKyr83vSNyBfJBHoLg9mmGe9F1rqQ5sIc oJHGtOsjngLuvpgBoN+MWyNex6SjjHd3+un0ILmj1TJblWH7cj16sjZbmvTFI5J2CY0b ICGw== X-Gm-Message-State: AOAM531zjzkczMruDqFTKvE9cJ6KAeqLQ9bNHCIwsJsghr1y4O9047Mk m9zj++8v9D7svd9f9yY1BGM= X-Google-Smtp-Source: ABdhPJy5lPqbw1Cp4jdlGAc/DEDvey5xejh9pUs7hRyiTR6u33fGRoBQ4S4v04bAYQG4DlXFeiGmeQ== X-Received: by 2002:a17:907:8c06:b0:6f4:9935:9049 with SMTP id ta6-20020a1709078c0600b006f499359049mr19792354ejc.517.1652788806982; Tue, 17 May 2022 05:00:06 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:06 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 4/6] regulator: qcom_spmi: Add support for PMP8074 regulators Date: Tue, 17 May 2022 13:59:58 +0200 Message-Id: <20220517120000.71048-4-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220517120000.71048-1-robimarko@gmail.com> References: <20220517120000.71048-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s. It features 5 HF-SMPS and 13 LDO regulators. This commit adds support for S3 and S4 HF-SMPS buck regulators of the HFS430 type and LDO11 of the HT_P150 type. S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores and LDO11 is the SDIO/eMMC I/O voltage regulator required for high speeds. Signed-off-by: Robert Marko --- drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 38bbc70241ae..696b088aae40 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -2137,6 +2137,13 @@ static const struct spmi_regulator_data pms405_regulators[] = { { } }; +static const struct spmi_regulator_data pmp8074_regulators[] = { + { "s3", 0x1a00, "vdd_s3"}, + { "s4", 0x1d00, "vdd_s4"}, + { "l11", 0x4a00, "vdd_l10_l11_l12_l13"}, + { } +}; + static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, @@ -2150,6 +2157,7 @@ static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, + { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, { } }; MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); From patchwork Tue May 17 11:59:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED2F6C433F5 for ; Tue, 17 May 2022 12:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345910AbiEQMAg (ORCPT ); Tue, 17 May 2022 08:00:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345714AbiEQMAT (ORCPT ); Tue, 17 May 2022 08:00:19 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E9F04C431; Tue, 17 May 2022 05:00:09 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id l18so34182924ejc.7; Tue, 17 May 2022 05:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S1hlOjb+KKdy0/QG/BxO1k2JNdhSZM3UJOdwKv3T7/8=; b=BU2KTNM4aG0nn5hJWHP5ZC3Ez46/Z+TnTCi2W7zcOdcbNCX4fglgyfFxa2cHGtM8Rw A6/srugFXEv1nzy7qWO4TPhGJuBhSi8uUANJCqjDL4SBt8SrNla2ZST48FHpzVnIUj84 6FRr1Mk8mjynIoFK5EKKR3fjwc2C/DXnY71Mief70mWbVoLq+7gjFKYYV8P53sIQemX8 b/G5aVVyVJNTMUIoa+xzD2AUoQekDDd7KPsag63QKN8Gmm6Fm38xN5Yae7rAq1AoHxEz n5yKXyK9w5D6aAYvXW1yCMXBlVXNim7cKiw+MNvc8gi9ZzPJ2bdLJq71Zk2GLBC/Vuu/ aSEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S1hlOjb+KKdy0/QG/BxO1k2JNdhSZM3UJOdwKv3T7/8=; b=yLidfNKebGCOao4SFSqYXnPY0EnXYPnxH+b2/+IMpWTJ8FehB2hJB+b0wuksioEuLp 9wa1hE7KkCIm7ZUqlVKsDAf3+Za8jXBI2VQ1+X/ka8mQCXGXOtYafjpOYdE+UfUzPj7P gAmR5fqa/PI0GdYJsX3Ib6EtvJy5JYBqiEN7YPWctHXH3F29g+A4GlO98cYTjz2vpBW3 xMH81Mgnt6qx++M96ZXzQCy/upT5IAdN+aDTxGv6639Rp8+jKEk3IFr4eacEyWX4qsKH 34sA36ohnDqzu0O408V2CccFW3UDZReSfRQmkqP2tNIul7Js5DIytnNwfL/+Js/OuAuW IpGw== X-Gm-Message-State: AOAM530BOaATufCZbYYQFja8p5nbKQ1P46iu/bmmBRedvM6wYLFqymAv 7LMUPE6naLI340dvJjmKZ4VtJA/Uk4J7Yg== X-Google-Smtp-Source: ABdhPJzS14AXLwhmzYl0Su0S93YfqX+6XOFjUdkedc6MteP8Kt4tfH+b2zdN1Nl35XOglwIUKGvmgQ== X-Received: by 2002:a17:907:a0c8:b0:6f7:492e:e74c with SMTP id hw8-20020a170907a0c800b006f7492ee74cmr19173903ejc.670.1652788808057; Tue, 17 May 2022 05:00:08 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:07 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 5/6] arm64: dts: ipq8074: add SPMI PMP8074 PMIC regulators Date: Tue, 17 May 2022 13:59:59 +0200 Message-Id: <20220517120000.71048-5-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220517120000.71048-1-robimarko@gmail.com> References: <20220517120000.71048-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PMP8074 is used in IPQ8074 and provides S3 for cores, S4 for UBI core and LDO11 for SDIO/eMMC. So, lets add the nodes in preparation for DVFS later. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 789fec7c6aa4..d1a0b77c38a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { model = "Qualcomm Technologies, Inc. IPQ8074"; @@ -421,6 +422,39 @@ spmi_bus: spmi@200f000 { interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; + + pmic@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + regulators { + compatible = "qcom,pmp8074-regulators"; + + s3: s3 { + regulator-name = "vdd_s3"; + regulator-min-microvolt = <592000>; + regulator-max-microvolt = <1064000>; + regulator-always-on; + regulator-boot-on; + }; + + s4: s4 { + regulator-name = "vdd_s4"; + regulator-min-microvolt = <712000>; + regulator-max-microvolt = <992000>; + regulator-always-on; + regulator-boot-on; + }; + + l11: l11 { + regulator-name = "l11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; }; sdhc_1: sdhci@7824900 { From patchwork Tue May 17 12:00:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1843C4332F for ; Tue, 17 May 2022 12:00:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345622AbiEQMAm (ORCPT ); Tue, 17 May 2022 08:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345716AbiEQMAV (ORCPT ); Tue, 17 May 2022 08:00:21 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A9284CD44; Tue, 17 May 2022 05:00:10 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id i19so34183722eja.11; Tue, 17 May 2022 05:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PAidMuA0ZfVLTFeYOY0jFETaKP5wFrL8y0MLkBWu2Mo=; b=Nk38ea2oeCbD8O058H3VMyJ5yxX8JNiGPQpf+RzwZfoUMwizfXVES2qnc9DmjDPskO mdfUkp40tpgTIdf47RFecu2Jcdrw/5mMPCwVREBWaF7qwSwbX7ptM7FpV6GQIsoJkyRJ E65deQoZm31KLlt7aSQfFSKyC0j6rwfTIUCmg5AjVW9YZfTlp7mtbwi7k2bubvbQSolJ xWoFprG43WD5xZNMKS62A7dfGGM/L5IYE2WD0yTwBGxbwwJ6XxAKYHrtw8OI0FHnVf5g Ezkd4GYMaaCCiUzlnXmkn9P6dlzdsKO0yQCL6xI6v32ujTsjkac2WUYmaH8dS3JLt5HP AS0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PAidMuA0ZfVLTFeYOY0jFETaKP5wFrL8y0MLkBWu2Mo=; b=vXx7jm7Ol55tQjJuZZYdkDCHVwRAguPZu9rnlgPyjweVHiJAbhnGOE3EYvGns9UtFr 2GtY8RkpkNRWejhQIrK1IZ0vcDTs2HvR8qqtNorGMEcNoK6sYGxtb59d45GKSSaed+Zv /MUQX/PIX452/v1Zul6qid3k+fHv7WXjI9Mj6yf4GKCHd0NzEyQhF4wEiQM7X/l6AGvO J8bVk3/Wk/3RUoHRO2Jp9DQZys9rDcGLyzkOvJUPq+RWs0AD/VQogWhnSVrTXy+Hk8p8 o08N/hXnmrhuGM56Wm31c/QGbxfjYNaXb6BgVkVjGX2ng7EvFgu7pIMm8iDGBamBFved 55ow== X-Gm-Message-State: AOAM530MI1DZjGa/KzX11z5J+LfZnGoyTxN13Eoi89HQv1hqlO/fc4E4 LBPtNvi7B9Nz9rrciBnUI8w= X-Google-Smtp-Source: ABdhPJx0xq/cRbDvNlIWIcAne3Bp5H3b6MmvrYn/C0TdCB8KTbJZ+25ILBRKVac9wWnRXsboSjTLwQ== X-Received: by 2002:a17:907:7e85:b0:6f4:78f1:75b5 with SMTP id qb5-20020a1709077e8500b006f478f175b5mr19728011ejc.54.1652788809052; Tue, 17 May 2022 05:00:09 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id hg16-20020a1709072cd000b006f3ef214e20sm948793ejc.134.2022.05.17.05.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 May 2022 05:00:08 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 6/6] arm64: dts: ipq8074: add VQMMC supply Date: Tue, 17 May 2022 14:00:00 +0200 Message-Id: <20220517120000.71048-6-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220517120000.71048-1-robimarko@gmail.com> References: <20220517120000.71048-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDHCI controller claims DDR, HS200 and HS400 1.8V support, however it cannot achieve those using the 2.95V I/O that is the default set by firmware. Since we know have access to the PMP8074 PMIC provided LDO that provides the I/O voltage set it as VQMMC supply so that higher speeds can actually be achieved. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d1a0b77c38a4..fea3c4ee3565 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -476,6 +476,8 @@ sdhc_1: sdhci@7824900 { mmc-hs400-1_8v; bus-width = <8>; + vqmmc-supply = <&l11>; + status = "disabled"; };