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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id bf3-20020a170902b90300b0015f2b3bc97asm9106026plb.13.2022.06.28.04.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 04:43:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com Subject: [PATCH v5 1/2] target/xtensa: Use an exception for semihosting Date: Tue, 28 Jun 2022 17:13:06 +0530 Message-Id: <20220628114307.697943-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628114307.697943-1-richard.henderson@linaro.org> References: <20220628114307.697943-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 ++ target/xtensa/helper.h | 3 --- target/xtensa/exc_helper.c | 4 ++++ target/xtensa/translate.c | 3 ++- target/xtensa/xtensa-semi.c | 3 +-- 5 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 579adcb769..ea66895e7f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -260,6 +260,7 @@ enum { EXC_USER, EXC_DOUBLE, EXC_DEBUG, + EXC_SEMIHOST, EXC_MAX }; @@ -576,6 +577,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void xtensa_semihosting(CPUXtensaState *env); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index ae938ceedb..531679cd86 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -11,9 +11,6 @@ DEF_HELPER_2(retw, void, env, i32) DEF_HELPER_3(window_check, noreturn, env, i32, i32) DEF_HELPER_1(restore_owb, void, env) DEF_HELPER_2(movsp, void, env, i32) -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(simcall, void, env) -#endif #ifndef CONFIG_USER_ONLY DEF_HELPER_3(waiti, void, env, i32, i32) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cd..d54a518875 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -219,6 +219,10 @@ void xtensa_cpu_do_interrupt(CPUState *cs) } switch (cs->exception_index) { + case EXC_SEMIHOST: + xtensa_semihosting(env); + return; + case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 70e11eeb45..b65c8b8428 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2377,7 +2377,8 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], { #ifndef CONFIG_USER_ONLY if (semihosting_enabled()) { - gen_helper_simcall(cpu_env); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXC_SEMIHOST); } #endif } diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index fa21b7e11f..5375f106fc 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "chardev/char-fe.h" -#include "exec/helper-proto.h" #include "semihosting/semihost.h" #include "qapi/error.h" #include "qemu/log.h" @@ -188,7 +187,7 @@ void xtensa_sim_open_console(Chardev *chr) sim_console = &console; } -void HELPER(simcall)(CPUXtensaState *env) +void xtensa_semihosting(CPUXtensaState *env) { CPUState *cs = env_cpu(env); uint32_t *regs = env->regs; From patchwork Tue Jun 28 11:43:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 585579 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp681640mab; Tue, 28 Jun 2022 04:45:02 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ur0qoFkbR1iHRhhEfn6n08yAo0EvJk3xIk1fpeJ87GEBnLhy4ev/O+hEmzAB8wW35v3/5O X-Received: by 2002:a05:620a:4306:b0:6a9:7122:edb2 with SMTP id u6-20020a05620a430600b006a97122edb2mr11005144qko.502.1656416702455; Tue, 28 Jun 2022 04:45:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1656416702; cv=none; d=google.com; s=arc-20160816; b=FH5CUgB+Mat19+RcA9qNNwsZiphkvL3yM1CES+JD9DkmnMJZIctjKqI1lJ+ra6mMUV bxdLR4uMNHVKyHNdizdPGRdCUvr+GNFTLJDZ+4AseJx8pE6L4Oju88Og/6KYLkX9y/Gb zOQ2FUCQYJYgFj57Vsc1RO8zp6oPEFEPys+0WN4hwoY2zhwCU+iQCIfKXy7LVUKpoG3t X9NRxIEcl6b132F/I2zinaK46Rh/kX65lTO0YPGgQznQECm+AsRFFSli+zX2oMqUGvmy dLInQTEnnddiwXAEgrtu3BWhBvTT1bWROaKSoL97EUgfDy+5UjeA7qhZ4niQEHCOfr2Q v54w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ugbJF6PVIezR2iJKyzNiaymmGRktI+k6YpseyxVcufU=; b=KuDgrio9MBUs09xp8DbJ97r2cAA/Kzta/T+BGa6nqbjMLwGpttprFUy/ujVanrTLIq W5fch7ITV/mx/xP4i1PHwnxGaeM7IvPtkjv99+hHbHJ40hT0nYeGVMV1VIGptm45piic 22LkGEvbpfimhpzxzGF/eCB7h2H0qr5I87/gJV0Nwl3uRC1VU/YRvg2cD75cBTU35aNE s9H4mZE5qyybi+IUTX0WlIgDfp9ykW8go66UW1xb2UUDPJr6SocorvP36bPrztWtGd4I fPnGmi8UckN4M6fwbayWHaWqXrS8Nt6r74BdfFxW6QKnbJCRDq/2qcRsBVELdrQnXVxR Xsbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KQlU0YKs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id bf3-20020a170902b90300b0015f2b3bc97asm9106026plb.13.2022.06.28.04.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 04:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com Subject: [PATCH v5 2/2] target/xtensa: Use semihosting/syscalls.h Date: Tue, 28 Jun 2022 17:13:07 +0530 Message-Id: <20220628114307.697943-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628114307.697943-1-richard.henderson@linaro.org> References: <20220628114307.697943-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Remove the xtensa custom console handing and rely on the generic -semihosting-config handling of chardevs. Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 1 - hw/xtensa/sim.c | 3 - target/xtensa/xtensa-semi.c | 226 ++++++++---------------------------- 3 files changed, 50 insertions(+), 180 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ea66895e7f..99ac3efd71 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -612,7 +612,6 @@ void xtensa_translate_init(void); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_register_core(XtensaConfigList *node); -void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 946c71cb5b..5cca6a170e 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -87,9 +87,6 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine) xtensa_create_memory_regions(&sysram, "xtensa.sysram", get_system_memory()); } - if (serial_hd(0)) { - xtensa_sim_open_console(serial_hd(0)); - } return cpu; } diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 5375f106fc..79431f5a64 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -27,8 +27,10 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "chardev/char-fe.h" +#include "exec/gdbstub.h" #include "semihosting/semihost.h" +#include "semihosting/syscalls.h" +#include "semihosting/softmmu-uaccess.h" #include "qapi/error.h" #include "qemu/log.h" @@ -143,48 +145,21 @@ static uint32_t errno_h2g(int host_errno) return TARGET_EINVAL; } -typedef struct XtensaSimConsole { - CharBackend be; - struct { - char buffer[16]; - size_t offset; - } input; -} XtensaSimConsole; - -static XtensaSimConsole *sim_console; - -static IOCanReadHandler sim_console_can_read; -static int sim_console_can_read(void *opaque) +static void xtensa_cb(CPUState *cs, uint64_t ret, int err) { - XtensaSimConsole *p = opaque; + CPUXtensaState *env = cs->env_ptr; - return sizeof(p->input.buffer) - p->input.offset; + env->regs[3] = errno_h2g(err); + env->regs[2] = ret; } -static IOReadHandler sim_console_read; -static void sim_console_read(void *opaque, const uint8_t *buf, int size) +static void xtensa_select_cb(CPUState *cs, uint64_t ret, int err) { - XtensaSimConsole *p = opaque; - size_t copy = sizeof(p->input.buffer) - p->input.offset; - - if (size < copy) { - copy = size; + if (ret & G_IO_NVAL) { + xtensa_cb(cs, -1, EBADF); + } else { + xtensa_cb(cs, ret != 0, 0); } - memcpy(p->input.buffer + p->input.offset, buf, copy); - p->input.offset += copy; -} - -void xtensa_sim_open_console(Chardev *chr) -{ - static XtensaSimConsole console; - - qemu_chr_fe_init(&console.be, chr, &error_abort); - qemu_chr_fe_set_handlers(&console.be, - sim_console_can_read, - sim_console_read, - NULL, NULL, &console, - NULL, true); - sim_console = &console; } void xtensa_semihosting(CPUXtensaState *env) @@ -194,165 +169,64 @@ void xtensa_semihosting(CPUXtensaState *env) switch (regs[2]) { case TARGET_SYS_exit: + gdb_exit(regs[3]); exit(regs[3]); break; case TARGET_SYS_read: + semihost_sys_read(cs, xtensa_cb, regs[3], regs[4], regs[5]); + break; case TARGET_SYS_write: - { - bool is_write = regs[2] == TARGET_SYS_write; - uint32_t fd = regs[3]; - uint32_t vaddr = regs[4]; - uint32_t len = regs[5]; - uint32_t len_done = 0; - - while (len > 0) { - hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr); - uint32_t page_left = - TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1)); - uint32_t io_sz = page_left < len ? page_left : len; - hwaddr sz = io_sz; - void *buf = cpu_physical_memory_map(paddr, &sz, !is_write); - uint32_t io_done; - bool error = false; - - if (buf) { - vaddr += io_sz; - len -= io_sz; - if (fd < 3 && sim_console) { - if (is_write && (fd == 1 || fd == 2)) { - io_done = qemu_chr_fe_write_all(&sim_console->be, - buf, io_sz); - regs[3] = errno_h2g(errno); - } else if (!is_write && fd == 0) { - if (sim_console->input.offset) { - io_done = sim_console->input.offset; - if (io_sz < io_done) { - io_done = io_sz; - } - memcpy(buf, sim_console->input.buffer, io_done); - memmove(sim_console->input.buffer, - sim_console->input.buffer + io_done, - sim_console->input.offset - io_done); - sim_console->input.offset -= io_done; - qemu_chr_fe_accept_input(&sim_console->be); - } else { - io_done = -1; - regs[3] = TARGET_EAGAIN; - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s fd %d is not supported with chardev console\n", - is_write ? - "writing to" : "reading from", fd); - io_done = -1; - regs[3] = TARGET_EBADF; - } - } else { - io_done = is_write ? - write(fd, buf, io_sz) : - read(fd, buf, io_sz); - regs[3] = errno_h2g(errno); - } - if (io_done == -1) { - error = true; - io_done = 0; - } - cpu_physical_memory_unmap(buf, sz, !is_write, io_done); - } else { - error = true; - regs[3] = TARGET_EINVAL; - break; - } - if (error) { - if (!len_done) { - len_done = -1; - } - break; - } - len_done += io_done; - if (io_done < io_sz) { - break; - } - } - regs[2] = len_done; - } + semihost_sys_write(cs, xtensa_cb, regs[3], regs[4], regs[5]); break; - case TARGET_SYS_open: - { - char name[1024]; - int rc; - int i; - - for (i = 0; i < ARRAY_SIZE(name); ++i) { - rc = cpu_memory_rw_debug(cs, regs[3] + i, - (uint8_t *)name + i, 1, 0); - if (rc != 0 || name[i] == 0) { - break; - } - } - - if (rc == 0 && i < ARRAY_SIZE(name)) { - regs[2] = open(name, regs[4], regs[5]); - regs[3] = errno_h2g(errno); - } else { - regs[2] = -1; - regs[3] = TARGET_EINVAL; - } - } + semihost_sys_open(cs, xtensa_cb, regs[3], 0, regs[4], regs[5]); break; - case TARGET_SYS_close: - if (regs[3] < 3) { - regs[2] = regs[3] = 0; - } else { - regs[2] = close(regs[3]); - regs[3] = errno_h2g(errno); - } + semihost_sys_close(cs, xtensa_cb, regs[3]); break; - case TARGET_SYS_lseek: - regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]); - regs[3] = errno_h2g(errno); + semihost_sys_lseek(cs, xtensa_cb, regs[3], regs[4], regs[5]); break; case TARGET_SYS_select_one: { - uint32_t fd = regs[3]; - uint32_t rq = regs[4]; - uint32_t target_tv = regs[5]; - uint32_t target_tvv[2]; + int timeout, events; - struct timeval tv = {0}; + if (regs[5]) { + uint32_t tv_sec, tv_usec; + uint64_t msec; - if (target_tv) { - cpu_memory_rw_debug(cs, target_tv, - (uint8_t *)target_tvv, sizeof(target_tvv), 0); - tv.tv_sec = (int32_t)tswap32(target_tvv[0]); - tv.tv_usec = (int32_t)tswap32(target_tvv[1]); - } - if (fd < 3 && sim_console) { - if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) { - regs[2] = 1; - } else if (fd == 0 && rq == SELECT_ONE_READ) { - regs[2] = sim_console->input.offset > 0; - } else { - regs[2] = 0; + if (get_user_u32(tv_sec, regs[5]) || + get_user_u32(tv_usec, regs[5])) { + xtensa_cb(cs, -1, EFAULT); + return; } - regs[3] = 0; - } else { - fd_set fdset; - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - regs[2] = select(fd + 1, - rq == SELECT_ONE_READ ? &fdset : NULL, - rq == SELECT_ONE_WRITE ? &fdset : NULL, - rq == SELECT_ONE_EXCEPT ? &fdset : NULL, - target_tv ? &tv : NULL); - regs[3] = errno_h2g(errno); + /* Poll timeout is in milliseconds; overflow to infinity. */ + msec = tv_sec * 1000ull + DIV_ROUND_UP(tv_usec, 1000ull); + timeout = msec <= INT32_MAX ? msec : -1; + } else { + timeout = -1; } + + switch (regs[4]) { + case SELECT_ONE_READ: + events = G_IO_IN; + break; + case SELECT_ONE_WRITE: + events = G_IO_OUT; + break; + case SELECT_ONE_EXCEPT: + events = G_IO_PRI; + break; + default: + xtensa_cb(cs, -1, EINVAL); + return; + } + + semihost_sys_poll_one(cs, xtensa_select_cb, + regs[3], events, timeout); } break;