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PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(396003)(136003)(376002)(39860400002)(346002)(40470700004)(36840700001)(46966006)(70586007)(8676002)(7696005)(4326008)(70206006)(8936002)(186003)(82310400005)(426003)(47076005)(336012)(6916009)(40480700001)(44832011)(83380400001)(356005)(82740400003)(54906003)(40460700003)(316002)(2616005)(478600001)(36756003)(5660300002)(6666004)(26005)(9786002)(36860700001)(2906002)(7636003)(41300700001)(1076003)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 14:26:19.5813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72586925-0de9-4c2f-9e35-08da6a5bd060 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5211 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The Xilinx Versal board uses the arm,pl011 ip. However the axi port that it is connected to has a limitation that it allows only 32-bit accesses. So to differentiate we add a compatible. Add support for Uart used in Xilinx Versal SOCs as a platform device. Signed-off-by: Shubhrajyoti Datta Signed-off-by: Raviteja Narayanam --- Documentation/devicetree/bindings/serial/pl011.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index d8aed84abcd3..bf094ab93086 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -24,9 +24,13 @@ select: properties: compatible: - items: - - const: arm,pl011 - - const: arm,primecell + oneOf: + - items: + - const: arm,pl011 + - const: arm,primecell + - items: + - const: arm,pl011 + - const: arm,xlnx-uart # xilinx uart as platform device reg: maxItems: 1 From patchwork Wed Jul 20 14:26:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhrajyoti Datta X-Patchwork-Id: 592085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD0C1CCA480 for ; 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Wed, 20 Jul 2022 07:26:20 -0700 Envelope-to: git@xilinx.com, linux-serial@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, devicetree@vger.kernel.org Received: from [10.140.6.59] (port=55844 helo=xhdshubhraj40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1oEAeZ-0000jg-V7; Wed, 20 Jul 2022 07:26:20 -0700 From: Shubhrajyoti Datta To: CC: , , , , , Subject: [PATCH v2 2/2] serial: pl011: Add support for Xilinx Uart Date: Wed, 20 Jul 2022 19:56:12 +0530 Message-ID: <20220720142612.19779-3-shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220720142612.19779-1-shubhrajyoti.datta@xilinx.com> References: <20220720142612.19779-1-shubhrajyoti.datta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95942d39-92d2-4fb9-b71e-08da6a5bd218 X-MS-TrafficTypeDiagnostic: SA0PR02MB7418:EE_ X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230016)(4636009)(376002)(136003)(39860400002)(396003)(346002)(40470700004)(46966006)(36840700001)(70206006)(40460700003)(54906003)(316002)(336012)(6916009)(26005)(36860700001)(426003)(8676002)(47076005)(83380400001)(70586007)(82310400005)(36756003)(40480700001)(4326008)(44832011)(2906002)(186003)(6666004)(9786002)(8936002)(7696005)(41300700001)(478600001)(1076003)(2616005)(7636003)(82740400003)(356005)(5660300002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 14:26:22.4812 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95942d39-92d2-4fb9-b71e-08da6a5bd218 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT030.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7418 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Raviteja Narayanam The xilinx uart used in Versal SOC follows arm pl011 implementation with just a minor change in data bus width. The minimum data transaction width in Versal SOC is 32-bit as specified in the TRM (Chapter 39: Transaction attributes). Pl011 defaults to 16-bit in the driver. So, add the xilinx uart as platform device with properties specified in 'vendor_data' structure. Signed-off-by: Raviteja Narayanam Signed-off-by: Shubhrajyoti Datta --- drivers/tty/serial/amba-pl011.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 97ef41cb2721..096a56f64d17 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -152,6 +152,21 @@ static const struct vendor_data vendor_sbsa = { .fixed_options = true, }; +static const struct vendor_data vendor_xlnx = { + .reg_offset = pl011_std_offsets, + .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, + .fr_busy = UART01x_FR_BUSY, + .fr_dsr = UART01x_FR_DSR, + .fr_cts = UART01x_FR_CTS, + .fr_ri = UART011_FR_RI, + .access_32b = true, + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = false, +}; + #ifdef CONFIG_ACPI_SPCR_TABLE static const struct vendor_data vendor_qdt_qdf2400_e44 = { .reg_offset = pl011_std_offsets, @@ -2581,6 +2596,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, } OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); +OF_EARLYCON_DECLARE(pl011, "arm,xlnx-uart", pl011_early_console_setup); /* * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by @@ -2824,6 +2840,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) { struct uart_amba_port *uap; struct resource *r; + int xlnx_uart = 0; int portnr, ret; int baudrate; @@ -2834,6 +2851,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) if (pdev->dev.of_node) { struct device_node *np = pdev->dev.of_node; + xlnx_uart = of_device_is_compatible(np, "arm,xlnx-uart"); ret = of_property_read_u32(np, "current-speed", &baudrate); if (ret) return ret; @@ -2863,13 +2881,23 @@ static int sbsa_uart_probe(struct platform_device *pdev) #endif uap->vendor = &vendor_sbsa; + uap->port.ops = &sbsa_uart_pops; + + if (xlnx_uart) { + uap->vendor = &vendor_xlnx; + uap->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(uap->clk)) + return PTR_ERR(uap->clk); + + uap->port.ops = &amba_pl011_pops; + } + uap->reg_offset = uap->vendor->reg_offset; uap->fifosize = 32; uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; - uap->port.ops = &sbsa_uart_pops; uap->fixed_baud = baudrate; - snprintf(uap->type, sizeof(uap->type), "SBSA"); + snprintf(uap->type, sizeof(uap->type), "%s\n", (xlnx_uart ? "xlnx_uart" : "SBSA")); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -2893,6 +2921,7 @@ static int sbsa_uart_remove(struct platform_device *pdev) static const struct of_device_id sbsa_uart_of_match[] = { { .compatible = "arm,sbsa-uart", }, + { .compatible = "arm,xlnx-uart", }, {}, }; MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);