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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org Subject: [RFC PATCH v3 net-next 02/10] dt-bindings: net: dsa: hellcreek: add missing CPU port phy-mode/fixed-link to example Date: Sat, 6 Aug 2022 17:10:51 +0300 Message-Id: <20220806141059.2498226-3-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220806141059.2498226-1-vladimir.oltean@nxp.com> References: <20220806141059.2498226-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: VI1PR0802CA0016.eurprd08.prod.outlook.com (2603:10a6:800:aa::26) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6a15bbee-f854-4965-3b9b-08da77b5884c X-MS-TrafficTypeDiagnostic: DB8PR04MB6988:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230016)(4636009)(376002)(396003)(346002)(39860400002)(136003)(366004)(5660300002)(44832011)(7416002)(7406005)(186003)(1076003)(2616005)(38100700002)(38350700002)(83380400001)(6666004)(52116002)(6486002)(41300700001)(316002)(36756003)(6916009)(54906003)(6506007)(26005)(6512007)(66946007)(66556008)(66476007)(4326008)(8676002)(8936002)(478600001)(86362001)(2906002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aBJNKlyexdUYhyuYHDQElT+w4nA62Slz+np3s9xuStk/IdtekyS5VMyCHFBNiEsl+qZeJauMg1YbyE9/+6eMtILnXsgpDs4y4SaQEZzBeRBGKz7OAPMt58Xv3SG+iVHe8CDrVtXU6FzSEn5zOisGjRkvZBWks2Xsbjn6Hhpvk8Wq3m08pP9jXsHYYo6dH81tFXOnOO7yW566/NlsoNWj42f7sue/XYSUrnG5Cm5oV20ycPorlI6kTXpQY0B2QOwrDt/ibGSIuod9H0iFEvaeuhu3NpAOH3TeG9foLP4dfgXR8xtArI7UxawaV+Lkni6+jEcei7RCCb3Qo6GlfLMWnTvbFVjcEVJnSo2wTngmrzuBhnR6FiedPPvAV4ufJbEwmuXea7z7iaBFkB+z46jPfL0pNIGJGDkgC8lZvv5QewW95hw0yS3hAg8ZOrd7FDd+KREqHXTkKKhO/tBGXBh0aMdMvhQatErApcVZ8t2e3RnbFFtDlrF+ZH3WiokC8KojRzV0znqjj3mX+vf0GJN5QsvEwkOqPP47wUoI9psjbnHP6YJI7X2LyC/2bV6gg5xG7gf4dze95ugMhtLbghfDJiTuGz51WWD1vVb7htvhXzkN/MCfhqi9uKIgO93DihYeVX0b8TsKWxFomf1ZCsm+SDy4WFkM2y0yCIXGTen3ur3be6OkWj7OFTNYP5nY5l1Ilorayqr3maJHEmt4rDKfBGP5i4B6JoAgrqc+EOQkoyVcttgIFy4fXWJo3xTE/xnxjQ1uRwgoWQBqi9b+mgt9HcYlb4rdJWqkJfPEHRkbVr18zEpiRMPLMze35h/nfRd692QcvCTK5yDP55NKbn+sAowp6kfSxlK0AWUvJjjTVO/zV49WYjFBJ7uN9IbxbOZ16xcjf3RDFR7BAUT9pv2rvySnJM+cYO8QRtzn5uBvRvyWR9Awabs8xLkbC+gCUzf00AwEidlcC3l1B/vJheuixbOEo/HOcXBbkZa1WV4RCqCw0aGTySFKHqUsE68tlcjCFMbgmdvrp24DKOR2tCj31uyx+9ltYXdZ56cR/Tp2x/z+9Yxk9Wt/FYMy26RzO9D1ny+t9F1UjYIj2XzCsZKOZ9h9Y82uI5ubTE1tAv85hsY+sJ/RfapinFW1Azigshk/rPT3RZYFsdMIe91i68s2QVw8fV569Sitx+nYQG17lG5x/wm4MOICGDlNhcDEVbc7YPAf3+9kCrfMBQO4pFMjZDfO6AirKhSZNo7GhvgNZHV8MgzGmgDE79g7BoTislnbKtoQOImkrne0CCs6spFFTaEbklAKrRJPnqkSLGj4V6Bv5nNFUr8agzNWP3NfkGi8KoTJWbJZygVVOFJm9XeP2QSMLeb+/24boFEY3v2K1N6b8evAC7wRWTFKXw+RKKrR/z0Aap7oeaK71DFo7bPDXwyLdwfxlGRmHVAFCs+CwsLyFJSXLBZomcMnaongXegXKC6PDR0h2XNkfCbEnHuJ3AqyUR+MPOG3MDpo2nw5t0kDv2mtsVEIOhml51KeBz5+kR9XRqeg5xNbz+mnoDB3B7y2masZQzZ3gPpcQzycc0C4Fne1eXqpB845k15uDwtChVd1TlYcWvnBs1viQBnmJQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6a15bbee-f854-4965-3b9b-08da77b5884c X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2022 14:11:18.8173 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t/0CZXWiRgmHb3JmQB36TB6PxggFzTDPi8jiQ7WAC5dlqdqDgt8pKpEQBOWikYzEcK3eOXuBHOzJ/Sd/VEGF7g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6988 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Looking at hellcreek_phylink_get_caps(), I see that depending on whether is_100_mbits is set, speeds of 1G or of 100M will be advertised. The de1soc_r1_pdata sets is_100_mbits to true. The PHY modes declared in the capabilities are MII, RGMII and GMII. GMII doesn't support 100Mbps, and as for RGMII, it would be a bit implausible to me to support this PHY mode but limit it to only 25 MHz. So I've settled on MII as a phy-mode in the example, and a fixed-link of 100Mbps. As a side note, there exists such a thing as "rev-mii", because the MII protocol is asymmetric, and "mii" is the designation for the MAC side (expected to be connected to a PHY), and "rev-mii" is the designation for the PHY side (expected to be connected to a MAC). I wonder whether "mii" or "rev-mii" should actually be used here, since this is a CPU port and presumably connected to another MAC. Signed-off-by: Vladimir Oltean --- v2->v3: patch is new .../devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml index 228683773151..1ff44dd68a61 100644 --- a/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml +++ b/Documentation/devicetree/bindings/net/dsa/hirschmann,hellcreek.yaml @@ -93,6 +93,12 @@ examples: reg = <0>; label = "cpu"; ethernet = <&gmac0>; + phy-mode = "mii"; + + fixed-link { + speed = <100>; + full-duplex; + }; }; port@2 { From patchwork Sat Aug 6 14:10:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 595846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE9B2C19F2D for ; Sat, 6 Aug 2022 14:11:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231829AbiHFOLq (ORCPT ); Sat, 6 Aug 2022 10:11:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231939AbiHFOLl (ORCPT ); Sat, 6 Aug 2022 10:11:41 -0400 Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130071.outbound.protection.outlook.com [40.107.13.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F292712604; Sat, 6 Aug 2022 07:11:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LGvu0Q5Xc2kfymP4C9Axu2TrecoO9S9U5rh5mXVOk+HkR45imvBNNkqa9kidfvKHia4jA80m3+ApcTYF5ZW8dUGkwtx/K9DzSgpzdI+yFikRKW0PRlHdlUtZW4dcAA5g1/KjvTysBmLpOODTinNk2FQsSZdvw0iy4R9J7mq/TMxukeiuGNsBIQdm4fX28Me0Z+c/db9M1+Zz8d4VKZKTol5S8OWVmPS2oR/eX3HfnufsYG3OgGlPC7ISOh1Lp3BbixPqFebSmBDS9unjh0TC1vgntkzXxtxTxUrm8hIcI/tbdyUXoFq1ehDd6A8UXNRbNSS5sN4TA0PQZvIlOBHJLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9j1m9+uZLoW75wjkbY5+CJ6yI8Q1KYRDrzdtNSlMHWw=; b=FfyhrqZpzp3B5Crwk8JHKVCjGBGgLcBqBSdTD54WEL8OXC3iF/FN5tXqpJloCY7AWnajgtODRMIn44TlC1AKOAN6qXJXzY5bfZVhlqon6gG7BArDsNmMlkNuNPzQIdGz92cf2sNT2WMYzWOrlLB0iBrHc0OuQoRzjGBPEuPuxHZlkE+KaQDnaYHYyLSy7LLSM9MKOUADO9gJxGBndplQcNdieQylNuAjpWzqTfxxTmP6BhsMlS4WguPJMAWIZU+FYxl53or7voc1zaa8DNr55Y6bqCdedE7DL0EvyBpjjak/RVTzjN7+JejdtpBbKyDS33/PMZO7j3qnjImBTooZdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9j1m9+uZLoW75wjkbY5+CJ6yI8Q1KYRDrzdtNSlMHWw=; b=d4V+jY1r5tpnG6zXe/8z7M8C8tiPnwNN0fmw6jcaAJi8xzAHe68Nx6G+H0B6Mje9eQN2l6MyQUCIK7HTXmlzuFfdmc3zRLJzHP9AIkFIQfDP7Z/GTQZC7E2IP0BXNTipYXmhpK3mSIYrv80c8N6plPCBn1UBhKK76mesB8xRD2c= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) by DB8PR04MB6988.eurprd04.prod.outlook.com (2603:10a6:10:117::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.17; Sat, 6 Aug 2022 14:11:29 +0000 Received: from VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::71b7:8ed1:e4e0:3857]) by VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::71b7:8ed1:e4e0:3857%4]) with mapi id 15.20.5504.017; Sat, 6 Aug 2022 14:11:29 +0000 From: Vladimir Oltean To: netdev@vger.kernel.org Cc: devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org Subject: [RFC PATCH v3 net-next 04/10] dt-bindings: net: dsa: microchip: add missing CPU port phy-mode to example Date: Sat, 6 Aug 2022 17:10:53 +0300 Message-Id: <20220806141059.2498226-5-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220806141059.2498226-1-vladimir.oltean@nxp.com> References: <20220806141059.2498226-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: VI1PR0802CA0016.eurprd08.prod.outlook.com (2603:10a6:800:aa::26) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c21e9946-e191-4c0e-9d02-08da77b58ac1 X-MS-TrafficTypeDiagnostic: DB8PR04MB6988:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230016)(4636009)(376002)(396003)(346002)(39860400002)(136003)(366004)(5660300002)(44832011)(7416002)(7406005)(186003)(1076003)(2616005)(38100700002)(38350700002)(6666004)(52116002)(6486002)(41300700001)(316002)(36756003)(6916009)(54906003)(6506007)(26005)(6512007)(66946007)(66556008)(66476007)(4326008)(8676002)(8936002)(478600001)(86362001)(2906002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7XVZ3dh0ZPJb469s4yHaxcSdNqI6SZvIq5h435PijqjcLf7WK/uoUJJLtm3OVB1bZNvGgdYtznBgTM4s7VqKg7GKGhXmYTWUl6qmVj2XXb81/P4CtEgxz7R0fNrSMYZok12iQ0SMgEpYD+z2M80l+2bQN4Jn2bjPnxaOuidpPeVKQEgT4sVnhywUEazteXW1jH+hab8RdjMXivbxIQGBA04Q2LZa7ebJh6I8nHgz5vvqRzwC0iyjVbfObiRtr513IhHl+jVl8PpF9ssw79oFMoccw8OxCabtQOBK/oCgzY5m9vlAJfEKbaAcwODugxzYSW+ghuE1yMZX8Te2hQiieLWDK9yLztw3wdB96+LWIhyssTmKCwOuNw7RTR1Q8pvi3JNSVaenB9ArSH8Sge+q4X1Xlhue+b2/ch40taWUnCv8GhTBLqyHCkDMC8uwlX3I4ds6ikwAcz7tmtLPk1hmUlTzLqVe1fg5wOxlg1KF4xDxHQkdk4qKVo/RInhnJJpZFMthM505NTNAzp4QqcClJKyUGYOSQTtBQSG2Etjd8p0AxowbdIw7o+IyrQW7qheazBHuYvo+XGRgQL6W8Jhhsaeu3xerLYVd8f7v2rLW2N6lB9MvrhQFk4OyOGNdCV67ZGCoeHLpZx2/W2+5ZCmQGa339uDyYKKIqi4V1ACGjJvQF+T58xRbXsAegMhIQdFIBub6rujl9E3nPMw8WT06pSipmNcaE4yIFcYuGjwlEcmyp3LaYVnKSVAobKN04rqnFT69orV6fELjGPigkA5MwIUI8hhB8JRB5Ascr+grG9MbLZ66BIuM2wfFAMo8kiVmbtrDvdzZyqb102t9bhgqKtd8WmrhctGdDUp+1684qMRfs2c6kr/Q/DS+VLqLCOj5jJhHV2TNGCAXkGqCPORz35iaOM130dHKCvoK48uFKN3iVChMZM5bvCk7TGdyWcmjfdZXkOhZQdhHn1srSarohW7SD2cpTbElnNNep3lm8P2N2xPSB+aVcz7TzcjOkd4AA+prMIdHhjVYRcMStJcj6H/rbNe6Y9UfqK5NOZyiir1xzMYnPwN8AFvrU97vSCEgbBqlhGPvIEWjXSW1DVTy8hz6IyNW5IJNAc0LNhKSQ5ebThI1ZTwR5n/xRzTryDIKviU9M09BPhCF7kefavyB2MDhXu2exgpvkZZiknJ7j+5xyGhfxXxztqTjDBJMY/IgesRaIPWv2983Sy9vRV884/yf0izyezTJvl41UR9882lx9ubcwdEjHtLP5IYeR2SE62A/AK8x0n/8/EI+waFV254Fxqyw/3hYrQhHFXQogYG1AEChaYLK2f2cNFA9HMhmgnNAvLhz2GQHwMmnsWsScWu0dQcR9wiO3FfU51NmsRA/M0VBV5Yg3Aq/Tc0MLWjz6iJm9L9pOzGtI30XLew4R2R/aipY6KtDFGls58Xf8EUWVzA05pRcXI8HpocIvbWc4OmAPm5ChxDC7JdcQ5Zxb1fU3F/cRb3d5wsqdfMaQnG5wzVpCAaXivyVeAxzjNHYtoeBaBPh8aTa8C+al6ZJCddNrqZTSvDd+1kRopSiHHykCX7n+5RdCGDtyWUYb3gMTJoMnx0EGw4mo8etf4jAdQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c21e9946-e191-4c0e-9d02-08da77b58ac1 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2022 14:11:29.1447 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6lAtzE+yCBKsupQppTIQDJ4ZtVMyX4jgscwtQJpw/pIIh6VBpgWGzEHfPydyoq6UiMUkM/Sl0DavvF3t5Mz0xQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6988 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ksz_switch_chips[] element for KSZ9477 says that port 5 is an xMII port and it supports speeds of 10/100/1000. The device tree example does declare a fixed-link at 1000, and RGMII is the only one of those modes that supports this speed, so use this phy-mode. The microchip,ksz8565 compatible string is not supported by the microchip driver, however on Microchip's product page it says that there are 5 ports, 4 of which have internal PHYs and the 5th is an MII/RMII/RGMII port. It's a bit strange that this is port@6, but it is probably just the way it is. Select an RGMII phy-mode for this one as well. Signed-off-by: Vladimir Oltean --- v2->v3: patch is new Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index 6bbd8145b6c1..456802affc9d 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -109,6 +109,8 @@ examples: reg = <5>; label = "cpu"; ethernet = <ð0>; + phy-mode = "rgmii"; + fixed-link { speed = <1000>; full-duplex; @@ -146,6 +148,8 @@ examples: reg = <6>; label = "cpu"; ethernet = <ð0>; + phy-mode = "rgmii"; + fixed-link { speed = <1000>; full-duplex; From patchwork Sat Aug 6 14:10:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 595845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72CABC25B0C for ; Sat, 6 Aug 2022 14:12:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231940AbiHFOMQ (ORCPT ); Sat, 6 Aug 2022 10:12:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbiHFOLx (ORCPT ); Sat, 6 Aug 2022 10:11:53 -0400 Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130085.outbound.protection.outlook.com [40.107.13.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 792A212089; Sat, 6 Aug 2022 07:11:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YIubBo218Ne4bCUV+JssS6qxdOJc9Yjc+cz4lhdndbnNTp84h2Qbk1VNT3zUkht9c+CQGNdscoY6bcjeXOTMoj/cjX+p8KEcl3eOBBPRv5zOSY0MC3fPEwFprhsJ3u5/tAa8bx3pTRhzQORMGBFCr/LB2tluH5e7NSZ6Aays9k3LOLtKTbvxfSFTuOp1Mi58bw4ptUq9AmszIILuyCOgrgQjF+WVF6yvD2xw9t2NW+QdeOAbPvsqxq98kwRuKTFbFQH2IO5IkC0fASF2Yw8kmn7xogLbgXCXtmtQVSoKGQttDz2z/ywfuWliWWARd/LZ5i+ohj2vQIP4hSMgnXgVBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BOECcxE/wuitMXPLospeENTd0YtUoIuYKlSSxSnhZrA=; b=kFLqzpeeiQtaBcxCdkJCpP1q+K6UE/YJFPDnjS/40+LzJ+wM0eCw8gtJwWutcgNYjvq9yu+hYEf5W4TwIi1EJisZeSfqrvuIBX5oaEiMnJftnyR/Wu7dGOq7uMGmwWCdDGFQOPY/VUGQHHpt3Ap3GVlOP6L74tBTe02nAA7/Ofw4YXmJHb5gRp6fPe+yaky6ekmegeZWwBk/eZfc5/PxtVSquOU5k+pjE0TKvilP6VVXe2k3XQfwEg6yzbLsPbN1mkPBRJ3LfyIgmsbH5pcb6bwglsn8+Y1nxl6s+clGHa0KdQFbUhnyr8NbK5lFON1Mw0ohKJStCTOIEIslnGSI/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BOECcxE/wuitMXPLospeENTd0YtUoIuYKlSSxSnhZrA=; b=StWNPtRn+L04WNdQp/qGW/fMoF2TNCmLpYvjhPLvgkFP1n5Rb00zYglquqW3ZGvLEfZlgb9yYnuiD3nJ113obPs6saHmcoUJjX5kHNTuX+28zA1hbWMy19LLfn7VDwtFq3Rjf/W6GXUyNRU3Fv/dUuDwappxZWvvrVlh1LPj8Cc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) by DB8PR04MB6988.eurprd04.prod.outlook.com (2603:10a6:10:117::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5504.17; Sat, 6 Aug 2022 14:11:39 +0000 Received: from VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::71b7:8ed1:e4e0:3857]) by VI1PR04MB5136.eurprd04.prod.outlook.com ([fe80::71b7:8ed1:e4e0:3857%4]) with mapi id 15.20.5504.017; Sat, 6 Aug 2022 14:11:39 +0000 From: Vladimir Oltean To: netdev@vger.kernel.org Cc: devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org Subject: [RFC PATCH v3 net-next 06/10] dt-bindings: net: dsa: make phylink bindings required for CPU/DSA ports Date: Sat, 6 Aug 2022 17:10:55 +0300 Message-Id: <20220806141059.2498226-7-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220806141059.2498226-1-vladimir.oltean@nxp.com> References: <20220806141059.2498226-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: VI1PR0802CA0016.eurprd08.prod.outlook.com (2603:10a6:800:aa::26) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7f187b93-569f-4d5d-d70f-08da77b59469 X-MS-TrafficTypeDiagnostic: DB8PR04MB6988:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230016)(4636009)(376002)(396003)(346002)(39860400002)(136003)(366004)(5660300002)(44832011)(7416002)(7406005)(186003)(1076003)(2616005)(38100700002)(38350700002)(6666004)(52116002)(6486002)(41300700001)(316002)(36756003)(6916009)(54906003)(6506007)(26005)(6512007)(66946007)(66556008)(66476007)(4326008)(8676002)(8936002)(478600001)(86362001)(2906002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rdKZ7enVYRGPbnnebOw2wy1xVlt5NWpinKCUPyP0YBGZoYFoYYO2ltWecZuAGOElEiaKPHSvFxBLMnZ2KuApXZG3Vg+vRjk/A7WHXfY/d9nKkvHlBupimD0J3Uc3oPz+w76fOyVafmKsH6msoisO8Ot5mCBTltGMEGLply7XMtXnyWPMXVN7EeKnpYrkzxEPDpHKyWd1l3dJr5Br/SEfDPx/4vmCQCbK3p0rixujCmit30jFhVPaq0nVtVPMoNpwQBo7j2IQJhvoVht9M+qm1BUInjimt0S4YnCfFIurE3Ij1bh2Ym28s6zhmtv6iA3sFwxQmNfvR4RGOyaABFwpJxrd6olNUFsBlOPchEVTBYdOuVZFmn55YQbMiKx1FxMQgxF3QdukLVhJ2K08aDYaB/WBy6LzHcfFd4RgoGbHguZ7h2HyBH8AgAzZkKH4gBNZ2s9b1GcpjR0cIJmwcXX8W6hK5uhw2PRT09Aduoc0fp47SLfiZpS9oyPf+XLPaMVaaTqGEX5EXKp5W0+lDNCgaMsyDCGRnaogdb9i6T841fhG5rUH5WML4wZ7piR3hQQnuCEyJycmlxEYA020x9DkcvLI1G/0VsJBDE78XRqiF2o+3OMJcRnPYAJIDt0GUSeCydMAJ41CihYyylpOaqNC4TzvZ2VPuYXlCjX/VmoWRNl2u2rQx2KVvbjACpubTepM96RTTIYyjjUM1MBgb7478eZqHo2pJDAVQkPjSxbQEIX8utICzqUZmP2YMYLyMUi3ToV20UJUTDQjI7NNRX52UAsuNP8NhQGgXsILrvcKM3UYyDEyThdZOp6FqO2lrI3FBljXTboQT1VgW9tUW80SmRCIS7lTJBgQr3XLcPqf2rlTHWDS48r6njKjINtItLfyrtDyUr3rxutg1Xe1iFfGLe0B08+QVOQcR3oaSAz8BIgosHqxN/2m9HhsVCSj2m6+0+/S7+LWV6G87lhaS5trY6nAnxQxsxP64SbkJosOhI2YlIGIGkuM3O9ISWViMZHAbMQhQngZstKbkiwcVXdvZnv03fdhpGCEbE+XjxkwRyAaa2pNwcjvNYeM2ujfPEy1p0V1bYk8XJIVZKaF89AQgh68WJK7/TiXubmVxiH7nkijn/HEU/vhKlwSj7coBdrG1HgdDJWF7PviN/kLpDtcfLXkWVaVL+mjJupmZSPHLHnReeM9okODQGyCB4LPRhW6e9iwfVlfyuoQkl6JxiwNfO02kYpJvkPuUWswEc+Otfdt468Idqa0fmu9Vpu4nvEshAk0EhbwmLQiwhMp0hkOj4FCnby9MrZ4Xnd/NNfulH5H6MCm4nH9rImgSVoFcqIENJuH/VSJtkaj4XNkq1AqShn/gtU09Kh11z57cSrvZOzkGf5XS8d2hPhTh4ggHHtbKTG7UA9IXc/bGLc+wOOG7LeyXZpB8Cwb3KlK/JyHg15ecR2cVM/m+cQdRpV7EGJ+UZ8kQj2AL5XglcQMvYALLjumkMSTpt8vbgzg7NNIHMfe/i3XvCVkuDDWwMcQD0Gwxqtk0o0LZguQN/+XI/o7rD5lN7qEjKdgX3T7ZrHfJvzDB1httQy7wz0Or4vq+Md1Wd7MRBz4dYvwN8cU2GRT1g== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7f187b93-569f-4d5d-d70f-08da77b59469 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2022 14:11:39.1440 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NcEFgH8M1UP3ImMZcMvXi1H+iW8dznkkPf2gSsWHyIMd2MPXOE1FdUxMuWIqIJffwfJKvmh3Onej2iTci6RQng== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6988 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It is desirable that new DSA drivers are written to expect that all their ports register with phylink, and not rely on the DSA core's workarounds to skip this process. To that end, DSA is being changed to warn existing drivers when such DT blobs are in use, and to opt new drivers out of the workarounds. Introduce another layer of validation in the DSA DT schema, and assert that CPU and DSA ports must have phylink-related properties present. Suggested-by: Rob Herring Signed-off-by: Vladimir Oltean --- v2->v3: patch is new .../devicetree/bindings/net/dsa/dsa-port.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml b/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml index 09317e16cb5d..10ad7e71097b 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa-port.yaml @@ -76,6 +76,23 @@ properties: required: - reg +# CPU and DSA ports must have phylink-compatible link descriptions +if: + oneOf: + - required: [ ethernet ] + - required: [ link ] +then: + allOf: + - required: + - phy-mode + - oneOf: + - required: + - fixed-link + - required: + - phy-handle + - required: + - managed + additionalProperties: true ... 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org Subject: [RFC PATCH v3 net-next 08/10] net: dsa: avoid dsa_port_link_{,un}register_of() calls with platform data Date: Sat, 6 Aug 2022 17:10:57 +0300 Message-Id: <20220806141059.2498226-9-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220806141059.2498226-1-vladimir.oltean@nxp.com> References: <20220806141059.2498226-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: VI1PR0802CA0016.eurprd08.prod.outlook.com (2603:10a6:800:aa::26) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 74bb33f1-6e7d-4542-d2d0-08da77b59844 X-MS-TrafficTypeDiagnostic: DB8PR04MB6988:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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How this behaves will differ depending on whether the backing driver implements ->adjust_link() or not. If it doesn't, the "if (of_phy_is_fixed_link(dp->dn) || phy_np)" condition will return false, and dsa_port_link_register_of() will do nothing and return 0. If the driver does implement ->adjust_link(), the "if (of_phy_is_fixed_link(dp->dn))" condition will return false (dp->dn is NULL) and we will call dsa_port_setup_phy_of(). This will call dsa_port_get_phy_device(), which will also return NULL, and we will also do nothing and return 0. It is hard to maintain this code and make future changes to it in this state, so just suppress calls to these 2 functions if dp->dn is NULL. The only functional effect is that if the driver does implement ->adjust_link(), we'll stop printing this to the console: Using legacy PHYLIB callbacks. Please migrate to PHYLINK! but instead we'll always print: [ 8.539848] dsa-loop fixed-0:1f: skipping link registration for CPU port 5 This is for the better anyway, since "using legacy phylib callbacks" was misleading information - we weren't issuing _any_ callbacks due to dsa_port_get_phy_device() returning NULL. Signed-off-by: Vladimir Oltean --- v1->v2: patch is new v2->v3: none net/dsa/dsa2.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/net/dsa/dsa2.c b/net/dsa/dsa2.c index cac48a741f27..12479707bf96 100644 --- a/net/dsa/dsa2.c +++ b/net/dsa/dsa2.c @@ -469,10 +469,16 @@ static int dsa_port_setup(struct dsa_port *dp) dsa_port_disable(dp); break; case DSA_PORT_TYPE_CPU: - err = dsa_port_link_register_of(dp); - if (err) - break; - dsa_port_link_registered = true; + if (dp->dn) { + err = dsa_port_link_register_of(dp); + if (err) + break; + dsa_port_link_registered = true; + } else { + dev_warn(ds->dev, + "skipping link registration for CPU port %d\n", + dp->index); + } err = dsa_port_enable(dp, NULL); if (err) @@ -481,10 +487,16 @@ static int dsa_port_setup(struct dsa_port *dp) break; case DSA_PORT_TYPE_DSA: - err = dsa_port_link_register_of(dp); - if (err) - break; - dsa_port_link_registered = true; + if (dp->dn) { + err = dsa_port_link_register_of(dp); + if (err) + break; + dsa_port_link_registered = true; + } else { + dev_warn(ds->dev, + "skipping link registration for DSA port %d\n", + dp->index); + } err = dsa_port_enable(dp, NULL); if (err) @@ -577,11 +589,13 @@ static void dsa_port_teardown(struct dsa_port *dp) break; case DSA_PORT_TYPE_CPU: dsa_port_disable(dp); - dsa_port_link_unregister_of(dp); + if (dp->dn) + dsa_port_link_unregister_of(dp); break; case DSA_PORT_TYPE_DSA: dsa_port_disable(dp); - dsa_port_link_unregister_of(dp); + if (dp->dn) + dsa_port_link_unregister_of(dp); break; case DSA_PORT_TYPE_USER: if (dp->slave) { From patchwork Sat Aug 6 14:10:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 595843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEBD4C19F2D for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , Rob Herring , Krzysztof Kozlowski , Oleksij Rempel , Christian Marangi , John Crispin , Kurt Kanzenbach , Mans Rullgard , Arun Ramadoss , Woojung Huh , UNGLinuxDriver@microchip.com, Claudiu Manoil , Alexandre Belloni , George McCollister , DENG Qingfang , Sean Wang , Landen Chao , Matthias Brugger , Hauke Mehrtens , Martin Blumenstingl , Aleksander Jan Bajkowski , =?utf-8?q?Alvin_=C5=A0ipraga?= , Luiz Angelo Daros de Luca , Linus Walleij , Pawel Dembicki , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Geert Uytterhoeven , Russell King , =?utf-8?q?Marek_Beh=C3=BAn?= , Marcin Wojtas , Marek Vasut , linux-renesas-soc@vger.kernel.org, Frank Rowand Subject: [RFC PATCH v3 net-next 10/10] net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports Date: Sat, 6 Aug 2022 17:10:59 +0300 Message-Id: <20220806141059.2498226-11-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220806141059.2498226-1-vladimir.oltean@nxp.com> References: <20220806141059.2498226-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: VI1PR0802CA0016.eurprd08.prod.outlook.com (2603:10a6:800:aa::26) To VI1PR04MB5136.eurprd04.prod.outlook.com (2603:10a6:803:55::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6e09fc8d-a28a-4afb-a119-08da77b59b4b X-MS-TrafficTypeDiagnostic: DB8PR04MB6988:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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User ports would have integrated PHYs at an internal MDIO address that is derivable from the port number, and shared (DSA and CPU) ports would have an MII-style (serial or parallel) connection to another MAC. Phylib and then phylink were used to drive the internal PHYs, and this needed little to no description through the platform data structures. Bringing up the shared ports at the maximum supported link speed was the responsibility of the drivers. As a result of this, when these early drivers were converted from platform data to the new DSA OF bindings, there was no link information translated into the first DT bindings. https://lore.kernel.org/all/YtXFtTsf++AeDm1l@lunn.ch/ Later, phylink was adopted for shared ports as well, and today we have a workaround in place, introduced by commit a20f997010c4 ("net: dsa: Don't instantiate phylink for CPU/DSA ports unless needed"). There, DSA checks for the presence of phy-handle/fixed-link/managed OF properties, and if missing, phylink registration would be skipped. This is because phylink is optional for some drivers (the shared ports already work without it), but the process of starting to register a port with phylink is irreversible: if phylink_create() fails to find the fwnode properties it needs, it bails out and it leaves the ports inoperational (because phylink expects ports to be initially down, so DSA necessarily takes them down, and doesn't know how to put them back up again). DSA being a common framework, new drivers opt into this workaround willy-nilly, but the ideal behavior from the DSA core's side would have been to not interfere with phylink's process of failing at all. This isn't possible because of regression concerns with pre-phylink DT blobs, but at least DSA should put a stop to the proliferation of more of such cases that rely on the workaround to skip phylink registration, and sanitize the environment that new drivers work in. To that end, create a list of compatible strings for which the workaround is preserved, and don't apply the workaround for any drivers outside that list (this includes new drivers). In some cases, we make the assumption that even existing drivers don't rely on DSA's workaround, and we do this by looking at the device trees in which they appear. We can't fully know what is the situation with downstream DT blobs, but we can guess the overall trend by studying the DT blobs that were submitted upstream. If there are upstream blobs that have lacking descriptions, we take it as very likely that there are many more downstream blobs that do so too. If all upstream blobs have complete descriptions, we take that as a hint that the driver is a candidate for strict validation (considering that most bindings are copy-pasted). If there are no upstream DT blobs, we take the conservative route of skipping validation, unless the driver maintainer instructs us otherwise. The driver situation is as follows: ar9331 ~~~~~~ compatible strings: - qca,ar9331-switch 1 occurrence in mainline device trees, part of SoC dtsi (arch/mips/boot/dts/qca/ar9331.dtsi), description is not problematic. Verdict: opt into validation. b53 ~~~ compatible strings: - brcm,bcm5325 - brcm,bcm53115 - brcm,bcm53125 - brcm,bcm53128 - brcm,bcm5365 - brcm,bcm5389 - brcm,bcm5395 - brcm,bcm5397 - brcm,bcm5398 - brcm,bcm53010-srab - brcm,bcm53011-srab - brcm,bcm53012-srab - brcm,bcm53018-srab - brcm,bcm53019-srab - brcm,bcm5301x-srab - brcm,bcm11360-srab - brcm,bcm58522-srab - brcm,bcm58525-srab - brcm,bcm58535-srab - brcm,bcm58622-srab - brcm,bcm58623-srab - brcm,bcm58625-srab - brcm,bcm88312-srab - brcm,cygnus-srab - brcm,nsp-srab - brcm,omega-srab - brcm,bcm3384-switch - brcm,bcm6328-switch - brcm,bcm6368-switch - brcm,bcm63xx-switch I've found at least these mainline DT blobs with problems: arch/arm/boot/dts/bcm47094-linksys-panamera.dts - lacks phy-mode arch/arm/boot/dts/bcm47189-tenda-ac9.dts - lacks phy-mode and fixed-link arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts - lacks phy-mode and fixed-link arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts arch/arm/boot/dts/bcm953012er.dts arch/arm/boot/dts/bcm4708-netgear-r6250.dts arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts - lacks phy-mode and fixed-link arch/arm/boot/dts/bcm53016-meraki-mr32.dts - lacks phy-mode Verdict: opt all switches out of strict validation. bcm_sf2 ~~~~~~~ compatible strings: - brcm,bcm4908-switch - brcm,bcm7445-switch-v4.0 - brcm,bcm7278-switch-v4.0 - brcm,bcm7278-switch-v4.8 A single occurrence in mainline (arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi), part of a SoC dtsi, valid description. Florian Fainelli explains that most of the bcm_sf2 device trees lack a full description for the internal IMP ports. Verdict: opt the BCM4908 into strict validation, and opt out the rest. Note that even though BCM4908 has strict DT bindings, it still does not register with phylink on the IMP port due to it implementing ->adjust_link(). hellcreek ~~~~~~~~~ compatible strings: - hirschmann,hellcreek-de1soc-r1 No occurrence in mainline device trees. Kurt Kanzenbach confirms that the downstream device tree lacks phy-mode and fixed link, and needs work. Verdict: opt out of validation. lan9303 ~~~~~~~ compatible strings: - smsc,lan9303-mdio - smsc,lan9303-i2c 1 occurrence in mainline device trees: arch/arm/boot/dts/imx53-kp-hsc.dts - no phy-mode, no fixed-link Verdict: opt out of validation. lantiq_gswip ~~~~~~~~~~~~ compatible strings: - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip No occurrences in mainline device trees. Martin Blumenstingl confirms that the downstream OpenWrt device trees lack a proper fixed-link and need work, and that the incomplete description can even be seen in the example from Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt. Verdict: opt out of validation. microchip ksz ~~~~~~~~~~~~~ compatible strings: - microchip,ksz8765 - microchip,ksz8794 - microchip,ksz8795 - microchip,ksz8863 - microchip,ksz8873 - microchip,ksz9477 - microchip,ksz9897 - microchip,ksz9893 - microchip,ksz9563 - microchip,ksz8563 - microchip,ksz9567 - microchip,lan9370 - microchip,lan9371 - microchip,lan9372 - microchip,lan9373 - microchip,lan9374 5 occurrences in mainline device trees, all descriptions are valid. But we had a snafu for the ksz8795 and ksz9477 drivers where the phy-mode property would be expected to be located directly under the 'switch' node rather than under a port OF node. It was fixed by commit edecfa98f602 ("net: dsa: microchip: look for phy-mode in port nodes"). The driver still has compatibility with the old DT blobs. The lan937x support was added later than the above snafu was fixed, and even though it has support for the broken DT blobs by virtue of sharing a common probing function, I'll take it that its DT blobs are correct. Verdict: opt lan937x into validation, and the others out. mt7530 ~~~~~~ compatible strings - mediatek,mt7621 - mediatek,mt7530 - mediatek,mt7531 Multiple occurrences in mainline device trees, one is part of an SoC dtsi (arch/mips/boot/dts/ralink/mt7621.dtsi), all descriptions are fine. Verdict: opt into strict validation. mv88e6060 ~~~~~~~~~ compatible string: - marvell,mv88e6060 no occurrences in mainline, nobody knows anybody who uses it. Verdict: opt out of strict validation. mv88e6xxx ~~~~~~~~~ compatible strings: - marvell,mv88e6085 - marvell,mv88e6190 - marvell,mv88e6250 Device trees that have incomplete descriptions of CPU or DSA ports: arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi - lacks phy-mode arch/arm64/boot/dts/marvell/cn9130-crb.dtsi - lacks phy-mode and fixed-link arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts - lacks phy-mode arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts - lacks phy-mode arch/arm/boot/dts/vf610-zii-spb4.dts - lacks phy-mode arch/arm/boot/dts/vf610-zii-cfu1.dts - lacks phy-mode arch/arm/boot/dts/vf610-zii-dev-rev-c.dts - lacks phy-mode on CPU port, fixed-link on DSA ports arch/arm/boot/dts/vf610-zii-dev-rev-b.dts - lacks phy-mode on CPU port arch/arm/boot/dts/armada-381-netgear-gs110emx.dts - lacks phy-mode arch/arm/boot/dts/vf610-zii-scu4-aib.dts - lacks fixed-link on xgmii DSA ports and/or in-band-status on 2500base-x DSA ports, and phy-mode on CPU port arch/arm/boot/dts/imx6qdl-gw5904.dtsi - lacks phy-mode and fixed-link arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts - lacks phy-mode and fixed-link arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts - lacks phy-mode arch/arm/boot/dts/kirkwood-dir665.dts - lacks phy-mode arch/arm/boot/dts/kirkwood-rd88f6281.dtsi - lacks phy-mode arch/arm/boot/dts/orion5x-netgear-wnr854t.dts - lacks phy-mode and fixed-link arch/arm/boot/dts/armada-388-clearfog.dts - lacks phy-mode arch/arm/boot/dts/armada-xp-linksys-mamba.dts - lacks phy-mode arch/arm/boot/dts/armada-385-linksys.dtsi - lacks phy-mode arch/arm/boot/dts/imx6q-b450v3.dts arch/arm/boot/dts/imx6q-b850v3.dts - has a phy-handle but not a phy-mode? arch/arm/boot/dts/armada-370-rd.dts - lacks phy-mode arch/arm/boot/dts/kirkwood-linksys-viper.dts - lacks phy-mode arch/arm/boot/dts/imx51-zii-rdu1.dts - lacks phy-mode arch/arm/boot/dts/imx51-zii-scu2-mezz.dts - lacks phy-mode arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi - lacks phy-mode arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts - lacks phy-mode and fixed-link Verdict: opt out of validation. ocelot ~~~~~~ compatible strings: - mscc,vsc9953-switch - felix (arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi) is a PCI device, has no compatible string 2 occurrences in mainline, both are part of SoC dtsi and complete. Verdict: opt into strict validation. qca8k ~~~~~ compatible strings: - qca,qca8327 - qca,qca8328 - qca,qca8334 - qca,qca8337 5 occurrences in mainline device trees, none of the descriptions are problematic. Verdict: opt into validation. realtek ~~~~~~~ compatible strings: - realtek,rtl8366rb - realtek,rtl8365mb 2 occurrences in mainline, both descriptions are fine, additionally rtl8365mb.c has a comment "The device tree firmware should also specify the link partner of the extension port - either via a fixed-link or other phy-handle." Verdict: opt into validation. rzn1_a5psw ~~~~~~~~~~ compatible strings: - renesas,rzn1-a5psw One single occurrence, part of SoC dtsi (arch/arm/boot/dts/r9a06g032.dtsi), description is fine. Verdict: opt into validation. sja1105 ~~~~~~~ Driver already validates its port OF nodes in sja1105_parse_ports_node(). Verdict: opt into validation. vsc73xx ~~~~~~~ compatible strings: - vitesse,vsc7385 - vitesse,vsc7388 - vitesse,vsc7395 - vitesse,vsc7398 2 occurrences in mainline device trees, both descriptions are fine. Verdict: opt into validation. xrs700x ~~~~~~~ compatible strings: - arrow,xrs7003e - arrow,xrs7003f - arrow,xrs7004e - arrow,xrs7004f no occurrences in mainline, we don't know. Verdict: opt out of strict validation. Because there is a pattern where newly added switches reuse existing drivers more often than introducing new ones, I've opted for deciding who gets to opt into the workaround based on an OF compatible match table in the DSA core. The alternative would have been to add another boolean property to struct dsa_switch, like configure_vlan_while_not_filtering. But this avoids situations where sometimes driver maintainers obfuscate what goes on by sharing a common probing function, and therefore making new switches inherit old quirks. Side note, we also warn about missing properties for drivers that rely on the workaround. This isn't an indication that we'll break compatibility with those DT blobs any time soon, but is rather done to raise awareness about the change, for future DT blob authors. Cc: Rob Herring Cc: Frank Rowand Acked-by: Alvin Šipraga # realtek Signed-off-by: Vladimir Oltean --- v1->v2: print warnings even for drivers skipping phylink registration, move code placement v2->v3: reword commit message net/dsa/port.c | 175 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 170 insertions(+), 5 deletions(-) diff --git a/net/dsa/port.c b/net/dsa/port.c index 4b6139bff217..c07a7c69d5e0 100644 --- a/net/dsa/port.c +++ b/net/dsa/port.c @@ -1650,22 +1650,187 @@ static int dsa_shared_port_phylink_register(struct dsa_port *dp) return err; } +/* During the initial DSA driver migration to OF, port nodes were sometimes + * added to device trees with no indication of how they should operate from a + * link management perspective (phy-handle, fixed-link, etc). Additionally, the + * phy-mode may be absent. The interpretation of these port OF nodes depends on + * their type. + * + * User ports with no phy-handle or fixed-link are expected to connect to an + * internal PHY located on the ds->slave_mii_bus at an MDIO address equal to + * the port number. This description is still actively supported. + * + * Shared (CPU and DSA) ports with no phy-handle or fixed-link are expected to + * operate at the maximum speed that their phy-mode is capable of. If the + * phy-mode is absent, they are expected to operate using the phy-mode + * supported by the port that gives the highest link speed. It is unspecified + * if the port should use flow control or not, half duplex or full duplex, or + * if the phy-mode is a SERDES link, whether in-band autoneg is expected to be + * enabled or not. + * + * In the latter case of shared ports, omitting the link management description + * from the firmware node is deprecated and strongly discouraged. DSA uses + * phylink, which rejects the firmware nodes of these ports for lacking + * required properties. + * + * For switches in this table, DSA will skip enforcing validation and will + * later omit registering a phylink instance for the shared ports, if they lack + * a fixed-link, a phy-handle, or a managed = "in-band-status" property. + * It becomes the responsibility of the driver to ensure that these ports + * operate at the maximum speed (whatever this means) and will interoperate + * with the DSA master or other cascade port, since phylink methods will not be + * invoked for them. + * + * If you are considering expanding this table for newly introduced switches, + * think again. It is OK to remove switches from this table if there aren't DT + * blobs in circulation which rely on defaulting the shared ports. + */ +static const char * const dsa_switches_dont_enforce_validation[] = { +#if IS_ENABLED(CONFIG_NET_DSA_XRS700X) + "arrow,xrs7003e", + "arrow,xrs7003f", + "arrow,xrs7004e", + "arrow,xrs7004f", +#endif +#if IS_ENABLED(CONFIG_B53) + "brcm,bcm5325", + "brcm,bcm53115", + "brcm,bcm53125", + "brcm,bcm53128", + "brcm,bcm5365", + "brcm,bcm5389", + "brcm,bcm5395", + "brcm,bcm5397", + "brcm,bcm5398", + "brcm,bcm53010-srab", + "brcm,bcm53011-srab", + "brcm,bcm53012-srab", + "brcm,bcm53018-srab", + "brcm,bcm53019-srab", + "brcm,bcm5301x-srab", + "brcm,bcm11360-srab", + "brcm,bcm58522-srab", + "brcm,bcm58525-srab", + "brcm,bcm58535-srab", + "brcm,bcm58622-srab", + "brcm,bcm58623-srab", + "brcm,bcm58625-srab", + "brcm,bcm88312-srab", + "brcm,cygnus-srab", + "brcm,nsp-srab", + "brcm,omega-srab", + "brcm,bcm3384-switch", + "brcm,bcm6328-switch", + "brcm,bcm6368-switch", + "brcm,bcm63xx-switch", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_BCM_SF2) + "brcm,bcm7445-switch-v4.0", + "brcm,bcm7278-switch-v4.0", + "brcm,bcm7278-switch-v4.8", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK) + "hirschmann,hellcreek-de1soc-r1", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_LANTIQ_GSWIP) + "lantiq,xrx200-gswip", + "lantiq,xrx300-gswip", + "lantiq,xrx330-gswip", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_MV88E6060) + "marvell,mv88e6060", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_MV88E6XXX) + "marvell,mv88e6085", + "marvell,mv88e6190", + "marvell,mv88e6250", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON) + "microchip,ksz8765", + "microchip,ksz8794", + "microchip,ksz8795", + "microchip,ksz8863", + "microchip,ksz8873", + "microchip,ksz9477", + "microchip,ksz9897", + "microchip,ksz9893", + "microchip,ksz9563", + "microchip,ksz8563", + "microchip,ksz9567", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) + "smsc,lan9303-mdio", +#endif +#if IS_ENABLED(CONFIG_NET_DSA_SMSC_LAN9303_I2C) + "smsc,lan9303-i2c", +#endif + NULL, +}; + +static void dsa_shared_port_validate_of(struct dsa_port *dp, + bool *missing_phy_mode, + bool *missing_link_description) +{ + struct device_node *dn = dp->dn, *phy_np; + struct dsa_switch *ds = dp->ds; + phy_interface_t mode; + + *missing_phy_mode = false; + *missing_link_description = false; + + if (of_get_phy_mode(dn, &mode)) { + *missing_phy_mode = true; + dev_err(ds->dev, + "OF node %pOF of %s port %d lacks the required \"phy-mode\" property\n", + dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index); + } + + /* Note: of_phy_is_fixed_link() also returns true for + * managed = "in-band-status" + */ + if (of_phy_is_fixed_link(dn)) + return; + + phy_np = of_parse_phandle(dn, "phy-handle", 0); + if (phy_np) { + of_node_put(phy_np); + return; + } + + *missing_link_description = true; + + dev_err(ds->dev, + "OF node %pOF of %s port %d lacks the required \"phy-handle\", \"fixed-link\" or \"managed\" properties\n", + dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index); +} + int dsa_shared_port_link_register_of(struct dsa_port *dp) { struct dsa_switch *ds = dp->ds; - struct device_node *phy_np; + bool missing_link_description; + bool missing_phy_mode; int port = dp->index; + dsa_shared_port_validate_of(dp, &missing_phy_mode, + &missing_link_description); + + if ((missing_phy_mode || missing_link_description) && + !of_device_compatible_match(ds->dev->of_node, + dsa_switches_dont_enforce_validation)) + return -EINVAL; + if (!ds->ops->adjust_link) { - phy_np = of_parse_phandle(dp->dn, "phy-handle", 0); - if (of_phy_is_fixed_link(dp->dn) || phy_np) { + if (missing_link_description) { + dev_warn(ds->dev, + "Skipping phylink registration for %s port %d\n", + dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index); + } else { if (ds->ops->phylink_mac_link_down) ds->ops->phylink_mac_link_down(ds, port, MLO_AN_FIXED, PHY_INTERFACE_MODE_NA); - of_node_put(phy_np); + return dsa_shared_port_phylink_register(dp); } - of_node_put(phy_np); return 0; }