From patchwork Thu Aug 11 10:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 597068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6097EC19F2A for ; Thu, 11 Aug 2022 10:35:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234070AbiHKKfb (ORCPT ); Thu, 11 Aug 2022 06:35:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233931AbiHKKfa (ORCPT ); Thu, 11 Aug 2022 06:35:30 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68F9B26AD7; Thu, 11 Aug 2022 03:35:29 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27B7um7t008941; Thu, 11 Aug 2022 10:35:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=sJmwoWJdyH94Hft/N6niNsaDqqw+f822cVnLfxeyonM=; b=o1sTFgjgpiXdiSZt5Ayq2+daSp3gCzaAgz9bdXhBtkACW7ZC3cgX1fPGvVP+8Icg+csy xHG8ErpHYdC1jkiz6HgGTjokoRFcK4UyLM29aRrYNiLKipi1MneuMGs7t+tuBlJO2rZk o2hKENQEaXvaJhKyhws2VuxDNop7P/ij6Qt9LHZWr+CyzMKbgZsavN0GGJyGzBDmhHk6 boB2yZ4vx5h5mggv5rLZtMcT9SxQAWDwNmY2WdmaCcWR1JAFZrOSUTIxomlNbmnv4DpQ 9dK3ZeTSLfTC9AFUJfFZedWjY9iQd6ZVWpqVfgc5I19y/XGPKjnWrkuTHgG9xhxfmfpQ Nw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hvh25tfwv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Aug 2022 10:35:15 +0000 Received: from pps.filterd (NASANPPMTA01.qualcomm.com [127.0.0.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 27BAXb7t021435; Thu, 11 Aug 2022 10:35:14 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTPS id 3hshckskhf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 11 Aug 2022 10:35:14 +0000 Received: from NASANPPMTA01.qualcomm.com (NASANPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 27BAW9Yv019796; Thu, 11 Aug 2022 10:35:13 GMT Received: from stor-presley.qualcomm.com (stor-presley.qualcomm.com [192.168.140.85]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 27BAZDLu023821; Thu, 11 Aug 2022 10:35:13 +0000 Received: by stor-presley.qualcomm.com (Postfix, from userid 359480) id 7320F22752; Thu, 11 Aug 2022 03:35:13 -0700 (PDT) From: Can Guo To: quic_asutoshd@quicinc.com, quic_nguyenb@quicinc.com, quic_xiaosenh@quicinc.com, stanley.chu@mediatek.com, adrian.hunter@intel.com, bvanassche@acm.org, beanhuo@micron.com, avri.altman@wdc.com, mani@kernel.org, linux-scsi@vger.kernel.org, kernel-team@android.com, quic_cang@quicinc.com Cc: Andy Gross , Bjorn Andersson , "James E.J. Bottomley" , "Martin K. Petersen" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-kernel@vger.kernel.org (open list) Subject: [RFC PATCH v2 2/2] scsi: ufs-qcom: Add MCQ support Date: Thu, 11 Aug 2022 03:33:04 -0700 Message-Id: <1660213984-37793-3-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1660213984-37793-1-git-send-email-quic_cang@quicinc.com> References: <1660213984-37793-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nuV-Gpnb1tNzBa42ykar5-x7th82x1iL X-Proofpoint-ORIG-GUID: nuV-Gpnb1tNzBa42ykar5-x7th82x1iL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-11_05,2022-08-11_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 clxscore=1011 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208110030 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ESI and define Runtime and Operation definitions for MCQ. Co-developed-by: Asutosh Das Signed-off-by: Can Guo Signed-off-by: Asutosh Das --- drivers/ufs/host/ufs-qcom.c | 125 ++++++++++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 4 ++ 2 files changed, 129 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 473fad8..1e25d8d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -25,6 +25,8 @@ #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \ (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN) +#define MAX_SUPP_MAC 63 + enum { TSTBUS_UAWM, TSTBUS_UARM, @@ -1424,6 +1426,125 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, } #endif +static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, + unsigned long *ocqs) +{ + return -EINVAL; +} + +static int ufs_qcom_config_mcq_rop(struct ufs_hba *hba) +{ + struct ufshcd_mcq_rop_info_t *rop; + struct ufshcd_res_info_t *mem_res, *sqdao_res; + int i; + + mem_res = &hba->res[RES_MEM]; + sqdao_res = &hba->res[RES_MCQ_SQD]; + + if (!mem_res->base || !sqdao_res->base) + return -EINVAL; + + for (i = 0; i < ROP_MAX; i++) { + rop = &hba->mcq_rop[i]; + rop->offset = sqdao_res->resource->start - + mem_res->resource->start + 0x40 * i; + rop->stride = 0x100; + rop->base = sqdao_res->base + 0x40 * i; + } + + return 0; +} + +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN +static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct device *dev = msi_desc_to_dev(desc); + struct ufs_hba *hba = dev_get_drvdata(dev); + + ufshcd_mcq_config_esi(hba, msg); +} + +static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *__hba) +{ + struct ufs_hba *hba = __hba; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + u32 event_id = irq - host->esi_base; + struct ufs_hw_queue *hwq = &hba->uhq[event_id]; + + ufshcd_mcq_poll_cqe_nolock(hba, hwq); + + return IRQ_HANDLED; +} + +static int ufs_qcom_config_mcq_esi(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct msi_desc *desc; + struct msi_desc *failed_desc = NULL; + u32 reg; + int nr_irqs, ret; + + /* + * 1. We only handle CQs as of now. + * 2. Poll queues do not need ESI. + */ + nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; + ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, + ufs_qcom_write_msi_msg); + if (ret) + goto out; + + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + if (!desc->msi_index) + host->esi_base = desc->irq; + + ret = devm_request_irq(hba->dev, desc->irq, + ufs_qcom_mcq_esi_handler, + 0, "qcom-mcq-esi", hba); + if (ret) { + dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", + __func__, desc->irq, ret); + failed_desc = desc; + break; + } + } + + if (ret) { + /* Rewind */ + msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { + if (desc == failed_desc) + break; + devm_free_irq(hba->dev, desc->irq, hba); + } + } else { + if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && + host->hw_ver.step == 0) { + reg = ufshcd_readl(hba, REG_UFS_CFG3); + reg |= 0x1F000; + ufshcd_writel(hba, reg, REG_UFS_CFG3); + reg = ufshcd_readl(hba, REG_UFS_CFG3); + } + ufshcd_mcq_enable_esi(hba); + } + +out: + if (ret) + dev_warn(hba->dev, "Failed to request Platform MSI %d\n", ret); + return ret; +} + +#else +static int ufs_qcom_config_mcq_esi(struct ufs_hba *hba) +{ + return -EOPNOTSUPP; +} +#endif + +static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) +{ + return MAX_SUPP_MAC; +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1447,6 +1568,10 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .device_reset = ufs_qcom_device_reset, .config_scaling_param = ufs_qcom_config_scaling_param, .program_key = ufs_qcom_ice_program_key, + .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, + .config_mcq_rop = ufs_qcom_config_mcq_rop, + .config_mcq_esi = ufs_qcom_config_mcq_esi, + .get_hba_mac = ufs_qcom_get_hba_mac, }; /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a3..17c052e 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -53,6 +53,8 @@ enum { * added in HW Version 3.0.0 */ UFS_AH8_CFG = 0xFC, + + REG_UFS_CFG3 = 0x271C, }; /* QCOM UFS host controller vendor specific debug registers */ @@ -221,6 +223,8 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; struct gpio_desc *device_reset; + + int esi_base; }; static inline u32