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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id t3sm1770661pfa.50.2019.02.04.16.54.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Feb 2019 16:54:58 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: qcom: sdm845: Define IOMMU for sdhc 2 Date: Mon, 4 Feb 2019 16:54:52 -0800 Message-Id: <20190205005452.21438-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With apps_smmu initializing the SMMU we must specify iommus property for the sdhc controller. Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500") Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 340af13ec0c3..05577f08d18f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1539,6 +1539,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; + iommus = <&apps_smmu 0xa0 0xf>; status = "disabled"; };