From patchwork Thu Sep 8 17:11:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 603957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DECEDC54EE9 for ; Thu, 8 Sep 2022 17:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231243AbiIHRMD (ORCPT ); Thu, 8 Sep 2022 13:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231366AbiIHRMC (ORCPT ); Thu, 8 Sep 2022 13:12:02 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84B2CC59FA; Thu, 8 Sep 2022 10:12:01 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [70.107.189.129]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0AACD6601FA8; Thu, 8 Sep 2022 18:11:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662657120; bh=tCLoDMHCGsfN19AdOHQQnTF1e0UrnGsePgOOtqnqe10=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Io7NRETv7li8kv2CaqgkE0SvYcrV9BAHk9wa+4I/BtX77uBU9JeVamgWhup4V6igE srZccw/DxikEZKXS0hswSTd7IvkagOuCnsielUG+3SB0eG5znY68DmKhLlF9uDZz6n 60ChwN2KG1qPr1n0jTSA2Gjmxa7mjr0X9DBlIoOFisv7A2HZmKrpiqWNvKmSJPcj6G pmf7l/5YE0dUMHdsBc+t/Gsy4m5tHKAiGUJwzYy4r+7hMj+BJTQRcrlwWJ7PKMPNos fje0+4ofCQfXgPKweWGPgzhYwEc0zcZRj9eRJHeAIr9TrdJIleZEGXzErRXhGENdS2 35XhYF8S2VLVA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: Chen-Yu Tsai , AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/3] arm64: dts: mediatek: asurada: Add display regulators Date: Thu, 8 Sep 2022 13:11:51 -0400 Message-Id: <20220908171153.670762-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220908171153.670762-1-nfraprado@collabora.com> References: <20220908171153.670762-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the regulators present on the Asurada platform that are used to power the internal and external displays. Signed-off-by: Nícolas F. R. A. Prado --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 4b314435f8fd..1d99e470ea1a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -23,6 +23,42 @@ memory@40000000 { reg = <0 0x40000000 0 0x80000000>; }; + pp1000_dpbrdg: regulator-1v0-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_dpbrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 19 GPIO_ACTIVE_HIGH>; + }; + + pp1000_mipibrdg: regulator-1v0-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1000_mipibrdg_en_pins>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + }; + + pp1800_dpbrdg: regulator-1v8-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_dpbrdg_en_pins>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 126 GPIO_ACTIVE_HIGH>; + }; + /* system wide LDO 1.8V power rail */ pp1800_ldo_g: regulator-1v8-g { compatible = "regulator-fixed"; @@ -34,6 +70,30 @@ pp1800_ldo_g: regulator-1v8-g { vin-supply = <&pp3300_g>; }; + pp1800_mipibrdg: regulator-1v8-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_mipibrdg_en_pins>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 128 GPIO_ACTIVE_HIGH>; + }; + + pp3300_dpbrdg: regulator-3v3-dpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_dpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_dpbrdg_en_pins>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 26 GPIO_ACTIVE_HIGH>; + }; + /* system wide switching 3.3V power rail */ pp3300_g: regulator-3v3-g { compatible = "regulator-fixed"; @@ -56,6 +116,18 @@ pp3300_ldo_z: regulator-3v3-z { vin-supply = <&ppvar_sys>; }; + pp3300_mipibrdg: regulator-3v3-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp3300_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_mipibrdg_en_pins>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 127 GPIO_ACTIVE_HIGH>; + }; + /* separately switched 3.3V power rail */ pp3300_u: regulator-3v3-u { compatible = "regulator-fixed"; @@ -719,6 +791,48 @@ pins-wifi-kill { }; }; + pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + pp3300_wlan_pins: pp3300-wlan-pins { pins-pcie-en-pp3300-wlan { pinmux = ; From patchwork Thu Sep 8 17:11:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 603956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56841C6FA86 for ; Thu, 8 Sep 2022 17:12:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231783AbiIHRMK (ORCPT ); Thu, 8 Sep 2022 13:12:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231799AbiIHRMG (ORCPT ); Thu, 8 Sep 2022 13:12:06 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFE13C59FF; Thu, 8 Sep 2022 10:12:04 -0700 (PDT) Received: from notapiano.myfiosgateway.com (unknown [70.107.189.129]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 515486601F99; Thu, 8 Sep 2022 18:12:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662657123; bh=O6Q6pQLSe215V4afYGc/Z7qOQ/faIT1gKwtDzzYCHdY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UuZXr7ryQqAQ8jwQdLPJnw8K+vSwFlAsJoPNZk4pVXjUB+7fpq2wUKQocv3BXVyTe uiY96G6ooylMqN+c5PXIyU7q0t9Hh5WB46YqYnxGYNqBLP+F5SVtHZcAbvqUeRf2lM RNjmwnLHdr2ITaPKaka7c5gykGqQSbxRjo/9+9EJMInEsUx1N82m7FHXV63hQhlJuw Y6ZjCOLOsYRzK7kZPKZ9sNpoQ1Vc87WNvSUi4LwxYiJL50CHNZGfyhAjZVXBR21NqR 5Re6hH0nRa86G+wnbfwo4vHFOV6Of964YTn5THyAsov+wO4ta30RZxUubUTcZI9ZxB 2z1v8vHZmkdkw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: Chen-Yu Tsai , AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 3/3] arm64: dts: mediatek: asurada: Enable internal display Date: Thu, 8 Sep 2022 13:11:53 -0400 Message-Id: <20220908171153.670762-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20220908171153.670762-1-nfraprado@collabora.com> References: <20220908171153.670762-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The asurada platform has an ANX7625 bridge connecting the DSI's output to the internal eDP panel. Add and enable these devices in order to get a usable internal display. Signed-off-by: Nícolas F. R. A. Prado --- .../boot/dts/mediatek/mt8192-asurada.dtsi | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 33ef55b6dbe1..fde8548f67ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -200,6 +200,14 @@ wifi_restricted_dma_region: wifi@c0000000 { }; }; +&dsi0 { + status = "okay"; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; +}; + &i2c0 { status = "okay"; @@ -248,6 +256,53 @@ &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&pp3300_mipibrdg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_mipibrdg>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; }; &i2c7 { @@ -258,6 +313,10 @@ &i2c7 { pinctrl-0 = <&i2c7_pins>; }; +&mipi_tx0 { + status = "okay"; +}; + &mmc0 { status = "okay"; @@ -589,6 +648,20 @@ &pio { "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + anx7625_pins: anx7625-default-pins { + pins-out { + pinmux = , + ; + output-low; + }; + + pins-in { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + cr50_int: cr50-irq-default-pins { pins-gsc-ap-int-odl { pinmux = ;