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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2022 12:57:05.3827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f93da4f4-820e-4acd-dd0d-08daa150f1ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7579 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Create new SoC data structure for Tegra234 platforms. Additional features, tap value configurations are added/ updated for Tegra234 platform hence separate Tegra194 and Tegra234 SoC data. Signed-off-by: Aniruddha Tvs Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, From patchwork Wed Sep 28 12:56:46 2022 Content-Type: text/plain; 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Wed, 28 Sep 2022 05:56:57 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 28 Sep 2022 05:56:56 -0700 Received: from pshete-ubuntu.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Wed, 28 Sep 2022 05:56:53 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v6 2/4] mmc: sdhci-tegra: Add support to program MC stream ID Date: Wed, 28 Sep 2022 18:26:46 +0530 Message-ID: <20220928125648.19636-2-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220928125648.19636-1-pshete@nvidia.com> References: <20220928125648.19636-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT007:EE_|IA1PR12MB6531:EE_ X-MS-Office365-Filtering-Correlation-Id: ae831d81-46e1-45aa-be44-08daa150f4e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2022 12:57:10.3823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae831d81-46e1-45aa-be44-08daa150f4e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6531 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SMMU clients are supposed to program stream ID from their respective address spaces instead of MC override. Define NVQUIRK_PROGRAM_STREAMID and use it to program SMMU stream ID from the SDMMC client address space. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a6c5bbae77b4..60ce3e80f248 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -25,6 +25,10 @@ #include #include #include +#ifdef CONFIG_IOMMU_API +#include +#include +#endif #include @@ -94,6 +98,8 @@ #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -121,6 +127,7 @@ #define NVQUIRK_HAS_TMCLK BIT(10) #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) +#define NVQUIRK_PROGRAM_STREAMID BIT(12) /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 @@ -177,6 +184,9 @@ struct sdhci_tegra { bool enable_hwcq; unsigned long curr_clk_rate; u8 tuned_tap_delay; +#ifdef CONFIG_IOMMU_API + u32 streamid; +#endif }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -1564,6 +1574,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104 | + NVQUIRK_PROGRAM_STREAMID | NVQUIRK_HAS_TMCLK, .min_tap_delay = 95, .max_tap_delay = 111, @@ -1775,6 +1786,25 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_add_host; + /* Program MC streamID for DMA transfers */ +#ifdef CONFIG_IOMMU_API + if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + struct iommu_fwspec *fwspec; + + fwspec = dev_iommu_fwspec_get(&pdev->dev); + if (fwspec == NULL) { + dev_warn(mmc_dev(host->mmc), + "iommu fwspec is NULL, continue without stream ID\n"); + } else { + tegra_host->streamid = fwspec->ids[0] & 0xff; + tegra_sdhci_writel(host, tegra_host->streamid | + FIELD_PREP(GENMASK(15, 8), + tegra_host->streamid), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + } +#endif + return 0; err_add_host: @@ -1861,6 +1891,10 @@ static int sdhci_tegra_suspend(struct device *dev) static int sdhci_tegra_resume(struct device *dev) { struct sdhci_host *host = dev_get_drvdata(dev); +#ifdef CONFIG_IOMMU_API + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); +#endif int ret; ret = mmc_gpio_set_cd_wake(host->mmc, false); @@ -1871,6 +1905,16 @@ static int sdhci_tegra_resume(struct device *dev) if (ret) return ret; + /* Re-program MC streamID for DMA transfers */ +#ifdef CONFIG_IOMMU_API + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + tegra_sdhci_writel(host, tegra_host->streamid | + FIELD_PREP(GENMASK(15, 8), + tegra_host->streamid), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } +#endif + ret = sdhci_resume_host(host); if (ret) goto disable_clk; From patchwork Wed Sep 28 12:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 610765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC8EC04A95 for ; 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Wed, 28 Sep 2022 05:56:57 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v6 3/4] mmc: sdhci-tegra: Issue CMD and DAT resets together Date: Wed, 28 Sep 2022 18:26:47 +0530 Message-ID: <20220928125648.19636-3-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220928125648.19636-1-pshete@nvidia.com> References: <20220928125648.19636-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT047:EE_|PH8PR12MB7109:EE_ X-MS-Office365-Filtering-Correlation-Id: 30b04e38-fe1a-4517-4133-08daa150f634 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZSq9ooNrVUUtEaJx4ROhbl+ZcG3qnj4+wtQxcMKlGmlt50IhvgQDrOk5Iv0M9KEV+9CBtJAN/UlwV19R1XWoN+TIct13YQjTUTjAacobIE16XQP61WYtaR0rb2l3NSFi0j8EHqqrSNVqLGm2OxwtswZDc3RwamhiKU7ag9n8YhvQwqjmmYEqxLSObld8KmMqMaF1wr23j9CG77hy6C1KEyDtl2w+ms8rrFt+IoWLsJjZL0LOa8qxCsEk2W9WcuTg0QgNFPQwX6qAecn/2hH+U3Tz9C5Dn/24+zIKqLTnO6VjwZfJT5UHubDpYJXT4VGJrDw7Lt8Y77MVIj0UJCMK+4+XHVaIqBhJk9S/MDC+nTrvlCWMMdddk40pbIMRCwE0LVke9zM0yNkPJmqmrHslxmyzWo8U1qBqcH8PIn8Dx/nmt4j8YFhIWBRke3VX7G7eI/8jWMeCpCKJrxjOpzNFtj0gHZwThFNGT4Eydw8iiRgFQrndFxbx3VYCe+hDZg2z5Y2cSvedd54SGKq8f/9wAmL0Y7ukGfhaKaGpikiIQ1+ZjjfeIei+4IK53ZgICW5btMxubwBfoOJ8ypwA/EGh6P/ABm3MJxgU3mkaypuWpx0zfX37h45sAVtQnkjeNfa6HD88lJPwfKyWQ/ANaP2K4ffR0DeXMIKC1Oj7de4uc9huKNl5Im3Q7kEMkQXzMa/dLpgnTK9StzS8U416gmW9w027X/Wql6k9M1NcwVXeAfDHnJjDbo+cjo/BlytLXpXQG9y6WiRUp3r6mhOBPJWIQg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(40470700004)(46966006)(36840700001)(6666004)(82310400005)(2616005)(336012)(186003)(47076005)(5660300002)(26005)(107886003)(82740400003)(83380400001)(426003)(1076003)(7696005)(2906002)(36860700001)(40480700001)(41300700001)(110136005)(54906003)(40460700003)(478600001)(8936002)(8676002)(70586007)(316002)(70206006)(36756003)(4326008)(356005)(7636003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2022 12:57:12.4234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30b04e38-fe1a-4517-4133-08daa150f634 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7109 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. SDHCI controller FSM goes into bad state due to rapid SD card hot-plug event. Issuing reset on the CMD FSM before DATA FSM results in kernel panic, hence add support to issue CMD and DAT resets together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 5 +++++ drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 60ce3e80f248..283f702b4993 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1535,7 +1535,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2b5dda521b0e..8512a69f1aae 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -270,6 +270,11 @@ enum sdhci_reset_reason { static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason) { + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + return; + } switch (reason) { case SDHCI_RESET_FOR_INIT: sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index d750c464bd1e..6a5766774b05 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -478,6 +478,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Wed Sep 28 12:56:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 610440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 137ADC54EE9 for ; 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Wed, 28 Sep 2022 05:57:00 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v6 4/4] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction Date: Wed, 28 Sep 2022 18:26:48 +0530 Message-ID: <20220928125648.19636-4-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220928125648.19636-1-pshete@nvidia.com> References: <20220928125648.19636-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT011:EE_|IA1PR12MB7519:EE_ X-MS-Office365-Filtering-Correlation-Id: 49027dd5-3e75-4a17-1898-08daa150f8b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: V6Icy72QRsza3TA0Fb4igcL+42ovkFaALXcJEvwHFRiQpwGBCaMEYj2R/SACGcBZ+N0eCuCAtWg4JQ1xkWKMAEVF9GDcY9tCnSwGNgomgxZrV0UcjOu1+658R0FosDUEIgh+X8+j1lsIG3K5HltDUF7sGyjuHBDVP3znx0+2g/3RBjhkkAa/7okTfGKJ5bqDeGwwIC+JeifY4u2VaQB4aLs90qNELQt4UJVRtoVbjdDgq3vZML12rjnNM9PY5j/z9kK0z5xYtLpK9UueLtHDnnY6R5D63ietYQ4fDtXqQwv0uISyYNHaj1lTUp1UyRUqlcl3DhgI0ss/LDeBZftqClODrj/anAaQbH8BaB4mu7oBxuxNVyXh/GWcDYk+Mrrc+8tlnXej4v9qXKU4FQ3kvfAypCCX4vBj9OBmuGeFnmMIhXzMSPyCGRRAxf9Hr6l3SB5/RLDQ/y8lts/prof4aaiVhsULVC9t3u1vH3qSZwsLVb0tbxuoW8RrI1gQJdAqU67HvJOIvFfqIRns5Oizwju/XbQRaSKUEhfc9SdYGDbUL6YWGC3YiKNeC12TRmpCD8YHy91SBh4LHKu00bRJaaNjQHVRa2QR1YTyNMDZcw9GZD0s6z/rJNOmqmtcRqb5t3Da8eOnTtHC6ULptw56zvVx99ofErIGuV9AZjF9sZhJjeliwEbJcDUHz/kQuHD7qIKC/K4fYHl9f5Er2wKVE/I1bRjS9zxbojIpDZjCpS2+BH/j0ZPr0aN1tNJYpuaU0eOWr/6Xpwfs/wAO/dIjNA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(7696005)(5660300002)(426003)(478600001)(83380400001)(107886003)(6666004)(41300700001)(47076005)(1076003)(186003)(2906002)(26005)(82310400005)(40460700003)(40480700001)(336012)(54906003)(70586007)(2616005)(70206006)(8676002)(8936002)(110136005)(316002)(4326008)(7636003)(86362001)(356005)(36860700001)(82740400003)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2022 12:57:16.7613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49027dd5-3e75-4a17-1898-08daa150f8b7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7519 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Ensure tegra_host member "curr_clk_rate" holds the actual clock rate instead of requested clock rate for proper use during tuning correction algorithm. Actual clk rate may not be the same as the requested clk frequency depending on the parent clock source set. Tuning correction algorithm depends on certain parameters which are sensitive to current clk rate. If the host clk is selected instead of the actual clock rate, tuning correction algorithm may end up applying invalid correction, which could result in errors Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 283f702b4993..8739cd6a702c 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -783,7 +783,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) dev_err(dev, "failed to set clk rate to %luHz: %d\n", host_clk, err); - tegra_host->curr_clk_rate = host_clk; + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); if (tegra_host->ddr_signaling) host->max_clk = host_clk; else