From patchwork Wed Mar 13 18:39:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160265 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14636966jad; Wed, 13 Mar 2019 11:40:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZwFldLOkn7XHvvsMcSmngxxEtveQP27wo1I2BTeBpZf93Dnm3k002Xs0SYsC0g54pHzr/ X-Received: by 2002:a63:234c:: with SMTP id u12mr42197227pgm.282.1552502417281; Wed, 13 Mar 2019 11:40:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502417; cv=none; d=google.com; s=arc-20160816; b=xpAvsTB5QVwTHfIG6Vvcpvos8bWwW+CJ5Hob7x7MgfrrMQyHGWYrcTcAwjElGx8Xx0 WJOuUm9Wqh60ba1wVijCHZWnsNVyhkuUx80u740b5pCkz7tPBifuz29ieXUGwKD7aEE4 2zhQVEDlIH9KrDhCriUNAFuhZi37au0EO+tRKRYCdoS6htBc3TrLiyz2RtVtcjy/Z7bN /RzG9V/HHrcdlgQQK+tSBeYz+fHrdnNEcTdAmd+V0ULXMaH4QSKPj0Z852KdwmXq5EPv Dlp0QF95mNqFa08d3zwG1BMhZw+LFXMKr2gV9eNbBh1e06Zp8i4T6QW6iw03zcFxrD4b fEeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7OCibVDj3ON11Iv/B5fQbr5wmXHceO6Y9v3ZEb/PvXw=; b=oHlqAJMbhI6MsQ1wwac0iyEpP+SRypCC+keV9BNx8rxX9IeEqWvdJ4PwFTTKq9pS0x U8UOykKz5HHYcaSB8ybpX9Bo4/byIj6g7uQxJGaq+zX2bCMEHdoaH4PmG4vBsFU9WtkB LR78kWAaFjbInQce0h14EpZUgofSas8ipKc7IGHi544qXcBXRZtIV5jKyj+nqxOAEgdo 2H7s6cN4AVYU4MQypSr1miv139phAX206TDs6iKvjLiIqDP/wxNuB4b2X6+Q3C7kJbqn 74maQwi9FrHKpLSgIMnZJl+Wvt80dMi6/Q43fFPMFVc8xHHDUHIUWY1AcZyFeJBwiI0c OjIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GZFKU34S; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i4si10114961pgs.408.2019.03.13.11.40.17; Wed, 13 Mar 2019 11:40:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GZFKU34S; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727136AbfCMSkO (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:14 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:32918 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727116AbfCMSkO (ORCPT ); Wed, 13 Mar 2019 14:40:14 -0400 Received: by mail-wr1-f66.google.com with SMTP id i8so3165653wrm.0 for ; Wed, 13 Mar 2019 11:40:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7OCibVDj3ON11Iv/B5fQbr5wmXHceO6Y9v3ZEb/PvXw=; b=GZFKU34S2Lbx6DqysakGu7w/AXr0EKkf9jtsvsWBUqgpXPcOPQq7742J26yfxhbR// Nx/zswMUYxhTce7T9oOxQDeDcg/5M9lBp9f76DS0hAzhCGv2ONEUQL+BIxA4p2TyWxCA 0KthCXFbxL/BweQb3SDsBHJKaGTbohGVD5x5vkp8AkKIquvjxDl1E2Gtsb5l/DxCmMru xYyrOXcsVU6/F4vwpVp26+TtVzUrb3oB25sNYdfYfdBHYxeEJ6NPHJwZ40NbQNPz4Apo lXqSb8x9aWtTtDNe7dyEMJV6x9izYW3ezMOx71YmTAbWe1cwzXpWyOCaixAYZU141O8T RlTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7OCibVDj3ON11Iv/B5fQbr5wmXHceO6Y9v3ZEb/PvXw=; b=BSR8Z+B0PDMmVM1VhtU1xtfd5gEkO80K8RQNOPR8RlDdFkZWCLVsNUYgxI4t80mWGo SDPLXuCofPVfpGakgF47HXX0gd9XgOnzsu/EB0LjCF6dzDRODa597b6l7gNCG5stVZ7c RJV9v9Bp2orUadh/NgV05oTV+/s9NKre2XpBzFEKtLT1IeJ6w22k4xtre2he7uUWVQZ2 SXYpIOn4e+FN3hi0dSALU/F0yCF18+6KrvFsq4crkueRXu0b+ub8DLzyxokvUUTfIC2o YvE7V2KBGT66K39HKyiMO4wL+4WiP8AEeadol6Aa3tv+Cemy4EJoxPw4Yhzeqc9QvJ3J zs9A== X-Gm-Message-State: APjAAAU2bxsGtiSqQKL/8Nz+qDgEMXxg9XUxwCcP0mhXGHL5v05fh8wb Rmq9+U+J7jE5ExWNww/ZF1OHng== X-Received: by 2002:a05:6000:8b:: with SMTP id m11mr27770411wrx.243.1552502412067; Wed, 13 Mar 2019 11:40:12 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:11 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 1/6] iio: gyro: add DT bindings to fxas21002c Date: Wed, 13 Mar 2019 18:39:57 +0000 Message-Id: <20190313184002.2501-2-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for the FXAS21002C gyroscope. Signed-off-by: Rui Miguel Silva --- .../bindings/iio/gyroscope/nxp,fxas21002c.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.txt -- 2.20.1 diff --git a/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.txt b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.txt new file mode 100644 index 000000000000..68b4cd283d1d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.txt @@ -0,0 +1,26 @@ +* NXP FXAS21002C Gyroscope device tree bindings + +http://www.nxp.com/products/sensors/gyroscopes/3-axis-digital-gyroscope:FXAS21002C + +Required properties: + - compatible : should be "nxp,fxas21002c" + - reg : the I2C address of the sensor or SPI chip select number for the + device. + - vdd-supply: phandle to the regulator that provides power to the sensor. + - vddio-supply: phandle to the regulator that provides power to the bus. + +Optional properties: + - reset-gpios : gpio used to reset the device, see gpio/gpio.txt + - interrupts : device support 2 interrupts, INT1 and INT2. + See interrupt-controller/interrupts.txt + - interrupt-names: should contain "INT1" or "INT2", the gyroscope interrupt + line in use. + +Example: + +gyroscope@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + vdd-supply = <®_peri_3p15v>; + vddio-supply = <®_peri_3p15v>; +}; From patchwork Wed Mar 13 18:39:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160270 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14637172jad; Wed, 13 Mar 2019 11:40:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqzha3mqKah0o7Mx4TyqxuUp67b/LVL9Ff5r7102xqsJFeak0jfhNKEpdhajDLq+HcI1lhBn X-Received: by 2002:aa7:8d43:: with SMTP id s3mr10109771pfe.118.1552502429836; Wed, 13 Mar 2019 11:40:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502429; cv=none; d=google.com; s=arc-20160816; b=NxmgCjsrgk3CS/N0HzcRlC0zGv3OMpe5MGOm5/LY1BVG4M5AggQxRkXzlkmU50766a prHi73pzH8xYQ2xMKil6Qx/86srO9Y+r5eEFzY4Zr+EAgevrEkKxD7Hs1gB5bR5C622h GMSSDkfcEo7C6OOTzjdKnupOVCtFBc7ZQ3D6wNFgmlzUfltumkE2iuNbi1Q/MWAaH8/F 0nZg2Z4Ed4/gD/gx/PT+eh+DUN12fRXK5q+Mqw7e6aX+McMSPigiz6IqdYvQHZgRFv17 oEHdH0Nnhk2x/h1u7rl8+oAddiWmLRSh8q/uUuBbb36mFjJgYioyo1CKQw3fhJC1NGvc TW9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9iTYSXu9st4Th+KT6KsDMLzzJmppLHVZpX37c7/nx08=; b=REWrsHCoQCdEN5hZRNoeftvkJ7I//6kkTIoVDYh/N9yuF6A+RbWMefkFQm7obsqiwP cZ83t0gr/KRrqfj1xHEomkzGv3y5ELhSiuDZSKopEvVWu7NZZgBjgRLLjzfZ/h2qfso8 qGk4Ffn94gMeQr0CwmFCoACMeFyuwt/msTM13VWZmAucOQHyUZA9Eyt89lUm+FTb1XNM YPlrUKtCaaLc98NMJyK6DCyIY6YESB3QFIBS35tAT2gFLicEVLBSqCHdM8PamvhwF2/o 5m42378r23X0q40XHKkzRIHSiQQmdfilLNsdj9qdtTcHGkMqolKx7qENAWUUIieaXI82 ud7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iG2Q22rk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p9si8575903pgc.373.2019.03.13.11.40.29; Wed, 13 Mar 2019 11:40:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iG2Q22rk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727175AbfCMSkT (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:19 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:51945 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727148AbfCMSkT (ORCPT ); Wed, 13 Mar 2019 14:40:19 -0400 Received: by mail-wm1-f65.google.com with SMTP id n19so355572wmi.1 for ; Wed, 13 Mar 2019 11:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9iTYSXu9st4Th+KT6KsDMLzzJmppLHVZpX37c7/nx08=; b=iG2Q22rkiMnBnnD6BLTjtREXd8G6LoDW7yjBVv2uhk9RR0uAdfOZ3+Cd/U4HUitqtB mC4P4F92DLiiZfREBeD6TRtQEaODXffW7E/u01C1vADWhAPXNTSvOlvNoaKsizYgTUdO Kw+v1fLvQ2Ad37IikpQUekSAtXrZeIItBKNTZaiz/OfDnyDYi+IFYBJo8UU1zc7/VuAS tqp8hdXde8bWdARxsbBj9nHkAx1G31B8GBCw4mpZyVTdm6sYv7op/pU/4vee5fEV7yoN HO/LuOVTBjWNwmSve1JqhRnvrBrybUjwtWlcnm58eX4i74MVfPKUg9iyX/ZhQk+lIx6o osPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9iTYSXu9st4Th+KT6KsDMLzzJmppLHVZpX37c7/nx08=; b=GIDHs51WomnOY7XQB0S+EyK8f+LRwa44lBbW0JKFjLMV3Q7mypfEspnGipbe8MbGuz 1DcTjVqZ8zbkHwZhXOi8GkNGqZYTMPHqErbarnWmoYEOSE18Xz7wtBBiZdzip/frpFx6 wGEpUJrJBZ2Pfn5PWVosgZtOZlir9lwLZJvL9Ve5j1JbMfLQ0PeNLUkH8ideHf/GXtJX eISx9Hb8Ger+OF3pXFOLs5S5a0LaGVEWBAbhsBgx4ciXRY+qZ0gHl+9WlfyJEirPEour uPKtQ8u824rlUNTLOdo0cJOxX3MeCKSiFO9PyfZAkDMjTHxdQqbSlxwRv5SWA3ONVMfT DMAA== X-Gm-Message-State: APjAAAUJo/j00DjO45Rbr7500l2uVGmpwnPkPqLp+rest0PF4ACDJbsx uKbHxMEP5Ahdk6fAYSsZGxBTDg== X-Received: by 2002:a1c:99d2:: with SMTP id b201mr1740834wme.90.1552502415251; Wed, 13 Mar 2019 11:40:15 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:14 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 2/6] iio: gyro: add core driver for fxas21002c Date: Wed, 13 Mar 2019 18:39:58 +0000 Message-Id: <20190313184002.2501-3-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add core support for the NXP fxas21002c Tri-axis gyroscope, using the iio subsystem. It supports PM operations, axis reading, temperature, scale factor of the axis, high pass and low pass filtering, and sampling frequency selection. It will have extras modules to support the communication over i2c and spi. Signed-off-by: Rui Miguel Silva --- drivers/iio/gyro/Kconfig | 11 + drivers/iio/gyro/Makefile | 1 + drivers/iio/gyro/fxas21002c.h | 151 +++++ drivers/iio/gyro/fxas21002c_core.c | 989 +++++++++++++++++++++++++++++ 4 files changed, 1152 insertions(+) create mode 100644 drivers/iio/gyro/fxas21002c.h create mode 100644 drivers/iio/gyro/fxas21002c_core.c -- 2.20.1 diff --git a/drivers/iio/gyro/Kconfig b/drivers/iio/gyro/Kconfig index 3126cf05e6b9..cfd2cf44bac8 100644 --- a/drivers/iio/gyro/Kconfig +++ b/drivers/iio/gyro/Kconfig @@ -73,6 +73,17 @@ config BMG160_SPI tristate select REGMAP_SPI +config FXAS21002C + tristate "NXP FXAS21002C Gyro Sensor" + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + Say yes here to build support for NXP FXAS21002C Tri-axis Gyro + Sensor driver connected via I2C or SPI. + + This driver can also be built as a module. If so, the module + will be called fxas21002c_i2c or fxas21002c_spi. + config HID_SENSOR_GYRO_3D depends on HID_SENSOR_HUB select IIO_BUFFER diff --git a/drivers/iio/gyro/Makefile b/drivers/iio/gyro/Makefile index 295ec780c4eb..247dc600a602 100644 --- a/drivers/iio/gyro/Makefile +++ b/drivers/iio/gyro/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ADXRS450) += adxrs450.o obj-$(CONFIG_BMG160) += bmg160_core.o obj-$(CONFIG_BMG160_I2C) += bmg160_i2c.o obj-$(CONFIG_BMG160_SPI) += bmg160_spi.o +obj-$(CONFIG_FXAS21002C) += fxas21002c_core.o obj-$(CONFIG_HID_SENSOR_GYRO_3D) += hid-sensor-gyro-3d.o diff --git a/drivers/iio/gyro/fxas21002c.h b/drivers/iio/gyro/fxas21002c.h new file mode 100644 index 000000000000..e21fd410950c --- /dev/null +++ b/drivers/iio/gyro/fxas21002c.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Driver for NXP FXAS21002C Gyroscope - Header + * + * Copyright (C) 2019 Linaro Ltd. + * + */ + +#ifndef FXAS21002C_H_ +#define FXAS21002C_H_ + +#include + +#define FXAS21002C_REG_STATUS 0x00 +#define FXAS21002C_REG_OUT_X_MSB 0x01 +#define FXAS21002C_REG_OUT_X_LSB 0x02 +#define FXAS21002C_REG_OUT_Y_MSB 0x03 +#define FXAS21002C_REG_OUT_Y_LSB 0x04 +#define FXAS21002C_REG_OUT_Z_MSB 0x05 +#define FXAS21002C_REG_OUT_Z_LSB 0x06 +#define FXAS21002C_REG_DR_STATUS 0x07 +#define FXAS21002C_REG_F_STATUS 0x08 +#define FXAS21002C_REG_F_SETUP 0x09 +#define FXAS21002C_REG_F_EVENT 0x0A +#define FXAS21002C_REG_INT_SRC_FLAG 0x0B +#define FXAS21002C_REG_WHO_AM_I 0x0C +#define FXAS21002C_REG_CTRL0 0x0D +#define FXAS21002C_REG_RT_CFG 0x0E +#define FXAS21002C_REG_RT_SRC 0x0F +#define FXAS21002C_REG_RT_THS 0x10 +#define FXAS21002C_REG_RT_COUNT 0x11 +#define FXAS21002C_REG_TEMP 0x12 +#define FXAS21002C_REG_CTRL1 0x13 +#define FXAS21002C_REG_CTRL2 0x14 +#define FXAS21002C_REG_CTRL3 0x15 + +enum fxas21002c_fields { + F_DR_STATUS, + F_OUT_X_MSB, + F_OUT_X_LSB, + F_OUT_Y_MSB, + F_OUT_Y_LSB, + F_OUT_Z_MSB, + F_OUT_Z_LSB, + /* DR_STATUS */ + F_ZYX_OW, F_Z_OW, F_Y_OW, F_X_OW, F_ZYX_DR, F_Z_DR, F_Y_DR, F_X_DR, + /* F_STATUS */ + F_OVF, F_WMKF, F_CNT, + /* F_SETUP */ + F_MODE, F_WMRK, + /* F_EVENT */ + F_EVENT, FE_TIME, + /* INT_SOURCE_FLAG */ + F_BOOTEND, F_SRC_FIFO, F_SRC_RT, F_SRC_DRDY, + /* WHO_AM_I */ + F_WHO_AM_I, + /* CTRL_REG0 */ + F_BW, F_SPIW, F_SEL, F_HPF_EN, F_FS, + /* RT_CFG */ + F_ELE, F_ZTEFE, F_YTEFE, F_XTEFE, + /* RT_SRC */ + F_EA, F_ZRT, F_ZRT_POL, F_YRT, F_YRT_POL, F_XRT, F_XRT_POL, + /* RT_THS */ + F_DBCNTM, F_THS, + /* RT_COUNT */ + F_RT_COUNT, + /* TEMP */ + F_TEMP, + /* CTRL_REG1 */ + F_RST, F_ST, F_DR, F_ACTIVE, F_READY, + /* CTRL_REG2 */ + F_INT_CFG_FIFO, F_INT_EN_FIFO, F_INT_CFG_RT, F_INT_EN_RT, + F_INT_CFG_DRDY, F_INT_EN_DRDY, F_IPOL, F_PP_OD, + /* CTRL_REG3 */ + F_WRAPTOONE, F_EXTCTRLEN, F_FS_DOUBLE, + /* MAX FIELDS */ + F_MAX_FIELDS, +}; + +static const struct reg_field fxas21002c_reg_fields[] = { + [F_DR_STATUS] = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7), + [F_OUT_X_MSB] = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7), + [F_OUT_X_LSB] = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7), + [F_OUT_Y_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7), + [F_OUT_Y_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7), + [F_OUT_Z_MSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7), + [F_OUT_Z_LSB] = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7), + [F_ZYX_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7), + [F_Z_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6), + [F_Y_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5), + [F_X_OW] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4), + [F_ZYX_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3), + [F_Z_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2), + [F_Y_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1), + [F_X_DR] = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0), + [F_OVF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7), + [F_WMKF] = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6), + [F_CNT] = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5), + [F_MODE] = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7), + [F_WMRK] = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5), + [F_EVENT] = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5), + [FE_TIME] = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4), + [F_BOOTEND] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3), + [F_SRC_FIFO] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2), + [F_SRC_RT] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1), + [F_SRC_DRDY] = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0), + [F_WHO_AM_I] = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7), + [F_BW] = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7), + [F_SPIW] = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5), + [F_SEL] = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4), + [F_HPF_EN] = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2), + [F_FS] = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1), + [F_ELE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3), + [F_ZTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2), + [F_YTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1), + [F_XTEFE] = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0), + [F_EA] = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6), + [F_ZRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5), + [F_ZRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4), + [F_YRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3), + [F_YRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2), + [F_XRT] = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1), + [F_XRT_POL] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0), + [F_DBCNTM] = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7), + [F_THS] = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6), + [F_RT_COUNT] = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7), + [F_TEMP] = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7), + [F_RST] = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6), + [F_ST] = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5), + [F_DR] = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4), + [F_ACTIVE] = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1), + [F_READY] = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0), + [F_INT_CFG_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7), + [F_INT_EN_FIFO] = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6), + [F_INT_CFG_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5), + [F_INT_EN_RT] = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4), + [F_INT_CFG_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3), + [F_INT_EN_DRDY] = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2), + [F_IPOL] = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1), + [F_PP_OD] = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0), + [F_WRAPTOONE] = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3), + [F_EXTCTRLEN] = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2), + [F_FS_DOUBLE] = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0), +}; + +extern const struct dev_pm_ops fxas21002c_pm_ops; + +int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq, + const char *name); +void fxas21002c_core_remove(struct device *dev); +#endif diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c new file mode 100644 index 000000000000..dccded203dd5 --- /dev/null +++ b/drivers/iio/gyro/fxas21002c_core.c @@ -0,0 +1,989 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for NXP FXAS21002C Gyroscope - Core + * + * Copyright (C) 2019 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "fxas21002c.h" + +#define FXAS21002C_CHIP_ID_1 0xD6 +#define FXAS21002C_CHIP_ID_2 0xD7 + +enum fxas21002c_mode_state { + FXAS21002C_MODE_STANDBY, + FXAS21002C_MODE_READY, + FXAS21002C_MODE_ACTIVE, +}; + +#define FXAS21002C_STANDBY_ACTIVE_TIME_MS 62 +#define FXAS21002C_READY_ACTIVE_TIME_MS 7 + +#define FXAS21002C_ODR_LIST_MAX 10 + +#define FXAS21002C_SCALE_FRACTIONAL 32 +#define FXAS21002C_RANGE_LIMIT_DOUBLE 2000 + +#define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2)) + +static const int fxas21002c_odr_values[] = { + 800, 400, 200, 100, 50, 25, 12, 12 +}; + +/* + * These values are taken from the low-pass filter cutoff frequency calculated + * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32 + * => LPF cutoff frequency = 800 * 0.32 = 256 Hz + */ +static const int fxas21002c_lpf_values[] = { + 32, 16, 8 +}; + +/* + * These values are taken from the high-pass filter cutoff frequency calculated + * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750 + * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz + */ +static const int fxas21002c_hpf_values[] = { + 18750, 9625, 4875, 2475 +}; + +static const int fxas21002c_range_values[] = { + 4000, 2000, 1000, 500, 250 +}; + +struct fxas21002c_data { + u8 chip_id; + enum fxas21002c_mode_state mode; + enum fxas21002c_mode_state prev_mode; + + struct mutex lock; /* serialize data access */ + struct regmap *regmap; + struct regmap_field *regmap_fields[F_MAX_FIELDS]; + struct iio_trigger *dready_trig; + int irq; + + struct regulator *vdd; + struct regulator *vddio; + + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + s16 buffer[8] ____cacheline_aligned; +}; + +enum fxas21002c_channel_index { + CHANNEL_SCAN_INDEX_X, + CHANNEL_SCAN_INDEX_Y, + CHANNEL_SCAN_INDEX_Z, + CHANNEL_SCAN_MAX, +}; + +static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value) +{ + int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1; + + value = min_t(u8, value, odr_value_max); + + return fxas21002c_odr_values[value]; +} + +static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data, + unsigned int hz) +{ + int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values); + int i; + + for (i = 0; i < odr_table_size; i++) + if (fxas21002c_odr_values[i] == hz) + return i; + + return -EINVAL; +} + +static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value) +{ + int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1; + + value = min_t(u8, value, lpf_value_max); + + return fxas21002c_lpf_values[value]; +} + +static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data, + unsigned int hz) +{ + int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values); + int i; + + for (i = 0; i < lpf_table_size; i++) + if (fxas21002c_lpf_values[i] == hz) + return i; + + return -EINVAL; +} + +static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value) +{ + int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1; + + value = min_t(u8, value, hpf_value_max); + + return fxas21002c_hpf_values[value]; +} + +static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data, + unsigned int hz) +{ + int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values); + int i; + + for (i = 0; i < hpf_table_size; i++) + if (fxas21002c_hpf_values[i] == hz) + return i; + + return -EINVAL; +} + +static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data, + u8 value) +{ + int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1; + unsigned int fs_double; + int ret; + + /* We need to check if FS_DOUBLE is enabled to offset the value */ + ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double); + if (ret < 0) + return ret; + + if (!fs_double) + value += 1; + + value = min_t(u8, value, range_value_max); + + return fxas21002c_range_values[value]; +} + +static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data, + unsigned int range) +{ + int range_table_size = ARRAY_SIZE(fxas21002c_range_values); + bool found = false; + int fs_double = 0; + int ret; + int i; + + for (i = 0; i < range_table_size; i++) + if (fxas21002c_range_values[i] == range) { + found = true; + break; + } + + if (!found) + return -EINVAL; + + if (range > FXAS21002C_RANGE_LIMIT_DOUBLE) + fs_double = 1; + + ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double); + if (ret < 0) + return ret; + + return i; +} + +static int fxas21002c_mode_get(struct fxas21002c_data *data) +{ + unsigned int active; + unsigned int ready; + int ret; + + ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active); + if (ret < 0) + return ret; + if (active) + return FXAS21002C_MODE_ACTIVE; + + ret = regmap_field_read(data->regmap_fields[F_READY], &ready); + if (ret < 0) + return ret; + if (ready) + return FXAS21002C_MODE_READY; + + return FXAS21002C_MODE_STANDBY; +} + +static int fxas21002c_mode_set(struct fxas21002c_data *data, + enum fxas21002c_mode_state mode) +{ + int ret; + + if (mode == data->mode) + return 0; + + if (mode == FXAS21002C_MODE_READY) + ret = regmap_field_write(data->regmap_fields[F_READY], 1); + else + ret = regmap_field_write(data->regmap_fields[F_READY], 0); + if (ret < 0) + return ret; + + if (mode == FXAS21002C_MODE_ACTIVE) + ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1); + else + ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0); + if (ret < 0) + return ret; + + /* if going to active wait the setup times */ + if (mode == FXAS21002C_MODE_ACTIVE && + data->mode == FXAS21002C_MODE_STANDBY) + msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS); + + if (data->mode == FXAS21002C_MODE_READY) + msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS); + + data->prev_mode = data->mode; + data->mode = mode; + + return ret; +} + +static int fxas21002c_write(struct fxas21002c_data *data, + enum fxas21002c_fields field, int bits) +{ + int actual_mode; + int ret; + + mutex_lock(&data->lock); + + actual_mode = fxas21002c_mode_get(data); + if (actual_mode < 0) { + ret = actual_mode; + goto out_unlock; + } + + ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY); + if (ret < 0) + goto out_unlock; + + ret = regmap_field_write(data->regmap_fields[field], bits); + if (ret < 0) + goto out_unlock; + + ret = fxas21002c_mode_set(data, data->prev_mode); + +out_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_pm_get(struct fxas21002c_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) + pm_runtime_put_noidle(dev); + + return ret; +} + +static int fxas21002c_pm_put(struct fxas21002c_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + + pm_runtime_mark_last_busy(dev); + + return pm_runtime_put_autosuspend(dev); +} + +static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val) +{ + struct device *dev = regmap_get_device(data->regmap); + unsigned int temp; + int ret; + + mutex_lock(&data->lock); + ret = fxas21002c_pm_get(data); + if (ret < 0) + goto data_unlock; + + ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp); + if (ret < 0) { + dev_err(dev, "failed to read temp: %d\n", ret); + goto data_unlock; + } + + *val = sign_extend32(temp, 7); + + ret = fxas21002c_pm_put(data); + if (ret < 0) + goto data_unlock; + + ret = IIO_VAL_INT; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_axis_get(struct fxas21002c_data *data, + int index, int *val) +{ + struct device *dev = regmap_get_device(data->regmap); + __be16 axis_be; + int ret; + + mutex_lock(&data->lock); + ret = fxas21002c_pm_get(data); + if (ret < 0) + goto data_unlock; + + ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index), + &axis_be, sizeof(axis_be)); + if (ret < 0) { + dev_err(dev, "failed to read axis: %d: %d\n", index, ret); + goto data_unlock; + } + + *val = sign_extend32(be16_to_cpu(axis_be), 15); + + ret = fxas21002c_pm_put(data); + if (ret < 0) + goto data_unlock; + + ret = IIO_VAL_INT; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr) +{ + unsigned int odr_bits; + int ret; + + mutex_lock(&data->lock); + ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits); + if (ret < 0) + goto data_unlock; + + *odr = fxas21002c_odr_hz_from_value(data, odr_bits); + + ret = IIO_VAL_INT; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr) +{ + int odr_bits; + + odr_bits = fxas21002c_odr_value_from_hz(data, odr); + if (odr_bits < 0) + return odr_bits; + + return fxas21002c_write(data, F_DR, odr_bits); +} + +static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2) +{ + unsigned int bw_bits; + int ret; + + mutex_lock(&data->lock); + ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits); + if (ret < 0) + goto data_unlock; + + *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000; + + ret = IIO_VAL_INT_PLUS_MICRO; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw) +{ + int bw_bits; + int odr; + int ret; + + bw_bits = fxas21002c_lpf_value_from_bw(data, bw); + if (bw_bits < 0) + return bw_bits; + + /* + * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08 + * is not allowed and for ODR = 12.5 value 0.16 is also not allowed + */ + ret = fxas21002c_odr_get(data, &odr); + if (ret < 0) + return -EINVAL; + + if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0)) + return -EINVAL; + + return fxas21002c_write(data, F_BW, bw_bits); +} + +static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2) +{ + unsigned int sel_bits; + int ret; + + mutex_lock(&data->lock); + ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits); + if (ret < 0) + goto data_unlock; + + *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits); + + ret = IIO_VAL_INT_PLUS_MICRO; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel) +{ + int sel_bits; + + sel_bits = fxas21002c_hpf_value_from_sel(data, sel); + if (sel_bits < 0) + return sel_bits; + + return fxas21002c_write(data, F_SEL, sel_bits); +} + +static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val) +{ + int fs_bits; + int scale; + int ret = 0; + + mutex_lock(&data->lock); + ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits); + if (ret < 0) + goto data_unlock; + + scale = fxas21002c_range_fs_from_value(data, fs_bits); + if (scale < 0) { + ret = scale; + goto data_unlock; + } + + *val = scale; + +data_unlock: + mutex_unlock(&data->lock); + + return ret; +} + +static int fxas21002c_scale_set(struct fxas21002c_data *data, int range) +{ + int fs_bits; + + fs_bits = fxas21002c_range_value_from_fs(data, range); + if (fs_bits < 0) + return fs_bits; + + return fxas21002c_write(data, F_FS, fs_bits); +} + +static int fxas21002c_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct fxas21002c_data *data = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + switch (chan->type) { + case IIO_TEMP: + return fxas21002c_temp_get(data, val); + case IIO_ANGL_VEL: + return fxas21002c_axis_get(data, chan->scan_index, val); + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_ANGL_VEL: + *val2 = FXAS21002C_SCALE_FRACTIONAL; + ret = fxas21002c_scale_get(data, val); + if (ret < 0) + return ret; + + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *val = 0; + return fxas21002c_lpf_get(data, val2); + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: + *val = 0; + return fxas21002c_hpf_get(data, val2); + case IIO_CHAN_INFO_SAMP_FREQ: + *val2 = 0; + return fxas21002c_odr_get(data, val); + default: + return -EINVAL; + } +} + +static int fxas21002c_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct fxas21002c_data *data = iio_priv(indio_dev); + int range; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + if (val2) + return -EINVAL; + + return fxas21002c_odr_set(data, val); + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + if (val) + return -EINVAL; + + val2 = val2 / 10000; + return fxas21002c_lpf_set(data, val2); + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_ANGL_VEL: + range = (((val * 1000 + val2 / 1000) * + FXAS21002C_SCALE_FRACTIONAL) / 1000); + return fxas21002c_scale_set(data, range); + default: + return -EINVAL; + } + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: + return fxas21002c_hpf_set(data, val2); + default: + return -EINVAL; + } +} + +static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800"); + +static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available, + "0.32 0.16 0.08"); + +static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available, + "0.018750 0.009625 0.004875 0.002475"); + +static IIO_CONST_ATTR(in_anglvel_scale_available, + "125.0 62.5 31.25 15.625 7.8125"); + +static struct attribute *fxas21002c_attributes[] = { + &iio_const_attr_sampling_frequency_available.dev_attr.attr, + &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr, + &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr, + &iio_const_attr_in_anglvel_scale_available.dev_attr.attr, + NULL, +}; + +static const struct attribute_group fxas21002c_attrs_group = { + .attrs = fxas21002c_attributes, +}; + +#define FXAS21002C_CHANNEL(_axis) { \ + .type = IIO_ANGL_VEL, \ + .modified = 1, \ + .channel2 = IIO_MOD_##_axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ + BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = CHANNEL_SCAN_INDEX_##_axis, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_BE, \ + }, \ +} + +static const struct iio_chan_spec fxas21002c_channels[] = { + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .scan_index = -1, + }, + FXAS21002C_CHANNEL(X), + FXAS21002C_CHANNEL(Y), + FXAS21002C_CHANNEL(Z), +}; + +static const struct iio_info fxas21002c_info = { + .attrs = &fxas21002c_attrs_group, + .read_raw = &fxas21002c_read_raw, + .write_raw = &fxas21002c_write_raw, +}; + +static irqreturn_t fxas21002c_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct fxas21002c_data *data = iio_priv(indio_dev); + int ret; + + mutex_lock(&data->lock); + ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB, + data->buffer, CHANNEL_SCAN_MAX * sizeof(s16)); + mutex_unlock(&data->lock); + if (ret < 0) + goto notify_done; + + iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, + pf->timestamp); + +notify_done: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int fxas21002c_chip_init(struct fxas21002c_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + unsigned int chip_id; + int ret; + + ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id); + if (ret < 0) + return ret; + + if (chip_id != FXAS21002C_CHIP_ID_1 && + chip_id != FXAS21002C_CHIP_ID_2) { + dev_err(dev, "chip id 0x%02x is not supported\n", chip_id); + return -EINVAL; + } + + data->chip_id = chip_id; + + ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY); + if (ret < 0) + return ret; + + /* Set ODR to 200HZ as default */ + ret = fxas21002c_odr_set(data, 200); + if (ret < 0) + dev_err(dev, "failed to set ODR: %d\n", ret); + + return ret; +} + +static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig, + bool state) +{ + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct fxas21002c_data *data = iio_priv(indio_dev); + + return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state); +} + +static const struct iio_trigger_ops fxas21002c_trigger_ops = { + .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state, +}; + +static irqreturn_t fxas21002c_data_rdy_trig_poll(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct fxas21002c_data *data = iio_priv(indio_dev); + unsigned int data_ready; + int ret; + + ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready); + if (ret < 0) + return IRQ_NONE; + + if (!data_ready) + return IRQ_NONE; + + iio_trigger_poll(data->dready_trig); + + return IRQ_HANDLED; +} + +static int fxas21002c_trigger_probe(struct fxas21002c_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct device_node *np = indio_dev->dev.of_node; + unsigned long irq_trig; + bool irq_open_drain; + int irq1; + int ret; + + if (!data->irq) + return 0; + + irq1 = of_irq_get_byname(np, "INT1"); + + if (irq1 == data->irq) { + dev_info(dev, "using interrupt line INT1\n"); + ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY], + 1); + if (ret < 0) + return ret; + } + + dev_info(dev, "using interrupt line INT2\n"); + + irq_open_drain = of_property_read_bool(np, "drive-open-drain"); + + data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + indio_dev->id); + if (!data->dready_trig) + return -ENOMEM; + + irq_trig = IRQF_TRIGGER_RISING; + if (irq_open_drain) + irq_trig |= IRQF_SHARED; + + ret = devm_request_irq(dev, data->irq, fxas21002c_data_rdy_trig_poll, + irq_trig, "fxas21002c_data_ready", + data->dready_trig); + if (ret < 0) + return ret; + + data->dready_trig->dev.parent = dev; + data->dready_trig->ops = &fxas21002c_trigger_ops; + iio_trigger_set_drvdata(data->dready_trig, indio_dev); + + return devm_iio_trigger_register(dev, data->dready_trig); +} + +static int fxas21002c_power_enable(struct fxas21002c_data *data) +{ + int ret; + + ret = regulator_enable(data->vdd); + if (ret < 0) + return ret; + + return regulator_enable(data->vddio); +} + +static void fxas21002c_power_disable(struct fxas21002c_data *data) +{ + regulator_disable(data->vdd); + regulator_disable(data->vddio); +} + +static void fxas21002c_power_disable_action(void *_data) +{ + struct fxas21002c_data *data = _data; + + fxas21002c_power_disable(data); +} + +static int fxas21002c_regulators_get(struct fxas21002c_data *data) +{ + struct device *dev = regmap_get_device(data->regmap); + + data->vdd = devm_regulator_get(dev->parent, "vdd"); + if (IS_ERR(data->vdd)) + return PTR_ERR(data->vdd); + + data->vddio = devm_regulator_get(dev->parent, "vddio"); + if (IS_ERR(data->vddio)) + return PTR_ERR(data->vddio); + + return 0; +} + +int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq, + const char *name) +{ + struct fxas21002c_data *data; + struct iio_dev *indio_dev; + struct regmap_field *f; + int i; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + dev_set_drvdata(dev, indio_dev); + data->irq = irq; + data->regmap = regmap; + + for (i = 0; i < F_MAX_FIELDS; i++) { + f = devm_regmap_field_alloc(dev, data->regmap, + fxas21002c_reg_fields[i]); + if (IS_ERR(f)) + return PTR_ERR(f); + + data->regmap_fields[i] = f; + } + + mutex_init(&data->lock); + + ret = fxas21002c_regulators_get(data); + if (ret < 0) + return ret; + + ret = devm_add_action(dev, fxas21002c_power_disable_action, data); + if (ret < 0) + return ret; + + ret = fxas21002c_power_enable(data); + if (ret < 0) + return ret; + + ret = fxas21002c_chip_init(data); + if (ret < 0) + return ret; + + indio_dev->dev.parent = dev; + indio_dev->channels = fxas21002c_channels; + indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels); + indio_dev->name = name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &fxas21002c_info; + + ret = fxas21002c_trigger_probe(data); + if (ret < 0) + return ret; + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + fxas21002c_trigger_handler, NULL); + if (ret < 0) + return ret; + + ret = pm_runtime_set_active(dev); + if (ret) + return ret; + + pm_runtime_enable(dev); + pm_runtime_set_autosuspend_delay(dev, 2000); + pm_runtime_use_autosuspend(dev); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret < 0) + return ret; + + dev_info(dev, "fxas21002c iio device ready\n"); + + return 0; +} +EXPORT_SYMBOL_GPL(fxas21002c_core_probe); + +void fxas21002c_core_remove(struct device *dev) +{ + struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); + + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + pm_runtime_put_noidle(dev); + + fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY); + fxas21002c_power_disable(data); +} +EXPORT_SYMBOL_GPL(fxas21002c_core_remove); + +static int __maybe_unused fxas21002c_suspend(struct device *dev) +{ + struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); + + fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY); + fxas21002c_power_disable(data); + + return 0; +} + +static int __maybe_unused fxas21002c_resume(struct device *dev) +{ + struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); + int ret; + + ret = fxas21002c_power_enable(data); + if (ret < 0) + return ret; + + ret = fxas21002c_mode_set(data, data->prev_mode); + if (ret < 0) + return ret; + + return 0; +} + +static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev) +{ + struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); + int ret; + + ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY); + if (ret < 0) + return -EAGAIN; + + return 0; +} + +static int __maybe_unused fxas21002c_runtime_resume(struct device *dev) +{ + struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev)); + int ret; + + ret = fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE); + if (ret < 0) + return ret; + + return 0; +} + +const struct dev_pm_ops fxas21002c_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume) + SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend, + fxas21002c_runtime_resume, NULL) +}; +EXPORT_SYMBOL_GPL(fxas21002c_pm_ops); + +MODULE_AUTHOR("Rui Miguel Silva "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("FXAS21002C Gyro driver"); From patchwork Wed Mar 13 18:39:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160266 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14637093jad; Wed, 13 Mar 2019 11:40:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqzS+HLNllZw96Z3fyZCqOfAclfkJMIiQeivUXP9/3l1ZTFp/DSuYrWuTdQNjCRsYO9cWNtk X-Received: by 2002:a17:902:aa92:: with SMTP id d18mr16198055plr.278.1552502425728; Wed, 13 Mar 2019 11:40:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502425; cv=none; d=google.com; s=arc-20160816; b=pxQATWqwZWbCQpJDmgZ2Q/f9KhUZ689W7RxnmlqHUEhym1Tzqe3IzEBW8bf4Jeelkq Iw2+xNbSolX/OgD5DyKBO3v6jjfC/Uab1VbyTeFrYcRnK2Dr021uMxtfRGKTqS0VB1Ov OeFaDgamdmFlzkcPEnl5S2OQkCD/sDRg9X+r8lLPIjqkzH9Px5d90c6uXSO8qZvvvRwQ ZitbCN5d2s7GHAJ4vMFngUWJtw3DZUdknvQN6FP4MWfnjhKTgupQrXL6c/U2jzzTMoK2 lLApOow0Mux6WJB2HcSuuBDtEwpp+/qaJm1oIccuEOUhzVzdwkk+qtXxWd3gMa6eJabu 7UeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2QCPTdmFK6cOLG6MFHJiz4CEb2BEdpfF4aAmH9h3POM=; b=dKLrxyZA4JpFCV5XqAGjnBPNOD4GiZMCC6Ix7k8LeCDullYLrbLq/Pb81fq6qgWa+9 53tU3JXmu/v3+9hhMGIOWXRqUFQu7Hy712vRloeUeVSsiF19vsmiaWCv9aBe6DtaHeG0 MsVJllBlIMyJZZmStb0APQRSfB7LqpHsp9HRmdgTJGnDOgpYEfDf+cbMuxORLb8WZ5gI 9o2wuKQPMA4jy5xRxYiPV6fWaCbq1vnKYeExjWFcKbWnTO8JGFaEGZYDd0pgfK9bRHrH ULjIa9qwWPIknmRNOedCNGNUphqLNWQ+vwaqsHtvM1vShydls1UOzx9xn4MQRUDq7oUT L4Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yP2nxjQj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h1si12075908plh.265.2019.03.13.11.40.25; Wed, 13 Mar 2019 11:40:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yP2nxjQj; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727189AbfCMSkV (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:21 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:52817 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727116AbfCMSkU (ORCPT ); Wed, 13 Mar 2019 14:40:20 -0400 Received: by mail-wm1-f65.google.com with SMTP id f65so348418wma.2 for ; Wed, 13 Mar 2019 11:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2QCPTdmFK6cOLG6MFHJiz4CEb2BEdpfF4aAmH9h3POM=; b=yP2nxjQjHBlGOaT/JX1rOnnbO6g6gYCGNaUwaB7/aeZw0m65fvp269zHaM8+GMcniC omjygLJMYLKz/RqZiWA5eiSWzeDqBSHShfINgc+q+m450tgYFJ3EWvezOqiQVojIbflS tas37OzYuRQPV24CodqtlRnqSLM/QwbVuKlBJ1zMI0v0ujRm4eMBeIdbhIoIdLHrkHcI HJk8VOWLkfDhFCFWbOBUKuNhXFj95nb+Omv/YX+zBdcLg1a7jQe1RzSzWmniVtnN1SxF jaPHwuB+RSYULciJslOw3VfbSb/1ux8XBwZlkT3xccBDTfYJGTpdhUDzbGP7EJYe9Fni cjUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2QCPTdmFK6cOLG6MFHJiz4CEb2BEdpfF4aAmH9h3POM=; b=ZY0Is4P7eOJhR5fswIOaj7CoxZNF0ST9gvnE5Hogb7RtOn7cyb0kNWMYtYXtdP3En6 mCj/7wU9G4xvdOjZ4erGEbUiE1HgYsvcu0GG4vHuHnyHdEH4CCFDr3whiSBfDlAsnQ/U 8HiZR5fxOzquy6ixfxlqNyiIqjXRsvDLFfkE8mWLfLTn+cqyDf1OtTC/CI4JZXUjv7+h eJkG8Dkx4ERBf6tnVIcPs1c43XaFiD438JWlQeaxOlm5wcRtXS2kd+AGGiLVP+5/6UwF wM3phiqxdfm9WDbwJdd/Y8NBiyF+p2AENbPRcoFP0DJCyeHWEwo7J3M2DSxFY/ZbsMrJ eUQw== X-Gm-Message-State: APjAAAVuD8A+6j3moykjJ0UZROKpVc9VUtkzT8PNm3GpyUrLVXPcWqev ehWyYgwNS3So7Gt6eBnXEHcohw== X-Received: by 2002:a1c:9e97:: with SMTP id h145mr3212380wme.147.1552502417952; Wed, 13 Mar 2019 11:40:17 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:17 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 3/6] iio: gyro: fxas21002c: add i2c driver Date: Wed, 13 Mar 2019 18:39:59 +0000 Message-Id: <20190313184002.2501-4-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the real driver to talk over i2c and use the fxas21002c core for the main tasks. Signed-off-by: Rui Miguel Silva --- drivers/iio/gyro/Kconfig | 6 +++ drivers/iio/gyro/Makefile | 1 + drivers/iio/gyro/fxas21002c_i2c.c | 73 +++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 drivers/iio/gyro/fxas21002c_i2c.c -- 2.20.1 diff --git a/drivers/iio/gyro/Kconfig b/drivers/iio/gyro/Kconfig index cfd2cf44bac8..71b6552ee06b 100644 --- a/drivers/iio/gyro/Kconfig +++ b/drivers/iio/gyro/Kconfig @@ -77,6 +77,8 @@ config FXAS21002C tristate "NXP FXAS21002C Gyro Sensor" select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select FXAS21002C_I2C if (I2C) + depends on I2C help Say yes here to build support for NXP FXAS21002C Tri-axis Gyro Sensor driver connected via I2C or SPI. @@ -84,6 +86,10 @@ config FXAS21002C This driver can also be built as a module. If so, the module will be called fxas21002c_i2c or fxas21002c_spi. +config FXAS21002C_I2C + tristate + select REGMAP_I2C + config HID_SENSOR_GYRO_3D depends on HID_SENSOR_HUB select IIO_BUFFER diff --git a/drivers/iio/gyro/Makefile b/drivers/iio/gyro/Makefile index 247dc600a602..adc18a5eb283 100644 --- a/drivers/iio/gyro/Makefile +++ b/drivers/iio/gyro/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_BMG160) += bmg160_core.o obj-$(CONFIG_BMG160_I2C) += bmg160_i2c.o obj-$(CONFIG_BMG160_SPI) += bmg160_spi.o obj-$(CONFIG_FXAS21002C) += fxas21002c_core.o +obj-$(CONFIG_FXAS21002C_I2C) += fxas21002c_i2c.o obj-$(CONFIG_HID_SENSOR_GYRO_3D) += hid-sensor-gyro-3d.o diff --git a/drivers/iio/gyro/fxas21002c_i2c.c b/drivers/iio/gyro/fxas21002c_i2c.c new file mode 100644 index 000000000000..c248ac5251df --- /dev/null +++ b/drivers/iio/gyro/fxas21002c_i2c.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for NXP FXAS21002C Gyroscope - I2C + * + * Copyright (C) 2018 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include "fxas21002c.h" + +static const struct regmap_config fxas21002c_regmap_i2c_conf = { + .reg_bits = 8, + .val_bits = 8, + .max_register = FXAS21002C_REG_CTRL3, +}; + +static int fxas21002c_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct regmap *regmap; + const char *name = NULL; + + regmap = devm_regmap_init_i2c(i2c, &fxas21002c_regmap_i2c_conf); + if (IS_ERR(regmap)) { + dev_err(&i2c->dev, "Failed to register i2c regmap: %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + if (id) + name = id->name; + + return fxas21002c_core_probe(&i2c->dev, regmap, i2c->irq, name); +} + +static int fxas21002c_i2c_remove(struct i2c_client *i2c) +{ + fxas21002c_core_remove(&i2c->dev); + + return 0; +} + +static const struct i2c_device_id fxas21002c_i2c_id[] = { + { "fxas21002c", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, fxas21002c_i2c_id); + +static const struct of_device_id fxas21002c_i2c_of_match[] = { + { .compatible = "nxp,fxas21002c", }, + { }, +}; +MODULE_DEVICE_TABLE(of, fxas21002c_i2c_of_match); + +static struct i2c_driver fxas21002c_i2c_driver = { + .driver = { + .name = "fxas21002c_i2c", + .pm = &fxas21002c_pm_ops, + .of_match_table = of_match_ptr(fxas21002c_i2c_of_match), + }, + .probe = fxas21002c_i2c_probe, + .remove = fxas21002c_i2c_remove, + .id_table = fxas21002c_i2c_id, +}; +module_i2c_driver(fxas21002c_i2c_driver); + +MODULE_AUTHOR("Rui Miguel Silva "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("FXAS21002C I2C Gyro driver"); From patchwork Wed Mar 13 18:40:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160267 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14637098jad; Wed, 13 Mar 2019 11:40:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2Gw50CR61HIeTs6tAQZYmt0uwT4YAtFLT+W+9/BkV3JSIdPGMXSsMqEnu6iLRuXiUxcYj X-Received: by 2002:a17:902:9008:: with SMTP id a8mr47295957plp.38.1552502426035; Wed, 13 Mar 2019 11:40:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502426; cv=none; d=google.com; s=arc-20160816; b=fXHau8ssd6Nb4as6lMHj2t3zeS+g4FFXvCOgoJApU9TwanAy500LiGFgHc/BpGTVg5 4oGbqo6lEtGtNRNjCLpTTRfVEWqTUnPe8MqT/Z6nYy38cARPZ9aQgq2jl1wEcWg9SMK9 G5dzk0EQjCxA8yCFTRzLlMgy+CxVaKpPzlUhD2xX3topU5E0CpR8tVqDRRlaAFX1IttY xDOtj8BrGRgdVzrkhBjU/FKDeDUx3DwSG0+L+IOTyVsIqNzlEcgiQw93FXRz1TtqlnwX yRVHDhgQuOMx9/3fXnBnQtKtnaeXRQlnfEO+xxyYLD9e8abJOKp3nb1ojmdPLQXJ1QyA NjVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YBROu6s1aUqFXVAOn6ZhMxPUlZjIbwtgWmPTml7WQYY=; b=J3Bpa6jVajzJFgrPFwq13YjUC25XNRQOnymAgTYGpeZyLUJ+XFv04JWqWuEE1xZVxv fQHWWkrRfTJfKERYQFDc/21cYfjRxyPWMpl2sgyCWrCLODHpw6oV69jLBovF5E3qU5Cj UvsgCknRB/miyL5oCXxySbLZSy3GU5fYuGhmqbf/m32HRgNWonOvUxkmjXCtTT4d6ODN L45Qi5qLAO2FfEeec4lsN9TwTVDEDjwa82vLgqPf7bd8eY1ZbaAWFyd2BMsv7GNLUX9L UXb7/V+cCRCE09Nadz2Q7Ctm2CtZugHd/tLeeK3HqyyfdzDTmCr7MhY0V5P9E1YCH54s qDug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cJL8Luw2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h1si12075908plh.265.2019.03.13.11.40.25; Wed, 13 Mar 2019 11:40:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cJL8Luw2; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727203AbfCMSkX (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:23 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:51957 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727199AbfCMSkW (ORCPT ); Wed, 13 Mar 2019 14:40:22 -0400 Received: by mail-wm1-f67.google.com with SMTP id n19so355833wmi.1 for ; Wed, 13 Mar 2019 11:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YBROu6s1aUqFXVAOn6ZhMxPUlZjIbwtgWmPTml7WQYY=; b=cJL8Luw2mmbur8J9ux/dfWGjDSuhM4V6OBO3gN6evqtSl4a/odxL3hVjoH7RdSTmX2 X1t9q2IWQLE4x77IqfdD8eTk78h+vMaleJ8dpeZq+CjAMxCg08nUr9wVMhVg+uyjY5k4 IEp2WQRf+uj30w2DASs2AYEdGqG/2whPVOf5IPzaAFCVsHmjut82rLRmNAmXkoO7XuES 3HvkHOqTOnQI9hXvYgbmJp+fONO3RRwGZw8OmY38W9DWscC3nJ9LIWCZsLULBuuib+IW IeOnD8QKnPp1QSAokz4UvMFGGXIFtQowpVcqc3FvzbtV9CwOmVVPbB3ytCS56+H4Cy8v ktsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YBROu6s1aUqFXVAOn6ZhMxPUlZjIbwtgWmPTml7WQYY=; b=G47GvRt2hBEfuaCw+7Scv+vudOfnZBUWPAbOvtXhcBnu1EsmLK2DPxO887Q0118Fgb XnVXSxtGt0J8iAXanCUIl1K+KZ8YlC9Csbl7+AQPLZN2So3s4CleNxGlvBzFsUNx2R+/ rx4w9soZaHeSKJzBjH3EhVT9J281JhDEQglm1YCwXZdYXr7jpH44iT/53cFIMP8ImHRo SOjOeCaSV3yLUdcKMtzOlcoYNiIawl6i4uwzc5ukhzcH5UBJIbofPQZpseb8WuUyrI4x GA6qAMqHhgaxPU7zNtjDjRhwRz6bJ8gEA1jp9B9eeboJeI0PE9cSECrp8NhXyBlAxXc8 vqyg== X-Gm-Message-State: APjAAAWUugz0HFtvk16qkulmS/dcuGUmjepnoovVcg1cZD5IVN4IGGOC D9HrHsy0c1LhNa193G5YKYKu4g== X-Received: by 2002:a1c:1cf:: with SMTP id 198mr3120510wmb.52.1552502420799; Wed, 13 Mar 2019 11:40:20 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:20 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 4/6] iio: gyro: fxas21002c: add spi driver Date: Wed, 13 Mar 2019 18:40:00 +0000 Message-Id: <20190313184002.2501-5-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add driver to talk over spi to a fxas21002c gyroscope device and use the core as main controller. Signed-off-by: Rui Miguel Silva --- drivers/iio/gyro/Kconfig | 7 +++- drivers/iio/gyro/Makefile | 1 + drivers/iio/gyro/fxas21002c_spi.c | 69 +++++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/iio/gyro/fxas21002c_spi.c -- 2.20.1 diff --git a/drivers/iio/gyro/Kconfig b/drivers/iio/gyro/Kconfig index 71b6552ee06b..61c00cee037d 100644 --- a/drivers/iio/gyro/Kconfig +++ b/drivers/iio/gyro/Kconfig @@ -78,7 +78,8 @@ config FXAS21002C select IIO_BUFFER select IIO_TRIGGERED_BUFFER select FXAS21002C_I2C if (I2C) - depends on I2C + select FXAS21002C_SPI if (SPI) + depends on (I2C || SPI_MASTER) help Say yes here to build support for NXP FXAS21002C Tri-axis Gyro Sensor driver connected via I2C or SPI. @@ -90,6 +91,10 @@ config FXAS21002C_I2C tristate select REGMAP_I2C +config FXAS21002C_SPI + tristate + select REGMAP_SPI + config HID_SENSOR_GYRO_3D depends on HID_SENSOR_HUB select IIO_BUFFER diff --git a/drivers/iio/gyro/Makefile b/drivers/iio/gyro/Makefile index adc18a5eb283..45cbd5dc644e 100644 --- a/drivers/iio/gyro/Makefile +++ b/drivers/iio/gyro/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_BMG160_I2C) += bmg160_i2c.o obj-$(CONFIG_BMG160_SPI) += bmg160_spi.o obj-$(CONFIG_FXAS21002C) += fxas21002c_core.o obj-$(CONFIG_FXAS21002C_I2C) += fxas21002c_i2c.o +obj-$(CONFIG_FXAS21002C_SPI) += fxas21002c_spi.o obj-$(CONFIG_HID_SENSOR_GYRO_3D) += hid-sensor-gyro-3d.o diff --git a/drivers/iio/gyro/fxas21002c_spi.c b/drivers/iio/gyro/fxas21002c_spi.c new file mode 100644 index 000000000000..88a4e9acad24 --- /dev/null +++ b/drivers/iio/gyro/fxas21002c_spi.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for NXP Fxas21002c Gyroscope - SPI + * + * Copyright (C) 2019 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include "fxas21002c.h" + +static const struct regmap_config fxas21002c_regmap_spi_conf = { + .reg_bits = 8, + .val_bits = 8, + .max_register = FXAS21002C_REG_CTRL3, +}; + +static int fxas21002c_spi_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + struct regmap *regmap; + + regmap = devm_regmap_init_spi(spi, &fxas21002c_regmap_spi_conf); + if (IS_ERR(regmap)) { + dev_err(&spi->dev, "Failed to register spi regmap: %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + return fxas21002c_core_probe(&spi->dev, regmap, spi->irq, id->name); +} + +static int fxas21002c_spi_remove(struct spi_device *spi) +{ + fxas21002c_core_remove(&spi->dev); + + return 0; +} + +static const struct spi_device_id fxas21002c_spi_id[] = { + { "fxas21002c", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, fxas21002c_spi_id); + +static const struct of_device_id fxas21002c_spi_of_match[] = { + { .compatible = "nxp,fxas21002c", }, + { }, +}; +MODULE_DEVICE_TABLE(of, fxas21002c_spi_of_match); + +static struct spi_driver fxas21002c_spi_driver = { + .driver = { + .name = "fxas21002c_spi", + .pm = &fxas21002c_pm_ops, + .of_match_table = of_match_ptr(fxas21002c_spi_of_match), + }, + .probe = fxas21002c_spi_probe, + .remove = fxas21002c_spi_remove, + .id_table = fxas21002c_spi_id, +}; +module_spi_driver(fxas21002c_spi_driver); + +MODULE_AUTHOR("Rui Miguel Silva "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("FXAS21002C SPI Gyro driver"); From patchwork Wed Mar 13 18:40:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160268 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14637127jad; Wed, 13 Mar 2019 11:40:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqzo5sPaJqCaHdGA9v/ZWYRNL7p5U528tSs4eFDDgQ92RLW5nkQtQmSwoCa2arclVqogAO5a X-Received: by 2002:a65:424d:: with SMTP id d13mr27686372pgq.203.1552502427954; Wed, 13 Mar 2019 11:40:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502427; cv=none; d=google.com; s=arc-20160816; b=seBqoggzJZsA12K1dNNn0xP9h2dN3FNxmPhmocopnJzyCVzrlg+wF8ZrlZ0bZwZvKM 3KAOx45uiqLtOKjyEbuTfAt9ETMJBqSpM2cJ6YB0kGRiaRLJh/1O7ZgWJ4rAynEQKD9V foSMEiqyFMSnBbP0PodXJCORZQ9ewcL/b7t31p4uNVYAKckStPYcUzraMym3eo4lLCB3 MrvgvKmN9MeGERHPcLjqQrAkIksEQKdOElqzlR2yR6V61VYd8MZ1UeFLAlEwqfYFEL1u UPAOz1Cg9kH3ABreGZQrGRHofeVetS7gb6gW1f06qsxSTW8+RIGXdfeGiJDp74Y2qQZq CcBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9ABacVTFYKOyRAzmYJteZEmqXfSALh7oSBIxWHFHOOY=; b=aRfQc3oaVfxpGFIssEbn64e7+fXRUUqMRZ/vy8nqgNFkWqnkdHzYNCl70qQNNq3qSE 7HP8GqcXNq0A3wIHJYPFhiw+zBKzsCTsiPqo3OdZU3Y0qOqyb03ADO+SWBvbp11DZSRc +3lexa4jyT/FtVCGSLaFGMPJDmWQ8yT+8uP9+Xp9zFW1Ej5Pec1BPYd6P47DVMp9drVO 4DmIDb3sCNfIEUAmbBorj6YHxX0AGMv3gGFtf+DCyfHD0NmUkAxUWHOb4HobKOg0LeZN 1EMnO95JoOP+JSnE8KRywmi12A261pGNKv72l/eH+Q5oOy4wOQU8vw8RU9Dm4m4dp/DE cC9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TLCepy8F; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h1si12075908plh.265.2019.03.13.11.40.27; Wed, 13 Mar 2019 11:40:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TLCepy8F; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727143AbfCMSk0 (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:26 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:40913 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727204AbfCMSkZ (ORCPT ); Wed, 13 Mar 2019 14:40:25 -0400 Received: by mail-wm1-f67.google.com with SMTP id g20so282052wmh.5 for ; Wed, 13 Mar 2019 11:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9ABacVTFYKOyRAzmYJteZEmqXfSALh7oSBIxWHFHOOY=; b=TLCepy8FOeVa9C2PtKhgNKA8Qho8pUF2h1J/3Wt6T/bNCMir5ikceLtQ3VcUze0ZZP wVeuiMTFRV9zJWkLZxCc/Goe6CJBUubXA1oz9VsgAKnfIYDkunNpi3pkbYnlA1de4s4S oHtI+Fdau2gb46AtPLxpzV6LNWtWDWry6VmmfljIbNdFqjB6WYw5xxHTV3FHT7smsgys LA5ujwQz+itRD9BmnuDWchNDxQl7DID7wcmIBrSqnwsgwUpZrwQ4vxcMvCff3bpw6vZG DawkszQk51K2x256gcUe+00sksHeCdjwhGMtHSDzfWRpacPE8br2aRqVpNaLRwySSxWt yNoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ABacVTFYKOyRAzmYJteZEmqXfSALh7oSBIxWHFHOOY=; b=NX3qgkdNGZPRU2Qt3z7xHN+ur7j1ubuf5vhPMD6XHEBCkmtiuFHLLgiSI1/yKiTFKD fkNPJ/iQ8Axlei1ujU0Wzf+LSJc08JF+Vj1Qd5WAtGeHd8ckD5vOu/PEokFEM3Q4g8K2 C/8BRNvXyIfamk5YJTRFeLyOIXFBsQCDZLNe2dS0+/Sm/9r+T9o8jL2pb/+5z52f8VzI VpQkiHwzQb3wwPhQfO8OIMxYLohnxvdPftDQMZjDuXfYYHzM5Bd3HbYLcK1EsCCzeMJy OhzLPQ80LOedENHM86yFqP3R3tMf0lYFWkBQuNmnNxj0OCBO92NgAnhLXPIR6kDN+YXb 7SYg== X-Gm-Message-State: APjAAAXDS0QffsPA2RcLCVbGCMufhczS99Y9hBeQuYpOzf/kw6j2uYPp 14xoJrHfzqqmcclNXOo1/M+Byg== X-Received: by 2002:a7b:c08a:: with SMTP id r10mr3175218wmh.112.1552502423609; Wed, 13 Mar 2019 11:40:23 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:23 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 5/6] ARM: dts: imx7s-warp: add fxas21002c gyroscope Date: Wed, 13 Mar 2019 18:40:01 +0000 Message-Id: <20190313184002.2501-6-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add entry to enable the fxas21002c gyroscope in the warp7 board. Signed-off-by: Rui Miguel Silva --- arch/arm/boot/dts/imx7s-warp.dts | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.20.1 diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 58d1a89ee3e3..bf853707b104 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -238,6 +238,13 @@ compatible = "fsl,mpl3115"; reg = <0x60>; }; + + gyroscope@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + vdd-supply = <®_peri_3p15v>; + vddio-supply = <®_peri_3p15v>; + }; }; &sai1 { From patchwork Wed Mar 13 18:40:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rui Miguel Silva X-Patchwork-Id: 160269 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp14637179jad; Wed, 13 Mar 2019 11:40:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqy/HkqNAWlipCi1OLxCVvr7Gmk8nco+cjEpyaOb5FIQ5enBiXEqLmzf3soxan8i+82c0nBF X-Received: by 2002:a62:168a:: with SMTP id 132mr45537384pfw.155.1552502430152; Wed, 13 Mar 2019 11:40:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552502430; cv=none; d=google.com; s=arc-20160816; b=W5M9qYKw4lnBeb0R+bCA/qX8VoxGlHmuYUgngwHiK87UGS3PTnwBW9m7m5nsN0rIu7 mBID8o23KUJFdGZplt+XDI26eWxv+iD/TzJszUCKsE+mKVxvZ1ENe9HwpO7IK/g9mBEz qLiY7MicWdJ8lbQIfS/nDHg276JzkXR9rtQXsoz6tFQJCa3D8oTfrQ4TUNJrXDHNKZHb WR3rXuKCEc73Bstv+aX1+tSiYYD0dXbmQoh7f5UY8vo++d1BeCugX98M5IcXFZivb0zv M2VkRDTXj3bsl/CrII/wNqWDrnZyiqpAtOvinGZsb97MgjMew/ojV+bzuT85cliOKjfj QFVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=83yOeT7jpEGLZ3WSC5kEEodmRHpZrlhkUDLCavBw4cY=; b=DbwRAQ0d54C88tSNG0h5pjWinosADpn8wBmJcRmRc/NY4yloybf3lN5emVde8B4ubw T2vNtQw75oGIWNFKFaPu747xV+6oBoK0qG3kZjziDNXT5EQeeW6uCi2gBAzVpsMHt/lH nxjzDIDtoFPYiejxHEDcnVLNDM61oOiszZN8EHssMEg/73GhchF29iaeOQljPQYV+fuq KM5vv8hHdGKMsFKNC45T/NdDucJyAzIj0uA6BuR0PEvoyKkwChixugDPS95zvksq/HIz oEOEUTQrtNWL82lX3bTuvW9DP6rpQOy859CW1Vc2nS0iqugciWF1vC2SFc02MFWxm6KU AV9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zvir5drZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p9si8575903pgc.373.2019.03.13.11.40.29; Wed, 13 Mar 2019 11:40:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zvir5drZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727204AbfCMSk2 (ORCPT + 7 others); Wed, 13 Mar 2019 14:40:28 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:32940 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727201AbfCMSk1 (ORCPT ); Wed, 13 Mar 2019 14:40:27 -0400 Received: by mail-wr1-f65.google.com with SMTP id i8so3166356wrm.0 for ; Wed, 13 Mar 2019 11:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=83yOeT7jpEGLZ3WSC5kEEodmRHpZrlhkUDLCavBw4cY=; b=zvir5drZ11/HUH7v0W0a0qAk54wJo7Ss0hxC+PQOCiepzmeYB1ThKopUiNlLLBspMN 79Tuieh6hbB/uh0AcxJYQIblp9LDy7ipQds5/wcVR4Lk8vgGmS7bM5p1pEv6gUer5cN+ oWQi+Fws+ztLiva4iJ3YbBwT1rvwwez3Got1THFXwy9Rzi7tQ5dXS9iT68Wux/ODUoKV ZDGQKH1LKRZ4amAAr62aLuT8tVeJDldKWmHl/9vQp3WAlhRRwnKSuvzXxled9i9Tnviw 0ZTrbP26UxvQ8Zb64hYzptsDoAtWEzn8zDBMmVMicEz3wM79qWk4uRgj1AojEvvHDSr/ U+EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=83yOeT7jpEGLZ3WSC5kEEodmRHpZrlhkUDLCavBw4cY=; b=UCTQa/gHxIpTCg8kisU6rg5HiSGcOI0CnjDe6fj50luWzRQZj4xHRltKvqb1rridy0 2qShikpgEUShUR0XllLePLs0UmrZU7w0SdV59BdaqsL0L6qFQDxH/jJVMHJT2mohepof cDYFPeaYHgzN79AIZd4fYHMXPUPFYB1SnYcrlqTlm1JerzOTFPpFrEKUt3zO8IgTIWKQ gR5sl/RE1nLmDa1E/QNKltDMShA4d0pAc5waiSgqs1qgZCCbtLeVNpuHQUVxNAxaJBdv 7e4yi/SDpEX1mUUip9JOAsfQ4UHCZ2AlcoIpZiygPMQOIZ5EMZRgmwpqGpX+8eAHjfWP Rm3Q== X-Gm-Message-State: APjAAAUAyA0muCwjeThWb3u35cP552V55eQ63qDpu08dnXOO/3WijY16 wNxoWzQijO33iuOO5xZOAvvcvQ== X-Received: by 2002:a5d:6a0c:: with SMTP id m12mr10285212wru.57.1552502426207; Wed, 13 Mar 2019 11:40:26 -0700 (PDT) Received: from arch-late.localdomain ([87.196.73.151]) by smtp.gmail.com with ESMTPSA id p17sm3829660wmi.35.2019.03.13.11.40.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Mar 2019 11:40:25 -0700 (PDT) From: Rui Miguel Silva To: Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , Shawn Guo , Rob Herring , Fabio Estevam Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v3 6/6] MAINTAINERS: add entry for fxas21002c gyro driver Date: Wed, 13 Mar 2019 18:40:02 +0000 Message-Id: <20190313184002.2501-7-rui.silva@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190313184002.2501-1-rui.silva@linaro.org> References: <20190313184002.2501-1-rui.silva@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add me as maintainer of the nxp fxas21002c gyroscope driver. Signed-off-by: Rui Miguel Silva --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.20.1 diff --git a/MAINTAINERS b/MAINTAINERS index d8e0c9040736..a164bc9fc2d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10899,6 +10899,16 @@ F: Documentation/ABI/stable/sysfs-bus-nvmem F: include/linux/nvmem-consumer.h F: include/linux/nvmem-provider.h +NXP FXAS21002C DRIVER +M: Rui Miguel Silva +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/gyroscope/fxas21002c.txt +F: drivers/iio/gyro/fxas21002c_core.c +F: drivers/iio/gyro/fxas21002c.h +F: drivers/iio/gyro/fxas21002c_i2c.c +F: drivers/iio/gyro/fxas21002c_spi.c + NXP SGTL5000 DRIVER M: Fabio Estevam L: alsa-devel@alsa-project.org (moderated for non-subscribers)