From patchwork Wed Nov 16 12:35:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 625169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A96FC43217 for ; Wed, 16 Nov 2022 12:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239010AbiKPMgs (ORCPT ); Wed, 16 Nov 2022 07:36:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231403AbiKPMgb (ORCPT ); Wed, 16 Nov 2022 07:36:31 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3B491262F for ; Wed, 16 Nov 2022 04:35:24 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id l14so29698867wrw.2 for ; Wed, 16 Nov 2022 04:35:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NByFCuUAaW4OorBUL4tvtlh/sf8BMWr3RB7zpoFsbEY=; b=jFpK/7TinwA7mXto6JKWGrObV8/S8tAvxAE678KBCTJZntoHqrlFIAaFDbAk1AaWEW 4O43MiNcBsqKuLnqXraQg/DFcFvF7P5j5DBQTI5NwxP4C1+BbzHXW1AnS4jvU0vjLQnb fwnloMz8XX7vpX0MhAhs445MfnXdncRblVX8qzW7MMb5KlArLTH7CrDXD5BdpTNzO8fo ZPujJr3pTBpoWADmWdtd8tCi7z+MGrdtMSKMdpw2pdcWs6nJll1v6eYORAD6Hc+MDUOW 5EAaI//lg9slmYzmbYfDLtCAluF8PBpbiWbOuZaq8v0yH1KogHNGUkeLbM6t281Bn/Yg VDoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NByFCuUAaW4OorBUL4tvtlh/sf8BMWr3RB7zpoFsbEY=; b=M9uPShSjPSW2MdIM3mN27sZBlwdMiwve4RtcOd3Jb9alijtfBLsKeDo91FpPh2MF8p thfpQiT/l/8reysi6fNovmURXD8VjNtEmbqR9DZaEgDGP8na+KlE5QaqpEb/DoprcQU9 JMhpLeUUAQoBPtIebaqcsjKBkmBFDgjwo6MryobEYyza9i15hT/msmlNrksxmyKfGat1 J7uWFHn4lEQ0O8n78r+psNEO06Tz2GIOaaUJZSMRTxH1gxp0/6PMF95+/Wie+ot1b87k QUcLGA4ovbtv2mz1H6Z7MVtnLZXWF5iVYFHUh4nJ5tRzmdZwC2DLMvfwS/9GTM2jgc1z 6eGA== X-Gm-Message-State: ANoB5pmvI96sqS4b4QTdbJSl1XAqDAuY+fB12ETANXZRzgmZhBddpWo0 q26Gp/fl8IRbWhC5wXwltLjCyg== X-Google-Smtp-Source: AA0mqf7MAq4RmLvD2UaXGN76VxewI6inkoZgXyxEzmwwnzjidbH7Xj2NCcbDhX5iKvZR7j7hiE4IzA== X-Received: by 2002:a5d:6044:0:b0:241:9a71:8938 with SMTP id j4-20020a5d6044000000b002419a718938mr4824317wrt.105.1668602123250; Wed, 16 Nov 2022 04:35:23 -0800 (PST) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id d20-20020a1c7314000000b003cfcf9f9d62sm1959925wmb.12.2022.11.16.04.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 04:35:22 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Manivannan Sadhasivam , Lorenzo Pieralisi , Rob Herring , kw@linux.com, Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: PCI: qcom: Add SM8550 to binding Date: Wed, 16 Nov 2022 14:35:04 +0200 Message-Id: <20221116123505.2760397-1-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the SM8550 platform to the binding. Signed-off-by: Abel Vesa --- .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..efa01a8411c4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -34,6 +34,8 @@ properties: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 - qcom,pcie-ipq6018 reg: @@ -92,6 +94,10 @@ properties: power-domains: maxItems: 1 + enable-gpios: + description: GPIO controlled connection to ENABLE# signal + maxItems: 1 + perst-gpios: description: GPIO controlled connection to PERST# signal maxItems: 1 @@ -187,6 +193,8 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 then: properties: reg: @@ -601,6 +609,92 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550-pcie0 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + interconnects: + maxItems: 1 + interconnect-names: + const: icc_path + iommus: + maxItems: 1 + iommu-map: + maxItems: 2 + power-domains: + maxItems: 1 + power-domain-names: + const: gdsc + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550-pcie1 + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock + interconnects: + maxItems: 1 + interconnect-names: + const: icc_path + iommus: + maxItems: 1 + iommu-map: + maxItems: 2 + power-domains: + maxItems: 1 + power-domain-names: + const: gdsc + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: pcie_1_link_down_reset # PCIe link down reset + - if: properties: compatible: @@ -672,6 +766,8 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 then: oneOf: - properties: From patchwork Wed Nov 16 12:35:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 625571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8476C433FE for ; Wed, 16 Nov 2022 12:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239036AbiKPMgw (ORCPT ); Wed, 16 Nov 2022 07:36:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238944AbiKPMgd (ORCPT ); Wed, 16 Nov 2022 07:36:33 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7E7D12AB6 for ; Wed, 16 Nov 2022 04:35:25 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id v1so29658444wrt.11 for ; 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Wed, 16 Nov 2022 04:35:24 -0800 (PST) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id d20-20020a1c7314000000b003cfcf9f9d62sm1959925wmb.12.2022.11.16.04.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 04:35:24 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Manivannan Sadhasivam , Lorenzo Pieralisi , Rob Herring , kw@linux.com, Krzysztof Kozlowski Cc: Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/2] pci: dwc: pcie-qcom: Add support for SM8550 PCIEs Date: Wed, 16 Nov 2022 14:35:05 +0200 Message-Id: <20221116123505.2760397-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221116123505.2760397-1-abel.vesa@linaro.org> References: <20221116123505.2760397-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatibles for both PCIe G4 and G3 found on SM8550. Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa --- drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6ac28ea8d67d..4a62b2500c1d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -181,7 +181,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1206,6 +1206,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_pcie_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1752,6 +1753,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550-pcie0", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550-pcie1", .data = &cfg_1_9_0 }, { } };