From patchwork Thu Nov 17 12:37:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 625506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67F32C4332F for ; Thu, 17 Nov 2022 12:34:40 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 72EDE16BD; Thu, 17 Nov 2022 13:33:48 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 72EDE16BD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1668688478; bh=mriXUUv4YdVpJ92OHSjzRqvTpbgG5OABDyze4/Hv4to=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Mq0EhvEX10yMaL8HylOVQaXq4GP7VB17oLHP8U8bcb4yAlwwa8TpD6/FWRhjAl1vY 4GLhIihrejN4lziwRJJX6fru4ptOwEPYN8k2nskoglNyTPtkHy8G75H2skcs/xaYj1 C3YPoX5xAc8hcEPt2ccBsyFqsmhrfjYfiuDK4gKM= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 1B74EF80526; Thu, 17 Nov 2022 13:33:30 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 95653F80526; Thu, 17 Nov 2022 13:33:28 +0100 (CET) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 5B93DF800B5 for ; Thu, 17 Nov 2022 13:33:17 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 5B93DF800B5 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Qgk9D3Xi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668688400; x=1700224400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mriXUUv4YdVpJ92OHSjzRqvTpbgG5OABDyze4/Hv4to=; b=Qgk9D3Xiz7o7F5B92Y838hCf4oVVCx83RxnmBkaGeDWmF2daBJFFMMHm h7eY4RJXYKe8ElUUHiXv1Iagim302GIKSF7y0l1fMIhmfDefgdK/49fB0 yYNDOGK17Q96RBC19kEuHdaQivDqQhJIjqvz+GBwztNQkNdEkBJnwHlri 2awalvPEkYLO30WvHX4TNv62UJ5KBv9/iPJc7cTvbY1JlnFD8DTF+OxRE IF5/Lt8umYOS4tKa+8DciPLZj80JANUt53bO5UpTXRwW4MyV2d3rYU0n8 mlycEGe0c5OjWd77sqpIr9vJXcXWoRReELlV0ygHmbqh8o47eylr6kdg8 w==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183977381" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 05:33:08 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 05:33:06 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 05:33:03 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH 1/3] ASoC: mchp-spdiftx: simplify locking around ctrl->ch_stat Date: Thu, 17 Nov 2022 14:37:48 +0200 Message-ID: <20221117123750.291911-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221117123750.291911-1-claudiu.beznea@microchip.com> References: <20221117123750.291911-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Use a temporary variable to keep the AES3 value. With this a spin_unlock_irqrestore() call has been removed from the final code. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdiftx.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c index ab2d7a791f39..4e231cec9045 100644 --- a/sound/soc/atmel/mchp-spdiftx.c +++ b/sound/soc/atmel/mchp-spdiftx.c @@ -355,6 +355,7 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, struct mchp_spdiftx_mixer_control *ctrl = &dev->control; u32 mr; unsigned int bps = params_physical_width(params) / 8; + unsigned char aes3; int ret; dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", @@ -440,48 +441,48 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, mr |= SPDIFTX_MR_BPS(bps); - spin_lock_irqsave(&ctrl->lock, flags); - ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; switch (params_rate(params)) { case 22050: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050; + aes3 = IEC958_AES3_CON_FS_22050; break; case 24000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000; + aes3 = IEC958_AES3_CON_FS_24000; break; case 32000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000; + aes3 = IEC958_AES3_CON_FS_32000; break; case 44100: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100; + aes3 = IEC958_AES3_CON_FS_44100; break; case 48000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000; + aes3 = IEC958_AES3_CON_FS_48000; break; case 88200: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200; + aes3 = IEC958_AES3_CON_FS_88200; break; case 96000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000; + aes3 = IEC958_AES3_CON_FS_96000; break; case 176400: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400; + aes3 = IEC958_AES3_CON_FS_176400; break; case 192000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000; + aes3 = IEC958_AES3_CON_FS_192000; break; case 8000: case 11025: case 16000: case 64000: - ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID; + aes3 = IEC958_AES3_CON_FS_NOTID; break; default: dev_err(dev->dev, "unsupported sample frequency: %u\n", params_rate(params)); - spin_unlock_irqrestore(&ctrl->lock, flags); return -EINVAL; } + spin_lock_irqsave(&ctrl->lock, flags); + ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS; + ctrl->ch_stat[3] |= aes3; mchp_spdiftx_channel_status_write(dev); spin_unlock_irqrestore(&ctrl->lock, flags); From patchwork Thu Nov 17 12:37:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 626144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D64EC4332F for ; Thu, 17 Nov 2022 12:35:08 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 706D416BB; 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17 Nov 2022 05:33:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 05:33:11 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 05:33:07 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH 2/3] ASoC: mchp-spdiftx: add runtime pm support Date: Thu, 17 Nov 2022 14:37:49 +0200 Message-ID: <20221117123750.291911-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221117123750.291911-1-claudiu.beznea@microchip.com> References: <20221117123750.291911-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add runtime PM support for Microchip SPDIFTX driver. The runtime PM APIs disables/enables IP's clock and enables/disable caching for regmap. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdiftx.c | 116 ++++++++++++++++++++++++--------- 1 file changed, 86 insertions(+), 30 deletions(-) diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c index 4e231cec9045..ec454e64d85c 100644 --- a/sound/soc/atmel/mchp-spdiftx.c +++ b/sound/soc/atmel/mchp-spdiftx.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -175,6 +176,7 @@ static const struct regmap_config mchp_spdiftx_regmap_config = { .readable_reg = mchp_spdiftx_readable_reg, .writeable_reg = mchp_spdiftx_writeable_reg, .precious_reg = mchp_spdiftx_precious_reg, + .cache_type = REGCACHE_FLAT, }; #define SPDIFTX_GCLK_RATIO 128 @@ -196,7 +198,6 @@ struct mchp_spdiftx_dev { struct clk *pclk; struct clk *gclk; unsigned int fmt; - unsigned int gclk_enabled:1; }; static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) @@ -486,10 +487,9 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, mchp_spdiftx_channel_status_write(dev); spin_unlock_irqrestore(&ctrl->lock, flags); - if (dev->gclk_enabled) { - clk_disable_unprepare(dev->gclk); - dev->gclk_enabled = 0; - } + /* GCLK is enabled by runtime PM. */ + clk_disable_unprepare(dev->gclk); + ret = clk_set_rate(dev->gclk, params_rate(params) * SPDIFTX_GCLK_RATIO); if (ret) { @@ -503,7 +503,7 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, dev_err(dev->dev, "unable to enable gclk: %d\n", ret); return ret; } - dev->gclk_enabled = 1; + dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, params_rate(params) * SPDIFTX_GCLK_RATIO); @@ -523,10 +523,6 @@ static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, regmap_write(dev->regmap, SPDIFTX_IDR, SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); - if (dev->gclk_enabled) { - clk_disable_unprepare(dev->gclk); - dev->gclk_enabled = 0; - } return regmap_write(dev->regmap, SPDIFTX_CR, SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); @@ -709,17 +705,9 @@ static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = { static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) { struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); - int ret; snd_soc_dai_init_dma_data(dai, &dev->playback, NULL); - ret = clk_prepare_enable(dev->pclk); - if (ret) { - dev_err(dev->dev, - "failed to enable the peripheral clock: %d\n", ret); - return ret; - } - /* Add controls */ snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls, ARRAY_SIZE(mchp_spdiftx_ctrls)); @@ -727,19 +715,9 @@ static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai) return 0; } -static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai) -{ - struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(dev->pclk); - - return 0; -} - static struct snd_soc_dai_driver mchp_spdiftx_dai = { .name = "mchp-spdiftx", .probe = mchp_spdiftx_dai_probe, - .remove = mchp_spdiftx_dai_remove, .playback = { .stream_name = "S/PDIF Playback", .channels_min = 1, @@ -763,6 +741,54 @@ static const struct of_device_id mchp_spdiftx_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids); +static int mchp_spdiftx_runtime_suspend(struct device *dev) +{ + struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); + + regcache_cache_only(spdiftx->regmap, true); + + clk_disable_unprepare(spdiftx->gclk); + clk_disable_unprepare(spdiftx->pclk); + + return 0; +} + +static int mchp_spdiftx_runtime_resume(struct device *dev) +{ + struct mchp_spdiftx_dev *spdiftx = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(spdiftx->pclk); + if (ret) { + dev_err(spdiftx->dev, + "failed to enable the peripheral clock: %d\n", ret); + return ret; + } + ret = clk_prepare_enable(spdiftx->gclk); + if (ret) { + dev_err(spdiftx->dev, + "failed to enable generic clock: %d\n", ret); + goto disable_pclk; + } + + regcache_cache_only(spdiftx->regmap, false); + regcache_mark_dirty(spdiftx->regmap); + ret = regcache_sync(spdiftx->regmap); + if (ret) { + regcache_cache_only(spdiftx->regmap, true); + clk_disable_unprepare(spdiftx->gclk); +disable_pclk: + clk_disable_unprepare(spdiftx->pclk); + } + + return ret; +} + +static const struct dev_pm_ops mchp_spdiftx_pm_ops = { + RUNTIME_PM_OPS(mchp_spdiftx_runtime_suspend, mchp_spdiftx_runtime_resume, + NULL) +}; + static int mchp_spdiftx_probe(struct platform_device *pdev) { struct mchp_spdiftx_dev *dev; @@ -827,29 +853,59 @@ static int mchp_spdiftx_probe(struct platform_device *pdev) dev->regmap = regmap; platform_set_drvdata(pdev, dev); + pm_runtime_enable(dev->dev); + if (!pm_runtime_enabled(dev->dev)) { + err = mchp_spdiftx_runtime_resume(dev->dev); + if (err) + return err; + } + dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR; dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); if (err) { dev_err(&pdev->dev, "failed to register PMC: %d\n", err); - return err; + goto pm_runtime_suspend; } err = devm_snd_soc_register_component(&pdev->dev, &mchp_spdiftx_component, &mchp_spdiftx_dai, 1); - if (err) + if (err) { dev_err(&pdev->dev, "failed to register component: %d\n", err); + goto pm_runtime_suspend; + } + + return 0; + +pm_runtime_suspend: + if (!pm_runtime_status_suspended(dev->dev)) + mchp_spdiftx_runtime_suspend(dev->dev); + pm_runtime_disable(dev->dev); return err; } +static int mchp_spdiftx_remove(struct platform_device *pdev) +{ + struct mchp_spdiftx_dev *dev = platform_get_drvdata(pdev); + + if (!pm_runtime_status_suspended(dev->dev)) + mchp_spdiftx_runtime_suspend(dev->dev); + + pm_runtime_disable(dev->dev); + + return 0; +} + static struct platform_driver mchp_spdiftx_driver = { .probe = mchp_spdiftx_probe, + .remove = mchp_spdiftx_remove, .driver = { .name = "mchp_spdiftx", .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids), + .pm = pm_ptr(&mchp_spdiftx_pm_ops) }, }; From patchwork Thu Nov 17 12:37:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 625505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D39F8C4332F for ; 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X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="189407195" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 05:33:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 05:33:16 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 05:33:12 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH 3/3] ASoC: mchp-spdiftx: add support for system suspend/resume Date: Thu, 17 Nov 2022 14:37:50 +0200 Message-ID: <20221117123750.291911-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221117123750.291911-1-claudiu.beznea@microchip.com> References: <20221117123750.291911-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Add support for system suspend/resume by moving the enable/disable of interrupts in mchp_spdiftx_trigger() on SNDRV_PCM_TRIGGER_SUSPEND/ SNDRV_PCM_TRIGGER_RESUME commands. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdiftx.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c index ec454e64d85c..dc96a6fbf514 100644 --- a/sound/soc/atmel/mchp-spdiftx.c +++ b/sound/soc/atmel/mchp-spdiftx.c @@ -198,6 +198,7 @@ struct mchp_spdiftx_dev { struct clk *pclk; struct clk *gclk; unsigned int fmt; + unsigned int suspend_irq; }; static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev) @@ -318,16 +319,25 @@ static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd, running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); switch (cmd) { - case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_START: + regmap_write(dev->regmap, SPDIFTX_IER, dev->suspend_irq | + SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); + dev->suspend_irq = 0; + fallthrough; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!running) { mr &= ~SPDIFTX_MR_TXEN_MASK; mr |= SPDIFTX_MR_TXEN_ENABLE; } break; - case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: + regmap_read(dev->regmap, SPDIFTX_IMR, &dev->suspend_irq); + fallthrough; + case SNDRV_PCM_TRIGGER_STOP: + regmap_write(dev->regmap, SPDIFTX_IDR, dev->suspend_irq | + SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); + fallthrough; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (running) { mr &= ~SPDIFTX_MR_TXEN_MASK; @@ -507,10 +517,6 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream, dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__, params_rate(params) * SPDIFTX_GCLK_RATIO); - /* Enable interrupts */ - regmap_write(dev->regmap, SPDIFTX_IER, - SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); - regmap_write(dev->regmap, SPDIFTX_MR, mr); return 0; @@ -521,9 +527,6 @@ static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream, { struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai); - regmap_write(dev->regmap, SPDIFTX_IDR, - SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR); - return regmap_write(dev->regmap, SPDIFTX_CR, SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR); } @@ -785,6 +788,7 @@ static int mchp_spdiftx_runtime_resume(struct device *dev) } static const struct dev_pm_ops mchp_spdiftx_pm_ops = { + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) RUNTIME_PM_OPS(mchp_spdiftx_runtime_suspend, mchp_spdiftx_runtime_resume, NULL) };