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[174.21.5.201]) by smtp.gmail.com with ESMTPSA id m7sm40267530pgg.62.2019.03.25.09.13.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 25 Mar 2019 09:13:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 09:13:38 -0700 Message-Id: <20190325161338.6536-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62e Subject: [Qemu-devel] [PATCH] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, irherder@gmail.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fixes: https://bugs.launchpad.net/bugs/1821430 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96f0ff0ec7..d9b8658921 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2025,6 +2025,11 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = t; + t = cpu->isar.mvfr2; + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 = t; + t = cpu->id_mmfr4; t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ cpu->id_mmfr4 = t;