From patchwork Mon Dec 12 12:32:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D9F1C04FDE for ; Mon, 12 Dec 2022 12:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232210AbiLLMdv (ORCPT ); Mon, 12 Dec 2022 07:33:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232211AbiLLMd1 (ORCPT ); Mon, 12 Dec 2022 07:33:27 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ADC263A2 for ; Mon, 12 Dec 2022 04:33:26 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id v13-20020a17090a6b0d00b00219c3be9830so12032453pjj.4 for ; Mon, 12 Dec 2022 04:33:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=alhK3ndi55Pn+UAZvehWSr5HT0WJYLohN8j26G14+mg=; b=qQu0KWtTsFZWdV2sgVCoDF3kIQeVcPNBTz1gprS37Trlf5kvhITuKFb77t0cE2+p0X ZrHStY317cD6gGjT64Jv9Hs+NJC1Kt8FMbQrJLmJWO+fbzjSkIXQj4xIq9171qJfb54c /bgEAeuR1jxftiiHNG961TjiKDzHELKKP9LIiGhP0K5hOgSWbjV/J84RAqRsuVahWzpD cKlgfh4+JAHYm+nmzxDZBhw1ELNJ+kyoIdFNUzbRbaAmGuuWf0w6b/1M/Fr2faKOzeJQ nIaYxdQQ9WtePfcI2YFxuOIbpk2pzKi59X4wy53mqLHUnp4cx4WVHYitfVc697GcFkYP FJCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=alhK3ndi55Pn+UAZvehWSr5HT0WJYLohN8j26G14+mg=; b=cNPRxx5m6xRFuO6QJO6oUtnKekNyyVgiKqa2rXrQOSHeeh2/s9qzmWFH5Fny5nzkYH MIZREswDSozSnTDN808bS6xa8XULzV23a8sV7t2kwh+WUI8FV8O8fr4twJf2IABkr7Ik jykqdAoONaMXnMF0ec/2aQYD5W1sBLDGH/Qfc/rfKQJy+/qtpUNDHUzKzzGvIfQ5Yy/C C5tepTuKg9AKC41AawPCCKzLC85BQQUZz1lMOPjF2QjRSH2sQr0v+AI35x5YMzBPaOu7 c2vkU4uDORnhz4AtwKODaqmeR9K4vdW1G/YxSiE7fqw/h2bGrFdKoPtYCUzhtQsdOhmf OqYg== X-Gm-Message-State: ANoB5pm2mu+BMM4S+gk3JYm/RZaWA6KHatq0sB8QU4u230hla5vB1qzc xwzSFzeeAWb5lgVmMogtxw/J X-Google-Smtp-Source: AA0mqf76W0vYctaP4uQGyTxz6lzA6fM+RGW0zYYAEweKJgILQ/VqIjWxTs1rUO32oLY1EHGDhJaxmA== X-Received: by 2002:a17:902:9b97:b0:189:9e91:762e with SMTP id y23-20020a1709029b9700b001899e91762emr15738614plp.57.1670848406037; Mon, 12 Dec 2022 04:33:26 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:25 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam Subject: [PATCH v2 01/13] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Mon, 12 Dec 2022 18:02:59 +0530 Message-Id: <20221212123311.146261-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Mon Dec 12 12:33:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29704C10F1E for ; Mon, 12 Dec 2022 12:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232266AbiLLMeJ (ORCPT ); Mon, 12 Dec 2022 07:34:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232144AbiLLMdo (ORCPT ); Mon, 12 Dec 2022 07:33:44 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF6A011A01 for ; Mon, 12 Dec 2022 04:33:32 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id 3-20020a17090a098300b00219041dcbe9so12039926pjo.3 for ; Mon, 12 Dec 2022 04:33:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oXSmdk6KZcIB/MFPzIeXJxotTRaDgWgu6sR2dSlOVP0=; b=hv669BzV1GDNlxLlrOcoVm+wZFU1E1dKb985Oy4y+3WWBByJI+PVqNf5hJY0BN4E/q 5XDqW3GoxNLDANL9Lkg/AWRhGGcDk1bRmE8HeglDBEKSMpLXNx039ApHC7e6ojmd1KhZ nP/65XIPZvSzoowT/qkd/5N3jSiueIsvUQknSWl51tUQkhEk641YuaNH9ua52p0Kj3Q0 4rpH6aJPHKdnyyIP2fY20R7F1A/PbhT6omNtN3Y9DxrPUGTmpFrEq9p1CmcXNBfgu/o8 Tvk3RDOE1/tZO4l2AouDY/HPxnAgTd3gUZ64g+wS0cFNuXJY2Ls9P6WU8Pkab/KAfjM4 ZQaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oXSmdk6KZcIB/MFPzIeXJxotTRaDgWgu6sR2dSlOVP0=; b=oM+198LnW31bL0jePSqnPr026F8iKLNhdaYpV36i4+cXaRQYDiKorWJ6AGfJNmP6mK aAltCZipMQu+zIxtNhJICzJBUjVwYbrXmEdkv5fEkwNB0kxpSAR3QIJA/7ucdQRMFLZG lBmPpOSXmXHndSu1n0daDWFJ9xVPGypmh8JPX9EV5NfzrOSk+718CtA6qoi8M573H37L if06rR6SJBaqz5baqPR4Uo9vgVMlIZqp8rKSsRa3DO2yQT9hF+sAJZ+Zzk36fh2vPM4D r+4cfI4TkIo5vHUREHKo/HTmQGx31T1gpVCPoVSaHrDMMl2DD7FWKDMH6NeTFkWSMTYA j3mQ== X-Gm-Message-State: ANoB5pkjClu5edEPK7/dfh4e+5QINYk3mjLp9veUTzeNDlkAJz+UCZxL d0Pcd8vwM9ZKwtUBuHGpcNNN X-Google-Smtp-Source: AA0mqf5zntEOyVqCEcUq2ZkGjr9XJImnZH+hxKgv86NAMpOZsFNEIoQU+AqnBq0L2/jaq6TH8Ad3QA== X-Received: by 2002:a17:903:240c:b0:188:9806:2e2b with SMTP id e12-20020a170903240c00b0018898062e2bmr16266852plo.35.1670848412076; Mon, 12 Dec 2022 04:33:32 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:31 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 02/13] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Mon, 12 Dec 2022 18:03:00 +0530 Message-Id: <20221212123311.146261-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register regions of the LLCC banks are located at separate addresses. Currently, the binding just lists the LLCC0 base address and specifies the size to cover all banks. This is not the correct approach since, there are holes and other registers located in between. So let's specify the base address of each LLCC bank and get rid of reg-names property as it is not needed anymore. It should be noted that the bank count differs for each SoC, so that also needs to be taken into account in the binding. Cc: # 4.19 Fixes: 7e5700ae64f6 ("dt-bindings: Documentation for qcom, llcc") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 97 ++++++++++++++++--- 1 file changed, 83 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..260bc87629a7 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,8 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region - - reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -48,7 +42,76 @@ properties: required: - compatible - reg - - reg-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region additionalProperties: false @@ -56,9 +119,15 @@ examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + interrupts = ; + }; }; From patchwork Mon Dec 12 12:33:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C116C4708D for ; Mon, 12 Dec 2022 12:34:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232344AbiLLMeX (ORCPT ); Mon, 12 Dec 2022 07:34:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232307AbiLLMdt (ORCPT ); Mon, 12 Dec 2022 07:33:49 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5728212636 for ; Mon, 12 Dec 2022 04:33:39 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id d7so11910301pll.9 for ; Mon, 12 Dec 2022 04:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8DCGU+aMFvu/t7Kdt87B6ewuHaXNeU8yBLP9UTUdSuo=; b=gt0eqdCyD/xGUbqsYqfrngyYsrqK9QOlFwwq5V0wiyqyuVsJ0XYiJoVcs304lD79by nfoiBMRcqh8n8Q2vXkF2NRRRx+/FRIiKbCnmjmKTjXvJvmMiXTexA3yXUTOmWK+6RYcs YtiXkhb5S0aw4+vrDdbRetdp/KzmY+9B+LLSp+XRlHP/M9OWtmXmy81+mVulJvxEkzKb VXmc3Gk5oejNX9e+I1gLyvBNc6Ir50w6TiAFSW16DL+m0JVjFpdYt+hSchW8LM9yR1Qe j67tSLY38LWPfyNePkw9ilDV7uCAPNn84Qzy/PqMiNJV4YsLXYN7egHZibbWSHp3lQ9j yZKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8DCGU+aMFvu/t7Kdt87B6ewuHaXNeU8yBLP9UTUdSuo=; b=I89FFZoVCuDggwJzV+iFM4+UeQRsHuECvDDlIwWNg4N9rN+qL+bd4mIenjgVJ6ERtN E7LX2tEp+nQGPXxfB0qTLne9m14wj/rQ6dO+6iXyZYZRwcGPO88o445KRAdcz+kpY7f5 RHbSREZb9qhmYcm1OnWHnWv1ekFFYJON07bV2kisagWqIDspE9Nt/dDwIHg3BHP/8Wh/ 1iSs69rZrL+/nE6xVzPivW6UsqTVMPuoo3iGpk6BHv5ecS0W243MX2smpVK30qFFRdSG dsHZepACZqRzQANOp8zVp6ljNew8tyesDue77RNPF3OeT9fm4s0lT4BORlnEpGODZgku XmfA== X-Gm-Message-State: ANoB5pnCqF4aFOTrNY3Sl9oIWRQQYhkuuSkVV2URAnTYsrwu0KmEnMiV Sduy5M0nDFU90/0pYNs08uup X-Google-Smtp-Source: AA0mqf6IfrLFwIA8ynXUBacuNjHqllcfNnQ/gFd1xeUcH7C00ttYD08/6fbvdYg+JEHAjPH1C6IWeQ== X-Received: by 2002:a17:903:2786:b0:189:f69d:d5cc with SMTP id jw6-20020a170903278600b00189f69dd5ccmr16939456plb.58.1670848418819; Mon, 12 Dec 2022 04:33:38 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:37 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:01 +0530 Message-Id: <20221212123311.146261-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.4 Fixes: ba0411ddd133 ("arm64: dts: sdm845: Add device node for Last level cache controller") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..683b861e060d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,9 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; interrupts = ; }; From patchwork Mon Dec 12 12:33:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92EDAC4167B for ; Mon, 12 Dec 2022 12:34:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231651AbiLLMen (ORCPT ); Mon, 12 Dec 2022 07:34:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232144AbiLLMeK (ORCPT ); Mon, 12 Dec 2022 07:34:10 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CAD562DD for ; Mon, 12 Dec 2022 04:33:45 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id d3so11907514plr.10 for ; Mon, 12 Dec 2022 04:33:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9tZFt9KOuRAc3YbaSpnuN3NeGcAiDnj5wQSKgrmzEBE=; b=NgJfy3y1hxcURsOqlHdWS+iXmzermi8gevcmy7kSd5IFztlubqTi1w8oncpQZ95Esd M979Lh+21IH1kwZWSOZH2yxTsSuykgsoM7SkJQZP6WmvBi752JU2YwGhmR6MlNb+GT9H cEeENCFO/fuf8eEyCaiO6G38GYWw/mGpNBBO03360wE815rAF8u4FX1Hg0nxehWliJeo 63PbPcqrRaun17whvOD8yYl7NgPzZeZTIn3aQSwzIjYjRsRjEdPQ+Ll+u4B3l7fcOMcE /lqjZrQYbUpTjEjLnGd6N+RC62W1v5V3ukN+m/KdL0u8MJaowC3cXv0ChtAP9xBdGmDx F7+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9tZFt9KOuRAc3YbaSpnuN3NeGcAiDnj5wQSKgrmzEBE=; b=XTo/jSeW5dbgMkJIN2WEM1jfY0bmLHFpZI7/ZhrWujPX32d1ll4WMMqdKPuaTbffeR npCY9z8cexSDJQonO7ub0clHbEi4f8m3hroaOr6pYvAlQORMZcdc3YBSN5PM7nZ7Algw BiHU4ikK/t0iOWHySsFhTUFfcmC4TrlBA1aYQGXQlNEBJkgoe+EPmZ2us8tvqEMUGx4U NGIrwFgOt73OMfrSNUuGUJ6m8RGJqOQO0x57mgYVKmYZJPgqkhAjw6EgJv9/9CyxDKES H+FRIyyNM4XazSOTpfs5C8KNEAFws+Qis6jigx69F5F8OKLiJSwEYhH/3oNkLxACoRNe vLYQ== X-Gm-Message-State: ANoB5pkIkEF8XZyhyylS+ZkDyEfWbpGBL8D3NnboB80QH7/gUQ6T7BLM wDm8AeJxYmOHaVVA2XYSBkrs X-Google-Smtp-Source: AA0mqf4ZO7xOmzA0pOR37AT59jPOz3Pbf+sfGigNiDnLJ7MxsEdWnhOZEtM/acfMFg3KN5mS/rC8PQ== X-Received: by 2002:a17:902:9b8d:b0:186:605b:7527 with SMTP id y13-20020a1709029b8d00b00186605b7527mr15249024plp.48.1670848424742; Mon, 12 Dec 2022 04:33:44 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 04/13] arm64: dts: qcom: sc7180: Remove reg-names property from LLCC node Date: Mon, 12 Dec 2022 18:03:02 +0530 Message-Id: <20221212123311.146261-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So only change needed is to remove the reg-names property from LLCC node to conform to the binding. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.6 Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..b0d524bbf051 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,6 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Mon Dec 12 12:33:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C101DC4332F for ; Mon, 12 Dec 2022 12:34:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232297AbiLLMey (ORCPT ); Mon, 12 Dec 2022 07:34:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232338AbiLLMeX (ORCPT ); Mon, 12 Dec 2022 07:34:23 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00602BF8 for ; Mon, 12 Dec 2022 04:33:50 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so15542489pjr.3 for ; Mon, 12 Dec 2022 04:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=26Q/WBAWFA3UhuhgRAc8FiDDi9U9JvKaLU8PlXNH5WA=; b=cmoELRfDJVkrewKkchK8Em88WWVknErid1uisKdEezigW0Dxn9Ge+SBHmjwBtQ2+E6 YxtuMsyHyxJodHk+b2wox/kY7OCLlbQ4xGpkdViVW0wO/0iKNyLEyBNvUfiDjQtR7IMk HvbBVXEETnyxk2AF22e+0l2ydtor+Lqow9QD7Kg82ZStryQDb7I94QnZBNfp0Jwu5+OO Lw+mClb/FD8uDwx+jfrK7+VrkLzIPl3WZX6DkHEld470Qh7pvK3c5cfrTyKB1XpdSYdk QrymkULlx0ur9VoOLp10l7FJ1BaTvi180PS7epFyTkIz9mmdI7C2sng3kJY/+L+or9NI Isyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=26Q/WBAWFA3UhuhgRAc8FiDDi9U9JvKaLU8PlXNH5WA=; b=HjybvzaUb1XON1rHYSyOXERJqIGtvWa59uWTsER5I6MeAovQ8wCBsRuXmNFBjVLZwy YzRHkrs+5jVNq9q5feJdjxFMpA7in9KbRltzLaaEBCj2cNHHMAxTNbCt62UVCcCEmYnF XdUA4LaNvSa1DkN3YgDItQ5jDAgmtzu4fw6piWJpUmSL5Ge01sysIvogQlv+O2xHI7Ew QJRFJnFVMS6PqG01RIDvEL0Vk+edLCFmUXKPZCWRXfclD51ND0scLH6hjgPYwwVNNvt3 q6OIvziU5akqyWFx1BJyyabWGIE6b04KIMH2xK4IwxKSBdwkovJ5qkCtrAsg8wduu1Oq sUlQ== X-Gm-Message-State: ANoB5plrHqq8+egJwQ09Zu5frOY+riow+vDH8+XaG+iB5y+GVjCOp0p3 4PPjHFTA6dVVq50Xe0YaoYes X-Google-Smtp-Source: AA0mqf5jgJNfNCAjLII3XBF0QHODNVOJ9pQBUhID7O5h5g2Vvqs89cTH4+jNXSevUebDUpoM1bwLGA== X-Received: by 2002:a17:902:aa91:b0:189:b8a2:27ed with SMTP id d17-20020a170902aa9100b00189b8a227edmr14858454plr.57.1670848430595; Mon, 12 Dec 2022 04:33:50 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:03 +0530 Message-Id: <20221212123311.146261-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.13 Fixes: 0392968dbe09 ("arm64: dts: qcom: sc7280: Add device tree node for LLCC") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..90e11cbbaf88 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,8 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; interrupts = ; }; From patchwork Mon Dec 12 12:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9486C4332F for ; Mon, 12 Dec 2022 12:35:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232357AbiLLMfY (ORCPT ); Mon, 12 Dec 2022 07:35:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232214AbiLLMfA (ORCPT ); Mon, 12 Dec 2022 07:35:00 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6A8212621 for ; Mon, 12 Dec 2022 04:34:21 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id e7-20020a17090a77c700b00216928a3917so15533141pjs.4 for ; Mon, 12 Dec 2022 04:34:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QfIwNI7T0psn5lDqNEX4WmRlkGqyl7ZmRdxDmkjkE3o=; b=uUzlkjM9xadP/wsfePCnqjzwimre9NyLsWAauCXIMA4K2H4sdT5xEbloK1SqvMpiI1 RbnWr8fQlEusmTFxO97E6HQ1SY+VLLpx6sUhuDJqsaXMoJP0o5up0rCoTYybXD16bjSA aShFXmtsF5KPZSAIn9B2I/d31rGvMztJVH6vtfl/b++okd4nu9Kk9FPoR8TXLQATuheJ r7UTt35dMuC18r94SFLCEwbfYUALLkwJ6XlpjFzImo2IStVCik4eblWALX0L9c+bkNeQ GGFJuMsb9mYhEuTkKtqKmMrm0wzFYLXUM8ja/vhaEuUngg7DDEcLEW3cLBDuCMUUESHN k2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QfIwNI7T0psn5lDqNEX4WmRlkGqyl7ZmRdxDmkjkE3o=; b=FAtV9aF/nuHlYXajO0eHxSIFzp6g8ljjMP+HFr9OrU2vU8LXFSbzv6tvE3MHuqUuAP 4J5MptVfLfvzLw5uvBEgppnS3nWECclNwkD9Q4gxCkRS8HPFkG7D9saG8oTzD5UXEvbx ye+fy6QkGP31o4sfQXclpSUOPxmiE7RfAc9sXjlJmimNAcQcA9LJ4RYnzw/J3IjSZtB0 2og6NtivVwZibwg0BKwUgcbt/2ciuflPbyL1ny6QOsfxXB59ed7d5fJ6CncHnj8phg7f oDaTRosY2nKQ//ftMdyptHiAF+3pMatvszqkVxZ9hrbXSYP2eMEKJRDbDJ0TeyU1IZKw ME3A== X-Gm-Message-State: ANoB5pmllSEthfE2SKcIz3h2hKY0F+5yljP6ZsUEowaAp11E3f1Vm9xw 6HVm4OsF5J+0TrwZwdSFM5UP X-Google-Smtp-Source: AA0mqf4rE6OP22oNrLonHgu1sGCKwOejdojpWXX0Em5PntzhDOwfs6CtZJREOlEYmIQSwLoJpiBijw== X-Received: by 2002:a17:902:6bc8:b0:188:d2b3:26c1 with SMTP id m8-20020a1709026bc800b00188d2b326c1mr15270890plt.10.1670848437579; Mon, 12 Dec 2022 04:33:57 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:33:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 06/13] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:04 +0530 Message-Id: <20221212123311.146261-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 6.0 Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..f8731cbccce9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,11 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; interrupts = ; }; From patchwork Mon Dec 12 12:33:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3238FC4167B for ; Mon, 12 Dec 2022 12:35:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232395AbiLLMfn (ORCPT ); Mon, 12 Dec 2022 07:35:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232144AbiLLMfJ (ORCPT ); Mon, 12 Dec 2022 07:35:09 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D4C12626 for ; Mon, 12 Dec 2022 04:34:31 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so15533144pje.5 for ; Mon, 12 Dec 2022 04:34:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eZ3me+mcNSacplSG7BmxN9uUD75qHevGLumn9ggiZjk=; b=Da9bwkmekbWk4IMIUkh88ZGsnj0KJGtXfDc1AWs0hK2XuiZj7jIKdfGvqnFHOM05L1 xR6JxwyCeCelvoW9qSumYDNeBnxnJVaUQ2S68T1zhtqGUQjg/cJC+dOYYP5g9THGora5 SDGBIqU2dYDoe2zPD73pcDBSKsbc+dREy3JgCmBwvtC+q7jJjRMvczc/0073uvJejuwC ajKJaapp4r8hMGUnvmiHYJtCEmDgLdZZUwUBez/Svg6YHD5jLJnN67iaiK+F+8GdxAcD fOIVwnxt/IIv7hVxyv5RESNOEGJRRe4D2svwqcttfGbyePU33mqv1f49V5zCr4l1aqfT jTBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZ3me+mcNSacplSG7BmxN9uUD75qHevGLumn9ggiZjk=; b=kpl4SmDCIqje02M69CwgRcuIhcjDA3BVc59QYn0rv6Vml4NuDFxA2erdro0T8FcdNL Gwu2wvYseDZ0y6ivw8WvWnnflXb5K+x951G8icsjFrqX8+VZ+zGcCB1aDjVu3QpkXG3D fowXZk7RVjWqUHX1AHSKSIPsOX6ZCkisPGsCq4ulZysQwx5tO80mIiICG9mSO+HmCoDH u7c6dzOItNcX7l/iR28ckSR6dl4YPbjndeV8MZsJQWps2S91vdmrU+NPH4iZRiHyCybN EafLsEuoPLGoP9MNPeKyoE4v0HQ8SC/kuhhE93zztwUdsIrdEzq4Ud5+/xzaDoiGt3Dn J1PA== X-Gm-Message-State: ANoB5pny/TQwqwz0Mnx4GXf9JMqNi6tDD84mhdYoF+nJ8n5OyddMci/B cbYtwEhi3G6qZQOB2sn7ukBC X-Google-Smtp-Source: AA0mqf5oz4xPavmtcpkaaihKxi2KT6i0eyqqiNNAYWS76y+0yOB1iu5CKW4I5DkFxH+YhyRV2K57Ag== X-Received: by 2002:a17:902:9b8d:b0:186:605b:7527 with SMTP id y13-20020a1709029b8d00b00186605b7527mr15250039plp.48.1670848443991; Mon, 12 Dec 2022 04:34:03 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:03 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 07/13] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:05 +0530 Message-Id: <20221212123311.146261-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.11 Fixes: bb1f7cf68a2d ("arm64: dts: qcom: sm8150: Add LLC support for sm8150") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..958655bf5b1a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,9 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; interrupts = ; }; From patchwork Mon Dec 12 12:33:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DACD4C4332F for ; Mon, 12 Dec 2022 12:35:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232146AbiLLMfq (ORCPT ); Mon, 12 Dec 2022 07:35:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232270AbiLLMfM (ORCPT ); Mon, 12 Dec 2022 07:35:12 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECC6413CD0 for ; Mon, 12 Dec 2022 04:34:35 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id g10so11909081plo.11 for ; Mon, 12 Dec 2022 04:34:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w1T81HxDJP60aMe8zkxEbatF3LDjVT92Yb8ZgaRaQ8U=; b=RbZaWt4JjHpC7wHc8DiR0ugxsqYVlSs/Ui0Tp+KU9MJDZo0efJx78afFLwZSmZGoBC UzhPhAktJRTlz2NIBzcfKmDVZKKu11egZcWrdK4bf/M6hbtuhL44fbEzU54WhkgUFUT1 d4Z5SJwxmhrTa+17dD/7/Nt1BQkIilRDI6pY21zaQf4atZ2ybOLN9oHQr67QYa88ViaV zr7Lvt4qFgJoUjIv6bJsym10KzgGmjmFZ8vdzgF7Zv80bGeD8FUjdi+3p9e0CwmBbBW6 PoFdCBcuDZzfnlOnFzpBJzXLo2ACL8ehLJz5KvdA1k6fqk3oN7Y10U9moixr943CGIWl SOKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w1T81HxDJP60aMe8zkxEbatF3LDjVT92Yb8ZgaRaQ8U=; b=1yPei1YwEXIP9G/E7W/WId1MnYmFXtecZoX6BivKcrHQXvNI/lrufa6uU4r5ddAXaF nKk4zvClnKQLU2XLkBnKO9nDW0hlSNFjbpk3c5gT166dRnugmM4Kda23VhTnFnJ3x86+ rcW0l71ttYkrQd5OAlg4Yx71r4ZDx4F1athegAKK6+ahp4OtI40L7X+4EYMJ8DywmeWk Wz6OKpyG+6bqZtP/+A/XB9sCu71c1gq6QUR1ioMijX/TRHkbxrXZnppN1Q83BWzU2Tgi wh1CaV1f5Bvpz2DXdZ3rU873cnnYcvxeKMN3S3pbxCHGMN0ysjv4ACJOBebGio8nqLgw pXgg== X-Gm-Message-State: ANoB5pklrn5KbI85okZqyJ9yANe/K3oas9zAUAYnl5XtXiRWdO7RpazY pZ6xyq+jzX5rD76AkTKtlt9S X-Google-Smtp-Source: AA0mqf5QoseNbK6SZLeykYOD214kolF+tAQknwNU6NkDpajx8Lphd/ctc5F9DtRkmA0s7Ib+bsztsQ== X-Received: by 2002:a17:902:b20c:b0:189:3308:9a2b with SMTP id t12-20020a170902b20c00b0018933089a2bmr15457836plr.7.1670848450047; Mon, 12 Dec 2022 04:34:10 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:09 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 08/13] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:06 +0530 Message-Id: <20221212123311.146261-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.12 Fixes: 0085a33a25cc ("arm64: dts: qcom: sm8250: Add support for LLCC block") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..439ca5f6000e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,9 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; }; usb_2: usb@a8f8800 { From patchwork Mon Dec 12 12:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73C3AC4167B for ; Mon, 12 Dec 2022 12:36:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232283AbiLLMf7 (ORCPT ); Mon, 12 Dec 2022 07:35:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231910AbiLLMfQ (ORCPT ); Mon, 12 Dec 2022 07:35:16 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54B9012744 for ; Mon, 12 Dec 2022 04:34:39 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id k88-20020a17090a4ce100b00219d0b857bcso12063016pjh.1 for ; Mon, 12 Dec 2022 04:34:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=apPGFedAv3uAmQAp6xD4tNC7N1DZdKzki801rLgGfFs=; b=rvpNc8D4tUlWJjtdcx6r2kqPUvDpcCZXEVp8rHRZOdG2ZylbdXSlA8X1WBvN3Dcze+ AqowEJ/9OFPO3NuyEVu89W2Orgo1iLJY3jmbYAXE6QvpdTh4I4ctkJMUq90CF/BX7lfL wad84Nmgs7J6W8BRaaSM5GcgN8dmrcwRN9QPNACcBPyZOqhO7pziTJPcx+ht4ft6YBwc i/BcTPWVq4YlLIw/zLf4Ilk/vQEByu5A9DwIWXQ8PkZpSs4Yqg7HOBoJl9OGUjgEvTPj Bcxhyv2FEGNfVvupN4jXpr/eQVVFIgLWmSC16XdVCZQXba6uXFWN1upJfaCW4yOhXL4Q v8WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=apPGFedAv3uAmQAp6xD4tNC7N1DZdKzki801rLgGfFs=; b=NzKF2OUmB619pAobsQof13lxWSiiBfg4oMTvAJocHT5+joCJAbAKGi4HaWMDagKtTJ CHV32+yiGESLGMuPLwBTCa6+KjnXgp5R43IoKE3wGALgCMGOAZzYd0+SZu4GtgZfuBu6 XZKk+PqApcIyZ9JnoVpHWhPV16vQwJu/SZL93Jpg1hRW9DcAwMW/jj/neIvLOcMKqYc+ 0ggWU3PhtmKmqw6/DAy6aDV8n+nEGaDb8ZmnBn0Lnvnk8dGGkczF7jl4rt0Mis5F4ufy DR7j2YhJNi52oiT+ymqGRkIJNV+gDPQhgkE2bhEuaUdooaf6b6Zv3U6zbmHHWrh/OQNm j2+g== X-Gm-Message-State: ANoB5pm2SuMOY7LGThmQK+cMsdOwUeVbQpIqYZKgce9OWdt0WneuApnQ PQVp+DHGOsXPOc1bCIWXm1PE X-Google-Smtp-Source: AA0mqf6+LShJsPN+/zqNTsvXdXBN/B4lMNcCK1WC0YzDvfRhwPh9u2OTOAPd9dPQ9F4U87PLHnaagw== X-Received: by 2002:a17:902:a70b:b0:187:ede:e014 with SMTP id w11-20020a170902a70b00b001870edee014mr15848859plq.44.1670848456668; Mon, 12 Dec 2022 04:34:16 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:15 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 09/13] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:07 +0530 Message-Id: <20221212123311.146261-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.17 Fixes: 9ac8999e8d6c ("arm64: dts: qcom: sm8350: Add LLCC node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..7f76778e1bc8 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; }; usb_1: usb@a6f8800 { From patchwork Mon Dec 12 12:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B66C04FDE for ; Mon, 12 Dec 2022 12:36:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232437AbiLLMgH (ORCPT ); Mon, 12 Dec 2022 07:36:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232036AbiLLMfV (ORCPT ); Mon, 12 Dec 2022 07:35:21 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C86012AF3 for ; Mon, 12 Dec 2022 04:34:42 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id n65-20020a17090a2cc700b0021bc5ef7a14so12084109pjd.0 for ; Mon, 12 Dec 2022 04:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zx2M7VMZ7B8c+kUNjbNWr72iqwdGfw5WQdhiPZvJmow=; b=ChLTkPtBcMiMzezMr5A2k/fcxzH6GZXKGhXafIdMmQy6P5xxxt3QqlY6ZOdjvKYdIN gTsDu0KsZIk9DgOW+KRsCxcvrubIk8wqM8DHr665seHOSOZXZeoRRtJ2S7ghAOKiTbt9 8DDOCLnvdaXmZvuOG4nah8pl273WS2HWpXWWXi819Jq+mXKfGuJP2MU+LHagr9WmzPvy wati+Do384INbDYhAqsCSrN/NCYwhw5llsfJMRWga1SQddsSwPx6ZKsnrNIeCoyG4CRW RPbcBlJETeiMZWwg13OAMGT9Mqu1Dl/U88ulbkvtceR1/CujVA9la+MTowRWGxFt1OXi fLRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zx2M7VMZ7B8c+kUNjbNWr72iqwdGfw5WQdhiPZvJmow=; b=KeeV0kEFWXLrjXjDM3QTeLdYaWU+q8cj/gWAiB8UHthZjLK3zhTebKq+qwF9L+zQES oO6Rg3eOkRTvzqj1uSeHzCzkgDEPXaFbp2zkGu1y45W+ryIQPIX1E3uJcO6d9F+XtFJr mmG4xOIGSgul/yN2hBSCEkqBqcr2REPe7e5fIVBfGODUe7fTpmJyBwM2paYdjsu+s/7F qvpelImNdHRGxPBne6WelWizu6Bk7XfZpyi2Ri3qHHwwNRQE5F4Y7eBRv2E75q6dHrIj 7WISujAeu/H45FS22uxZLCfX8Vgu+pjCQcxEZhE6pe+r8x1wSThd4YtK4LRI4PnnpJsM Eqqw== X-Gm-Message-State: ANoB5pkBE45qFGlldRkGzuGeE5Cm5YpHNJYXdPwf//5WIUDdPI6kGrxN M3n4DwbP8BjmQeeBTz7kMDwL X-Google-Smtp-Source: AA0mqf65ZwsDRJcMCxtsvw68gNbQfCRwWblSmVd+N7SKsXS6LrRiZ0ziBV9T34IccwUe/FcHlbOkjA== X-Received: by 2002:a17:902:e952:b0:189:dc3:ee9c with SMTP id b18-20020a170902e95200b001890dc3ee9cmr18076957pll.65.1670848463236; Mon, 12 Dec 2022 04:34:23 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:22 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 10/13] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Mon, 12 Dec 2022 18:03:08 +0530 Message-Id: <20221212123311.146261-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Also, let's get rid of reg-names property as it is not needed anymore. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.18 Fixes: 1dc3e50eb680 ("arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..30685857021a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,9 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; interrupts = ; }; From patchwork Mon Dec 12 12:33:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 150C1C4167B for ; Mon, 12 Dec 2022 12:36:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232441AbiLLMgJ (ORCPT ); Mon, 12 Dec 2022 07:36:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232369AbiLLMfW (ORCPT ); Mon, 12 Dec 2022 07:35:22 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5830312AFD for ; Mon, 12 Dec 2022 04:34:42 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id a9so11914072pld.7 for ; Mon, 12 Dec 2022 04:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cWyQujEvk1ZvvBEgjMYf46UtX0tdPlQNyeagksROeaI=; b=M+NOjZk3UqxL2qLgCMURy7Ekh48jPeaCcqRn64ULQe7hLXCTrQX/RIV15uLXE6ohIx Q2HQnbsrSIbSM3fwr3TKe+sjv/qq6aWEPaxcckJhx/TpQqTtFwU1ndqGT1K+U5ek5cKf 1duNN7KH4MkKiz/3HAoUeuIgmOFaW4PtKxAD7Pkyn2roSKdAbEftDLUCgfVD8CKh1QtM Dng++ZhI/2ylK4xxS2ARFK5UT+ZZLyjtG4M2XZ1xvKrNsCuyotdLqReA4+QAMZ9/zTYi KNFh6iGZtfi+Yot+VNHfjOz2/VhOIglbuhXIt+r5ej2duICSXtQ8ttGOCPspoofzc+CK SIdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cWyQujEvk1ZvvBEgjMYf46UtX0tdPlQNyeagksROeaI=; b=mQy3S0BnkZJCRO47eoj7et7hshUqo0nhagNOPf7vTilbc1fBqu1SHdNfnjxg0Sg6Nz +CE0o+bk6XmpUz4z1tZbrepEBcHRuqGqcskaDhxJneCbU66tWyaEFueqYT80qw4Cbtj0 x/2evIy6M0skRUD2ywdYdiTl6uGTEqDIqq1CwmwC7ttMMq0A4llZqDbMcDXqJ5fMiwNK mykEFLlaMppREI+m3PWEdQhw4sPKIqDt2+fSVfjLWj2+OsQYiGDHAxQpETRfuDDGti0w z0i/nG582TgHQakGOcuxe6qFouyPxDPeYncbl8i/D+FM3tOYP8+AsLe4CtFi87HVVDs+ 9Euw== X-Gm-Message-State: ANoB5pkQ+kPDqwopUjFJTVBI49Cyzy/GYGYvg6SuVBxAVoMzpnBuMbBY wdhIjpHziYzpox5gnk3cssWhMycgnaJZ86U= X-Google-Smtp-Source: AA0mqf65XirmVvA0c0kA2Sw63W0K3JpljPLCsrpQEBXohP+sfrTv4TgVx/eA7KLFInbLI/SmVexiqw== X-Received: by 2002:a17:902:bd03:b0:187:1c7b:207 with SMTP id p3-20020a170902bd0300b001871c7b0207mr15731543pls.38.1670848469266; Mon, 12 Dec 2022 04:34:29 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:28 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 11/13] arm64: dts: qcom: sm6350: Remove reg-names property from LLCC node Date: Mon, 12 Dec 2022 18:03:09 +0530 Message-Id: <20221212123311.146261-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So only change needed is to remove the reg-names property from LLCC node to conform to the binding. The driver is expected to parse the reg field based on index to get the addresses of each LLCC banks. Cc: # 5.16 Fixes: ced2f0d75e13 ("arm64: dts: qcom: sm6350: Add LLCC node") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Sai Prakash Ranjan --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..1f39627cd7c6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,6 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Mon Dec 12 12:33:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 301B2C04FDE for ; Mon, 12 Dec 2022 12:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232345AbiLLMgX (ORCPT ); Mon, 12 Dec 2022 07:36:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232244AbiLLMfd (ORCPT ); Mon, 12 Dec 2022 07:35:33 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DBF11274F for ; Mon, 12 Dec 2022 04:34:44 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id q17-20020a17090aa01100b002194cba32e9so15551521pjp.1 for ; Mon, 12 Dec 2022 04:34:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wh6m1JcK6STNBXORkx35NkjOywagUzfiNFikKvcldrw=; b=tZ4QCiCi57c8AXrLrbQadVtl/gJetV5jfdp19zgCctxTIPtWX+IZUFLwMcQMtsf0QU yHsylcO5d6cpIAJO2tUg46uZ/SHRnlBIv9vaOSi1+V8nom1DY0+tlVE3FXvyMmtrpKPU lW7rUro7Q6LJxSMxP3XcYaCH0udFRMSMMRhHgIHQYQFU+9ILBDeSOXHtvKrmBnJjvr0r pQ95hoXf5efGxKJhnis5gINcO7es8xuDQqWTXrCZahMKCzNAS3+zBqSvb957dKlcNqNN VA57RPLouYDk1ntUhmunc9aRDxNuvNb+zL0KNqW6qaHRvKWqgTTvj99IeG1AaZcWjlRN ikRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wh6m1JcK6STNBXORkx35NkjOywagUzfiNFikKvcldrw=; b=1hEkqm/Z7j1moutNc0ZUMmqoh0Vwivdgs4J9GXQf3lnqB87AfD1o3z4c+igrpPfzEw MxwfRz/KOR35GR5SVZLEkyz3ktppw0JrBCF9NO+aTnnMXIskKcIEuB++GBfYJE78pj20 dMQwdpiVYbhkqu2SmcUkdBSp8Fs3xWsPR0Ay2EfrNP7Zy4d0JTUClzt2lm0403Z1+uZI MG2As+dB8MqfqWPM4LnW2fpURMIh5NYO9OjNkgA2uUE/VnO8/jJJcBvhcEO/K8XklwF+ mQdsc+usdmePJVlwc9oZAAG1hGJCee4ds5Ria3eUuovfvfshEAQyaZJWd1Y3GiwhiBHT 2URw== X-Gm-Message-State: ANoB5pk5n2Ibj1BSzH6Hhn8tcngPXQzywXJ6bzaSRmjDk/pLczZXVRIg y/+ShEmj2fPyDUTmFfxbCD6G X-Google-Smtp-Source: AA0mqf6kBOsY3V8ewIKyXxh5nzjdVMnE2nR/Bd1+ZMaYWNa/fM4K3fxQ4LlQtilUMGM35zYuQq6lXg== X-Received: by 2002:a17:902:f2ca:b0:189:ac49:fe9d with SMTP id h10-20020a170902f2ca00b00189ac49fe9dmr15186029plc.19.1670848475217; Mon, 12 Dec 2022 04:34:35 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v2 12/13] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Mon, 12 Dec 2022 18:03:10 +0530 Message-Id: <20221212123311.146261-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, we no longer need to rely on reg-names property and get the base addresses using index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those needs to be defined in devicetree for index from 1..N-1. Cc: # 4.20 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..5be93577fc03 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..a29f22dad7fa 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, i, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { ret = PTR_ERR(drv_data->bcast_regmap); goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From patchwork Mon Dec 12 12:33:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 633278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CF50C4332F for ; Mon, 12 Dec 2022 12:36:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232361AbiLLMg2 (ORCPT ); Mon, 12 Dec 2022 07:36:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232259AbiLLMfm (ORCPT ); Mon, 12 Dec 2022 07:35:42 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 800CE12759 for ; Mon, 12 Dec 2022 04:34:48 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id b13-20020a17090a5a0d00b0021906102d05so12032606pjd.5 for ; Mon, 12 Dec 2022 04:34:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jie7lgdvEnIQyGE6zlhbT0B1hTmWl4xcVmRV6TIX7Ks=; b=eaCgJOSU0Eenl1pCm9rc7ZdHXRGdaf8ehej2UyKExNX14OP9y9q7t6bzQA9F6MFh8Y H5ULrBo5EayBNpm/RX2smnE8G548NKB+F/i7bd6N6gqpr21/w2Qd0P8N/nVI+2EMt6rF AAlK2EEuSaJIAuKutAfLU9L72haqT/M1tnZ2bOVub6MnlWS+qDQNFOZE/CyiureudYl6 9FcYjh41G5dtfMEYlWm98BRgL2o/VV5IpCu6tGc4VFD/0yOf4LyBy4Ybbompy1W5lgXb CGQ3l29KZo7FTLPLFOP7UcSTCXflCzB4YR7lqMTRmCQVsTMalLhAO8tzybd3nJVE4QwW yeWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jie7lgdvEnIQyGE6zlhbT0B1hTmWl4xcVmRV6TIX7Ks=; b=Oxo6NpgiQzUjRVzmRnEAjR/U+doF1z7k7nsl6aCkPFEpYlzZIfbfFA1UhYHbm46mk1 bmefZj4mX1g8nmKAlhxON4jg+ZcFmI3f1TMvgQu5sQPUU78eoCaNUY8LQg/pIQVinSth /3FG4plL8H0nGQXeRowFv6m1U04QdLtDSoLspEDKWztK7g7LvBpr9aYJkfdqMzPPhKH4 gVOGKdHth/Lg4HcE0ObFm1LdM7Nr7IOjB7Xh9SBHwslyMxPyGUNUVUZYl9o1tRTGa4Uj OpqQZCwKf8ydyGJfZFRPqoS+yrNNYImRZwetl+x4NKE8gAZOmutroiCAsf74u3P/JbMX w5Iw== X-Gm-Message-State: ANoB5plsLlxyv8TaPsEuR1cWsaAC2vak9yr2MVJ1EKGEcbJ2KxbfLEih eF5Zr5Jp9eEUJ2iDYkYdjAKJ X-Google-Smtp-Source: AA0mqf5LpwGxW+PLMAvFM3kf27MXz56pW7cTMD9M0+puHlZxDzlk3HeUecpzAWk/fLvCVmfLeMnunA== X-Received: by 2002:a17:902:9891:b0:189:2688:c97f with SMTP id s17-20020a170902989100b001892688c97fmr14982727plp.50.1670848481155; Mon, 12 Dec 2022 04:34:41 -0800 (PST) Received: from localhost.localdomain ([220.158.159.33]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b00189c93ce5easm6252557plx.166.2022.12.12.04.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 04:34:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, Manivannan Sadhasivam Subject: [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling Date: Mon, 12 Dec 2022 18:03:11 +0530 Message-Id: <20221212123311.146261-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosed based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 5be93577fc03..f7afb5375293 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->pvt_info; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; edev_ctl->pvt_info = llcc_driv_data; + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state = EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state = EDAC_OPSTATE_POLL; + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + } + rc = edac_device_add_device(edev_ctl); if (rc) goto out_mem; platform_set_drvdata(pdev, edev_ctl); - /* Request for ecc irq */ - ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } return rc; diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a29f22dad7fa..e044e6756415 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: