From patchwork Mon Dec 19 15:46:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 635362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F55EC4167B for ; Mon, 19 Dec 2022 15:39:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbiLSPjN (ORCPT ); Mon, 19 Dec 2022 10:39:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232268AbiLSPjM (ORCPT ); Mon, 19 Dec 2022 10:39:12 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A35AA11178 for ; Mon, 19 Dec 2022 07:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464351; x=1703000351; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+upwQwze58+VXG+39ATg90l00WT7gm0SqCvuLlxgE3E=; b=fugq2C28dNIt3SjEuyhkICIyDYAEie6iDVdPdtrgG8Fxct7fCUG2T83a EDPEzZrQzsAse1dqY1XdEnsibfd599foMqAEYS+hdg3pBcQ2mO9gyOhXn oTCZUBlUuYflJLGDkw+1CgSYy+VjZhMapMsqf9M4uMdpa8Zz/PQdUeSDe bPSNYPgc+4nd9XtW8TRZyKgiv4wBY7LwkxEcwhkvDqlHbUGh7Mmcm/ExT uNybNwgcA+UCJj+Xi6rTcERVZ2oEEJ60M53TcWNAtGDm9btJhxqPvJrFn QoJ5HPLWxrr2CWtM3air16vRoL21KZuO0jhQqt4aoygbkElFxq7dHeWhH A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051207" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051207" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960313" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960313" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:09 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 1/6] thermal/intel: Introduce Intel TCC library Date: Mon, 19 Dec 2022 23:46:15 +0800 Message-Id: <20221219154620.3630-2-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There are several different drivers that accesses the Intel TCC (thermal control circuitry) MSRs, and each of them has its own implementation for the same functionalities, e.g. getting the current temperature, getting the tj_max, and getting/setting the tj_max offset. Introduce a library to unify the code for Intel CPU TCC MSR access. At the same time, ensure the temperature is got based on the updated tjmax value because tjmax can be changed at runtime for cases like the Intel SST-PP (Intel Speed Select Technology - Performance Profile) level change. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 4 + drivers/thermal/intel/Makefile | 1 + drivers/thermal/intel/intel_tcc.c | 139 ++++++++++++++++++++++++++++++ include/linux/intel_tcc.h | 18 ++++ 4 files changed, 162 insertions(+) create mode 100644 drivers/thermal/intel/intel_tcc.c create mode 100644 include/linux/intel_tcc.h diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index f0c845679250..6b938c040d6e 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -12,6 +12,10 @@ config X86_THERMAL_VECTOR def_bool y depends on X86 && CPU_SUP_INTEL && X86_LOCAL_APIC +config INTEL_TCC + bool + depends on X86 + config X86_PKG_TEMP_THERMAL tristate "X86 package temperature thermal driver" depends on X86_THERMAL_VECTOR diff --git a/drivers/thermal/intel/Makefile b/drivers/thermal/intel/Makefile index 9a8d8054f316..5d8833c82ab6 100644 --- a/drivers/thermal/intel/Makefile +++ b/drivers/thermal/intel/Makefile @@ -2,6 +2,7 @@ # # Makefile for various Intel thermal drivers. +obj-$(CONFIG_INTEL_TCC) += intel_tcc.o obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o obj-$(CONFIG_INTEL_SOC_DTS_IOSF_CORE) += intel_soc_dts_iosf.o diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c new file mode 100644 index 000000000000..2e5c741c41ca --- /dev/null +++ b/drivers/thermal/intel/intel_tcc.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access + * Copyright (c) 2022, Intel Corporation. + */ + +#include +#include +#include + +/** + * intel_tcc_get_tjmax() - returns the default TCC activation Temperature + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * + * Get the TjMax value, which is the default thermal throttling or TCC + * activation temperature in degrees C. + * + * Return: Tjmax value in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_tjmax(int cpu) +{ + u32 low, high; + int val, err; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + val = (low >> 16) & 0xff; + + return val ? val : -ENODATA; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, INTEL_TCC); + +/** + * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * + * Get the TCC offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degrees C. + * + * Return: Tcc offset value in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_offset(int cpu) +{ + u32 low, high; + int err; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + return (low >> 24) & 0x3f; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC); + +/** + * intel_tcc_set_offset() - set the TCC offset value to Tjmax + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * @offset: TCC offset value in degree C + * + * Set the TCC Offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degree C. + * + * Return: On success returns 0, negative error code otherwise. + */ + +int intel_tcc_set_offset(int cpu, int offset) +{ + u32 low, high; + int err; + + if (offset < 0 || offset > 0x3f) + return -EINVAL; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + /* MSR Locked */ + if (low & BIT(31)) + return -EPERM; + + low &= ~(0x3f << 24); + low |= offset << 24; + + if (cpu < 0) + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + else + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC); + +/** + * intel_tcc_get_temp() - returns the current temperature + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor. + * + * Get the current temperature returned by the CPU core/package level + * thermal sensor, in degrees C. + * + * Return: Temperature in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_temp(int cpu, bool pkg) +{ + u32 low, high; + u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; + int tjmax, temp, err; + + tjmax = intel_tcc_get_tjmax(cpu); + if (tjmax < 0) + return tjmax; + + if (cpu < 0) + err = rdmsr_safe(msr, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, msr, &low, &high); + if (err) + return err; + + /* Temperature is beyond the valid thermal sensor range */ + if (!(low & BIT(31))) + return -ENODATA; + + temp = tjmax - ((low >> 16) & 0x7f); + + /* Do not allow negative CPU temperature */ + return temp >= 0 ? temp : -ENODATA; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_temp, INTEL_TCC); diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h new file mode 100644 index 000000000000..f422612c28d6 --- /dev/null +++ b/include/linux/intel_tcc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * header for Intel TCC (thermal control circuitry) library + * + * Copyright (C) 2022 Intel Corporation. + */ + +#ifndef __INTEL_TCC_H__ +#define __INTEL_TCC_H__ + +#include + +int intel_tcc_get_tjmax(int cpu); +int intel_tcc_get_offset(int cpu); +int intel_tcc_set_offset(int cpu, int offset); +int intel_tcc_get_temp(int cpu, bool pkg); + +#endif /* __INTEL_TCC_H__ */ From patchwork Mon Dec 19 15:46:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 635361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CC60C4167B for ; Mon, 19 Dec 2022 15:39:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232268AbiLSPjR (ORCPT ); Mon, 19 Dec 2022 10:39:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232292AbiLSPjQ (ORCPT ); Mon, 19 Dec 2022 10:39:16 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37C241180B for ; Mon, 19 Dec 2022 07:39:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464355; x=1703000355; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=IKGVvi7Ow+KJIOJlp/40S7/gq5GYZf30XRqJNQhnNUw=; b=frwWwvtUdJLwUS53Si2+JxIThC6MXiMQOBgGcqJ4RmLwFnE4tfmJgGUG Gayw0B7qjd84Cp9PEf90pD59MIt7FxeA0qlXRAg1Iu/Ao5Zq8tSPxsN1S 7mILWRHoU/tf6usJQkRiNVWVHcQIoVn2GTrdtK+w/5nyHogF8PBFkFuUl NJaT+7OcAJ4Yy8g/6KmRmT3E1m2TbZXTnAuPHO9n+D3ZlOMLiwfRwYoWX EeIwqT7vHlFBux1VgK3x7bTPZ8+9CvsBaRKh9VWZ1Vos+bMHYampSkAEd q/jeSbH8tBEFUPN6TzGzNybzHFdd0M1cWrbaq4urLQGjYlgnfK4nZjUZV g==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051236" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051236" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960332" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960332" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:13 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 3/6] thermal/intel/intel_soc_dts_iosf: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:17 +0800 Message-Id: <20221219154620.3630-4-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/intel_soc_dts_iosf.c | 33 ++++------------------ 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index 6b938c040d6e..329c0ee934c4 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -32,6 +32,7 @@ config INTEL_SOC_DTS_IOSF_CORE tristate depends on X86 && PCI select IOSF_MBI + select INTEL_TCC help This is becoming a common feature for Intel SoCs to expose the additional digital temperature sensors (DTSs) using side band interface (IOSF). This diff --git a/drivers/thermal/intel/intel_soc_dts_iosf.c b/drivers/thermal/intel/intel_soc_dts_iosf.c index 342b0bb5a56d..2138693d8afd 100644 --- a/drivers/thermal/intel/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel/intel_soc_dts_iosf.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -45,32 +46,6 @@ /* DTS0 and DTS 1 */ #define SOC_MAX_DTS_SENSORS 2 -static int get_tj_max(u32 *tj_max) -{ - u32 eax, edx; - u32 val; - int err; - - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - goto err_ret; - else { - val = (eax >> 16) & 0xff; - if (val) - *tj_max = val * 1000; - else { - err = -EINVAL; - goto err_ret; - } - } - - return 0; -err_ret: - *tj_max = 0; - - return err; -} - static int sys_get_trip_temp(struct thermal_zone_device *tzd, int trip, int *temp) { @@ -415,8 +390,9 @@ struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( if (!trip_count || read_only_trip_count > trip_count) return ERR_PTR(-EINVAL); - if (get_tj_max(&tj_max)) - return ERR_PTR(-EINVAL); + tj_max = intel_tcc_get_tjmax(-1); + if (tj_max < 0) + return ERR_PTR(tj_max); sensors = kzalloc(sizeof(*sensors), GFP_KERNEL); if (!sensors) @@ -475,4 +451,5 @@ void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors) } EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_exit); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 19 15:46:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 635360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F882C10F1B for ; Mon, 19 Dec 2022 15:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231370AbiLSPjX (ORCPT ); Mon, 19 Dec 2022 10:39:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232299AbiLSPjU (ORCPT ); Mon, 19 Dec 2022 10:39:20 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E70911815 for ; Mon, 19 Dec 2022 07:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464359; x=1703000359; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=sHoWlnZF2lxigqX1MPRD5MgEFvKhfKxiXtw5H2qwB8k=; b=gFGOp3b5lckexdj3CU0p13/KpoqlQa2VX9yF4KHpnxPv7niSUpGKb/+Z /CCM1Z8wq1ud4tw9qe7zmWwBv6fvFdICzi7VCmxFjerB9s3fApGLaz40j ZgFUgwoO4jLzSx3vBk9o9YOqMSPDSG0/T+zzbsa+GtCffmhk8VIxbxr/u zAlYV//95R7g1Kk5P1nRDzbpALloDmXGYgfhXlwNZ9PaXy25iWe9XH3MC t3j50pvIKu1dUV025FREeTTBwrPcAj0l3v9lrmvyGBM403Ha3VlC3AXl3 v6T9bIoZY2AlrrW0SZqVeQPII3mIrY1PUZrKL5bDx1gNQRESgEYR7W7zk w==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051265" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051265" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960348" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960348" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:17 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 5/6] thermal/x86_pkg_temp_thermal: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:19 +0800 Message-Id: <20221219154620.3630-6-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/x86_pkg_temp_thermal.c | 44 ++++++-------------- 2 files changed, 14 insertions(+), 31 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index dafdb3dd3fc7..fd41c810629b 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -21,6 +21,7 @@ config X86_PKG_TEMP_THERMAL depends on X86_THERMAL_VECTOR select THERMAL_GOV_USER_SPACE select THERMAL_WRITABLE_TRIPS + select INTEL_TCC default m help Enable this to register CPU digital sensor for package temperature as diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index a0e234fce71a..416ff23da4de 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -104,38 +105,18 @@ static struct zone_device *pkg_temp_thermal_get_dev(unsigned int cpu) return NULL; } -/* -* tj-max is interesting because threshold is set relative to this -* temperature. -*/ -static int get_tj_max(int cpu, u32 *tj_max) -{ - u32 eax, edx, val; - int err; - - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - return err; - - val = (eax >> 16) & 0xff; - *tj_max = val * 1000; - - return val ? 0 : -EINVAL; -} - static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) { struct zone_device *zonedev = tzd->devdata; - u32 eax, edx; + int val; - rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_STATUS, - &eax, &edx); - if (eax & 0x80000000) { - *temp = zonedev->tj_max - ((eax >> 16) & 0x7f) * 1000; - pr_debug("sys_get_curr_temp %d\n", *temp); - return 0; - } - return -EINVAL; + val = intel_tcc_get_temp(zonedev->cpu, true); + if (val < 0) + return val; + + *temp = val * 1000; + pr_debug("sys_get_curr_temp %d\n", *temp); + return 0; } static int sys_get_trip_temp(struct thermal_zone_device *tzd, @@ -345,9 +326,9 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) thres_count = clamp_val(thres_count, 0, MAX_NUMBER_OF_TRIPS); - err = get_tj_max(cpu, &tj_max); - if (err) - return err; + tj_max = intel_tcc_get_tjmax(cpu); + if (tj_max < 0) + return tj_max; zonedev = kzalloc(sizeof(*zonedev), GFP_KERNEL); if (!zonedev) @@ -536,6 +517,7 @@ static void __exit pkg_temp_thermal_exit(void) } module_exit(pkg_temp_thermal_exit) +MODULE_IMPORT_NS(INTEL_TCC); MODULE_DESCRIPTION("X86 PKG TEMP Thermal Driver"); MODULE_AUTHOR("Srinivas Pandruvada "); MODULE_LICENSE("GPL v2");