From patchwork Tue Apr 2 13:37:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 161629 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1758821jan; Tue, 2 Apr 2019 06:38:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqzMn5rOBADMZPBE5bgKgp3/LnXG9M6ENHfaoGoBKi8ig+gS5H2KwHXpGwOnd1W0uCicEYV6 X-Received: by 2002:a17:902:2ec1:: with SMTP id r59mr69582105plb.171.1554212302695; Tue, 02 Apr 2019 06:38:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554212302; cv=none; d=google.com; s=arc-20160816; b=KzMnqgKJojWlUa7SZVgBCKh9T4Hc/+h772lAqyHU8X9+7MBSSMi/XV9EYQ7uTe4n1S Crgyk/K90JRXMaBi6tjhAauGe0TcTtJjTcrsXR1MDG8OsCf+foSApk6O35e0gN4dIepG 1tJhwUKAVo30qgnMvB6goEhwzlQFpWqsjySvoNy6+oyycPnr+HU3TsQ/SnooNVzTZS3r BszvUC0yBqsX/pA2ySEgDqh3pUPmv5pDRp6j1s05fDPL3KnNFFnqEzi49PRZUZiiquJC q+SJD1aPSfLZSZcpIq1twlLLTfP/OqP3b3U/xeSUNZycvZ2JtGfEYLR7ruVx5sRbRZ4j yshQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0RueluNUmnctCVcpjCePWJlghhTJkq8vCQtlL6gR87o=; b=YZkU69XxxI81UDgjUQgZICHrUZb6u2GqMVREfAq1rykTXKWXvSEz9HrCnctPpwJuT+ cx2jxm0UddXxc4uXIZUMtMTEeDIEswbqbVmfJMYQybv1AnpPUZ3QlAPHY/2WrFPQ+G4Y j0obiTAD4PpeMMixVq5DwsJCScCj6C+qBiwWWS0Z5dcYrYMhDethHQHpEM6JrhvGP4MM IMarRDh7+0cacz9kYwyGvqd6DN72utT9udGbIJ04aK7jP2/lwwj71HIHtKn+C8jghw8Y NtEXPAmKYH7tQJxiDSkOOra88/XWZ1HFifmpIR6+gEjTmdDk3NqgDqsB0/iM9sPOODvd f8yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="M/CBaSBx"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n1si11192504plp.26.2019.04.02.06.38.22; Tue, 02 Apr 2019 06:38:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="M/CBaSBx"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730087AbfDBNiB (ORCPT + 31 others); Tue, 2 Apr 2019 09:38:01 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48530 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729532AbfDBNiA (ORCPT ); Tue, 2 Apr 2019 09:38:00 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x32Dbx7A091852; Tue, 2 Apr 2019 08:37:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554212279; bh=0RueluNUmnctCVcpjCePWJlghhTJkq8vCQtlL6gR87o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=M/CBaSBxwmyPDrmwyp3bzpyQvVPMy905bFSeTYTBVEQtwmV5NafGaJnaz9jH/3g1k IE7LXJXPejs6OcgWz34IDstU1TYjktEIVUWVKKLWFY/GT05d2MqEwT32xvi5CyS0qh WKEqCH/JTDQecH8/tldGZY9OULTZg1mYaXGYD584= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x32Dbw9i018384 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 Apr 2019 08:37:58 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 2 Apr 2019 08:37:58 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 2 Apr 2019 08:37:58 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x32DbsTx051551; Tue, 2 Apr 2019 08:37:57 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [RFC PATCH 1/4] ARM: dts: dra7: Keep usb_otg_ss3 and usb_otg_ss4 disabled Date: Tue, 2 Apr 2019 16:37:49 +0300 Message-ID: <20190402133752.6912-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190402133752.6912-1-rogerq@ti.com> References: <20190402133752.6912-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These 2 modules are not present on all families (e.g. AM57). Keep them disabled. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-l4.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki Signed-off-by: Roger Quadros diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 414f1cd68733..40e7281c12f7 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -4120,6 +4120,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x20000>; + status = "disabled"; omap_dwc3_3: omap_dwc3_3@0 { compatible = "ti,dwc3"; @@ -4169,6 +4170,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x140000 0x20000>; + status = "disabled"; }; target-module@170000 { /* 0x48970000, ap 21 0a.0 */ From patchwork Tue Apr 2 13:37:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 161626 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1758502jan; Tue, 2 Apr 2019 06:38:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLjRB2bmyZXX+1TMCwR9uP1KzOBeYZ2WxuCmlpzK+Ukac91k2NOmQvy+XJkSLjmEZdsMci X-Received: by 2002:a65:47c6:: with SMTP id f6mr49585848pgs.173.1554212287325; Tue, 02 Apr 2019 06:38:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554212287; cv=none; d=google.com; s=arc-20160816; b=Dp2Vvz/qMmyfOBbEA64ug75siU7RqjmM98tydzYD9gNdixSXdTWYDXeCszWpV/yJf4 l+vYpXMqK0IqKsfaMBDwEgVU9vLX+5OHWAFgCgfUPwpNWrEf9fcHK/K7CkjQX76qiQ/q OEwLDRLwf40ByRc18gmeWOVPXdGGjNfv8dl13RjzFKSZIp/FdjluHUGOaiTXSjn5+F8Z +Mjm4DkjOJjVdJEch5b64AEDkkE5E4wOiW5G0XtsToGM6mjzfTU0zrPoagCfREokJAyV Jd2hfx1aCWoQDiiRiBZQ/6EW7Mfb+abBiEJnOMx+qsDlFfA2udOw7MHiDtNr9xBbgsMm hYnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=aAk0r9TUo1AqkBkCxh24GlYC3DNt9KEpMWg5nv+RvLQ=; b=JSn1fU+QPl8gMVeekRpVTBkuWEt87PcG6LDjiyri+W6MR5hYh5gobpbO5dckVz5rPz plzSdYuP5dIpwyVt2vwT17g7iYzn+tsnwCoNHuYzt5BGU39Fv8xqBoqwFiFJ1QHIL9jy L//kRjMVhr8w8J5cZrqHTu+x7Nu7Wu4Py40sdRvFI3HWUDjSi0aUq538KVuUn9jd9T0T +ucRn3RQ9BJDbFkkGXcHWIGFnopfC/+mm8vY/TZqAm1k42+Jaoiq8NBBKtTctnpwea5H AS0SiCVrWbsOf2wbdZwtj/2zC+sA/TCSkBgWLWOG/zO5wepNTAmZLX9yzBcFGzMZwUZp k9LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JJP1JIR+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b22si4110631pls.285.2019.04.02.06.38.07; Tue, 02 Apr 2019 06:38:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JJP1JIR+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730695AbfDBNiG (ORCPT + 31 others); Tue, 2 Apr 2019 09:38:06 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:60154 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728105AbfDBNiE (ORCPT ); Tue, 2 Apr 2019 09:38:04 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x32Dc2lM023114; Tue, 2 Apr 2019 08:38:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554212282; bh=aAk0r9TUo1AqkBkCxh24GlYC3DNt9KEpMWg5nv+RvLQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JJP1JIR+ChPZJCf05+ZpB9w0KhVeOwG1X8wXR6XiLCr0/FVkwyO3JGb1NdU8p/bkJ 9pMkHSi3zqtdpe5RVcXWgzwGoASStdpDPSpZMTvsXE8xigmbAjnroo8fOQldmYnz4c W+h6gbBQSHFycF2l9b3Fjn9x7HI3vf51zZ42teNU= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x32Dc2a7018468 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 Apr 2019 08:38:02 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 2 Apr 2019 08:38:00 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 2 Apr 2019 08:38:00 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x32DbsU0051551; Tue, 2 Apr 2019 08:37:58 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [RFC PATCH 2/4] bus: ti-sysc: Add generic enable/disable functions Date: Tue, 2 Apr 2019 16:37:50 +0300 Message-ID: <20190402133752.6912-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190402133752.6912-1-rogerq@ti.com> References: <20190402133752.6912-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For non legacy cases, add generic sysc_enable_module() and sysc_disable_module() functions. Signed-off-by: Roger Quadros --- drivers/bus/ti-sysc.c | 114 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 5c0dd80021cc..1e63b6265764 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -793,6 +793,112 @@ static void sysc_show_registers(struct sysc *ddata) buf); } +#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) + +static int sysc_enable_module(struct device *dev) +{ + struct sysc *ddata; + const struct sysc_regbits *regbits; + u32 reg, idlemodes, best_mode; + + ddata = dev_get_drvdata(dev); + if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) + return 0; + + regbits = ddata->cap->regbits; + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + + /* Set SIDLE mode */ + idlemodes = ddata->cfg.sidlemodes; + if (!idlemodes || regbits->sidle_shift < 0) + goto set_midle; + + best_mode = fls(ddata->cfg.sidlemodes) - 1; + if (best_mode > SYSC_IDLE_MASK) { + dev_err(dev, "%s: invalid sidlemode\n", __func__); + return -EINVAL; + } + + reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); + reg |= best_mode << regbits->sidle_shift; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + +set_midle: + /* Set MIDLE mode */ + idlemodes = ddata->cfg.midlemodes; + if (!idlemodes || regbits->midle_shift < 0) + return 0; + + best_mode = fls(ddata->cfg.midlemodes) - 1; + if (best_mode > SYSC_IDLE_MASK) { + dev_err(dev, "%s: invalid midlemode\n", __func__); + return -EINVAL; + } + + reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); + reg |= best_mode << regbits->midle_shift; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + + return 0; +} + +static int sysc_disable_module(struct device *dev) +{ + struct sysc *ddata; + const struct sysc_regbits *regbits; + u32 reg, idlemodes, best_mode; + + ddata = dev_get_drvdata(dev); + if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) + return 0; + + regbits = ddata->cap->regbits; + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + + /* Set MIDLE mode */ + idlemodes = ddata->cfg.midlemodes; + if (!idlemodes || regbits->midle_shift < 0) + goto set_sidle; + + if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) { + best_mode = SYSC_IDLE_SMART_WKUP; + } else if (idlemodes & BIT(SYSC_IDLE_SMART)) { + best_mode = SYSC_IDLE_SMART; + } else if (idlemodes & SYSC_IDLE_FORCE) { + best_mode = SYSC_IDLE_FORCE; + } else { + dev_err(dev, "%s: invalid midlemode\n", __func__); + return -EINVAL; + } + + reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); + reg |= best_mode << regbits->midle_shift; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + +set_sidle: + /* Set SIDLE mode */ + idlemodes = ddata->cfg.sidlemodes; + if (!idlemodes || regbits->sidle_shift < 0) + return 0; + + if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) { + best_mode = SYSC_IDLE_SMART_WKUP; + } else if (idlemodes & BIT(SYSC_IDLE_SMART)) { + best_mode = SYSC_IDLE_SMART; + } else if (idlemodes & SYSC_IDLE_FORCE) { + best_mode = SYSC_IDLE_FORCE; + } else { + dev_err(dev, "%s: invalid sidlemode\n", __func__); + return -EINVAL; + } + + reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); + reg |= best_mode << regbits->sidle_shift; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + + return 0; +} + static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, struct sysc *ddata) { @@ -849,6 +955,10 @@ static int __maybe_unused sysc_runtime_suspend(struct device *dev) error = sysc_runtime_suspend_legacy(dev, ddata); if (error) return error; + } else { + error = sysc_disable_module(dev); + if (error) + return error; } sysc_disable_main_clocks(ddata); @@ -885,6 +995,10 @@ static int __maybe_unused sysc_runtime_resume(struct device *dev) error = sysc_runtime_resume_legacy(dev, ddata); if (error) goto err_main_clocks; + } else { + error = sysc_enable_module(dev); + if (error) + goto err_main_clocks; } ddata->enabled = true; From patchwork Tue Apr 2 13:37:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 161628 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1758683jan; Tue, 2 Apr 2019 06:38:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqyzy+M3XCFz6fUvT4g/HCdWOstt7t1xpKDoNoMsGDFpH76mSyhM/InXPjy+nzqG9RMZocpw X-Received: by 2002:a63:3185:: with SMTP id x127mr66542005pgx.299.1554212295740; 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[209.132.180.67]) by mx.google.com with ESMTP id f11si11113345pgf.406.2019.04.02.06.38.15; Tue, 02 Apr 2019 06:38:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=g7aG8zlN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730964AbfDBNiO (ORCPT + 31 others); Tue, 2 Apr 2019 09:38:14 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:48548 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728817AbfDBNiF (ORCPT ); Tue, 2 Apr 2019 09:38:05 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x32Dc35u091865; Tue, 2 Apr 2019 08:38:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554212283; bh=Za2kgWFbKuq5etVSa0oON5gBamI1FQB22QDbBAHljnY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g7aG8zlNpGMQ0eHX0k6JlGNAvWKe3fYCHJqiwqbBUvsr0raJM6RnIv1ZOk5X4eKrS pLH+pwkmlvbp9W+l88ZX5zIwWpWyMOkWfyxSQCyRZP51mBsGWXejOjeXlXBXnyagRZ CZt7C2lOaqAwMih6Uxb+DMdaOY5cwlu+3t4LJOZQ= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x32Dc314072470 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 Apr 2019 08:38:03 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 2 Apr 2019 08:38:01 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 2 Apr 2019 08:38:01 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x32DbsU1051551; Tue, 2 Apr 2019 08:38:00 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [RFC PATCH 3/4] bus: ti-sysc: Add support for PRU-ICSS type Date: Tue, 2 Apr 2019 16:37:51 +0300 Message-ID: <20190402133752.6912-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190402133752.6912-1-rogerq@ti.com> References: <20190402133752.6912-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PRU-ICSS moduels has a SYSCONFIG register that is similar to omap4-simple but with 2 speacial register bits. Let's add a new type for that so we can deal with any PRU-ICSS specific details if required. Signed-off-by: Roger Quadros --- .../devicetree/bindings/bus/ti-sysc.txt | 1 + drivers/bus/ti-sysc.c | 21 +++++++++++++++++++ include/linux/platform_data/ti-sysc.h | 7 ++++++- 3 files changed, 28 insertions(+), 1 deletion(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt index f200f45572ae..f9716c841ecd 100644 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt @@ -38,6 +38,7 @@ Required standard properties: "ti,sysc-dra7-mcasp" "ti,sysc-usb-host-fs" "ti,sysc-dra7-mcan" + "ti,sysc-pruss" - reg shall have register areas implemented for the interconnect target module in question such as revision, sysc and syss diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 1e63b6265764..e4ab4d422ea5 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1993,6 +1993,26 @@ static const struct sysc_capabilities sysc_dra7_mcan = { .regbits = &sysc_regbits_dra7_mcan, }; +/* + * PRU-ICSS, similar to omap4-simple but has special bits + */ +static const struct sysc_regbits sysc_regbits_pruss = { + .dmadisable_shift = -ENODEV, + .midle_shift = 2, + .sidle_shift = 0, + .clkact_shift = -ENODEV, + .enwkup_shift = -ENODEV, + .srst_shift = -ENODEV, + .emufree_shift = -ENODEV, + .autoidle_shift = -ENODEV, + .standby_init_shift = 4, + .sub_mwait_shift = 5, +}; + +static const struct sysc_capabilities sysc_pruss = { + .type = TI_SYSC_PRUSS, + .regbits = &sysc_regbits_pruss, +}; static int sysc_init_pdata(struct sysc *ddata) { struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); @@ -2186,6 +2206,7 @@ static const struct of_device_id sysc_match[] = { { .compatible = "ti,sysc-usb-host-fs", .data = &sysc_omap4_usb_host_fs, }, { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, + { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, { }, }; MODULE_DEVICE_TABLE(of, sysc_match); diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 9256c0305968..bb95ae7da56c 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -15,6 +15,7 @@ enum ti_sysc_module_type { TI_SYSC_OMAP4_MCASP, TI_SYSC_OMAP4_USB_HOST_FS, TI_SYSC_DRA7_MCAN, + TI_SYSC_PRUSS, }; struct ti_sysc_cookie { @@ -30,7 +31,9 @@ struct ti_sysc_cookie { * @srst_shift: Offset of the softreset bit * @autoidle_shift: Offset of the autoidle bit * @dmadisable_shift: Offset of the dmadisable bit - * @emufree_shift; Offset of the emufree bit + * @emufree_shift: Offset of the emufree bit + * @standby_init_shift: Offset to standby_init bit + * @sub_mwait_shift: Offset to sub_mwait bit * * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a * feature is not available. @@ -44,6 +47,8 @@ struct sysc_regbits { s8 autoidle_shift; s8 dmadisable_shift; s8 emufree_shift; + s8 standby_init_shift; + s8 sub_mwait_shift; }; #define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13) From patchwork Tue Apr 2 13:37:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 161627 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1758626jan; Tue, 2 Apr 2019 06:38:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZOjzzj9Lh+Ks0ztOvkpbUbguaT1sQVajr7l8SOkVGHYcWaJW2r4ceTV4H8eQvrtO+Pgzu X-Received: by 2002:a63:1064:: with SMTP id 36mr39266495pgq.155.1554212292206; Tue, 02 Apr 2019 06:38:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554212292; cv=none; d=google.com; s=arc-20160816; b=k4DRmpPYwBzfW/Pbi1b9eci34nyi5ArKS2AcENLgGRKDEa8LwcOWe03NQieepzH6zr OULj4oh71JidKEWiEBBw0E+DvV9bBQl+3GpQwHcB4P7RHv/Cllt6YH2TbeIKrzr+Zyvj /aMOo61ceGUqSFizC8QnjctTQdDBuVajKG+Mdy/25WEXr1ouuE/kc3FT3r4o4iie558e fmZnVp7G2CwwNAPoaKTrIR24rB4O4hbt8zwhghm6msfcpq6Su/N4btCqo8Pgpcin6rRg DYqB8x8ByCNmm9enIfhy3IVwTsADwXhVsgUrdzAetAQhgtX3psYgZvC2rCG/kd8G7ivB jV1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0/edQbd/JCK6PPPftxF7RTw4Vc6XeooZElbDVEEf+4M=; b=H6RxOMGGf+tLwhwsQeyt3zZiXzlXoo/b5A3s/8Gh0SN6JxVWd3D0hTJT1viBvE0qOl ZZpd7HpBu/vGk5J1DGF9ZWUhM7FC8/A64UIXn9jMWaRVXCUmVGieGOnqvmWXuPn3hl8q whLG8oz+K/dr5YH3U+42KbhdwpZYXFnILHhJsdEBTXbulMDORiGTly79dfktlzO8s6gt lOF5dnPn0gvqF5P9s7X9na1ms82ZahfXJAtVE/GOtf1E0ghhHWXG9uMVMKIxNIXJWV9M r5DLMfRi309mdpBMxXPZiaxM89Ml6xr/7+iVzTsHczOFbhiKCFjhja1YZndSCCrntqJ4 P2SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CxGlve3a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f11si11113345pgf.406.2019.04.02.06.38.11; Tue, 02 Apr 2019 06:38:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CxGlve3a; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730738AbfDBNiK (ORCPT + 31 others); Tue, 2 Apr 2019 09:38:10 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:43754 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730639AbfDBNiG (ORCPT ); Tue, 2 Apr 2019 09:38:06 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x32Dc48Z103113; Tue, 2 Apr 2019 08:38:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1554212284; bh=0/edQbd/JCK6PPPftxF7RTw4Vc6XeooZElbDVEEf+4M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CxGlve3ad1ndAlgnnA5HpOyNoWvx5q36UgCdY02/5rypkxJduvMbcOVECDP5s2vIq Lr7wZ0uhhfOZAVsgqJMQKl/xGKG6Zt5qEEDmqmpTdlcJtranzstWHmkfVdZ56vORkD vdueFcxlIY518odHKBVFTEr8AxkTYif6I3I9Fn4Y= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x32Dc4uf098759 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 Apr 2019 08:38:04 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 2 Apr 2019 08:38:03 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 2 Apr 2019 08:38:03 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x32DbsU2051551; Tue, 2 Apr 2019 08:38:02 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [RFC PATCH 4/4] bus: ti-sysc: Ensure PRU-ICSS doesn't break suspend/resume Date: Tue, 2 Apr 2019 16:37:52 +0300 Message-ID: <20190402133752.6912-5-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190402133752.6912-1-rogerq@ti.com> References: <20190402133752.6912-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PRU-ICSS subsystem's SYSCONFIG register is similar to omap4-simple but has 2 special bits STANDBY_INIT and SUB_MWAIT. The STANDBY_INIT bit initiates a Standby sequence (when set) and triggers a MStandby request to the SoC's PRCM module. This same bit is also used to enable the OCP master ports (when cleared). Some PRU applications require the OCP master port access to be enabled thus keeping it out of standby. During sustem suspend/resume we must ensure that the PRUSS is in standby else it will break resume. NOTE: 1. This patch only adds the PM callbacks with code to fix the System Suspend/Resume hang issue on AM33xx/AM437x SoCs, but does not implement the full context save and restore required for the PRUSS drivers to work across system suspend/resume when the power domain is switched off (L4PER domain is switched OFF on AM335x/AM437x during system suspend/resume, so PRUSS modules do lose context). 2. The PRUSS driver functionality on AM57xx SoCs is not affected that much because the PER power domain to which the PRUSS IPs belong is not switched OFF during suspend/resume. Based on work by Suman Anna. Cc: Suman Anna Signed-off-by: Roger Quadros --- drivers/bus/ti-sysc.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index e4ab4d422ea5..9c94ce08dd36 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -71,6 +71,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { * @name: name if available * @revision: interconnect target module revision * @needs_resume: runtime resume needed on resume from suspend + * @in_standby: flag used by PRUSS type during suspend/resume */ struct sysc { struct device *dev; @@ -92,6 +93,7 @@ struct sysc { bool enabled; bool needs_resume; bool child_needs_resume; + bool in_standby; struct delayed_work idle_work; }; @@ -1023,6 +1025,21 @@ static int __maybe_unused sysc_noirq_suspend(struct device *dev) if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) return 0; + if (ddata->cap->type == TI_SYSC_PRUSS) { + u32 reg, mask; + const struct sysc_regbits *regbits = ddata->cap->regbits; + + mask = BIT(regbits->standby_init_shift); + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + ddata->in_standby = reg & mask; + + /* initiate MStandby */ + if (!ddata->in_standby) { + reg |= mask; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + } + } + return pm_runtime_force_suspend(dev); } @@ -1035,6 +1052,25 @@ static int __maybe_unused sysc_noirq_resume(struct device *dev) if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) return 0; + if (ddata->cap->type == TI_SYSC_PRUSS && !ddata->in_standby) { + u32 reg; + const struct sysc_regbits *regbits = ddata->cap->regbits; + + /* re-enable OCP master ports/disable MStandby */ + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + reg &= ~BIT(regbits->standby_init_shift); + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + ddata->in_standby = 0; + + /* wait till ready for transactions - delay is arbitrary */ + usleep_range(50, 100); + reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); + if (reg & BIT(regbits->sub_mwait_shift)) { + dev_err(dev, "timeout waiting for SUB_MWAIT_READY\n"); + return -ETIMEDOUT; + } + } + return pm_runtime_force_resume(dev); }