From patchwork Tue Mar 7 04:41:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 660000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C314C6FD1B for ; Tue, 7 Mar 2023 04:42:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230013AbjCGEmN (ORCPT ); Mon, 6 Mar 2023 23:42:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229994AbjCGEmJ (ORCPT ); Mon, 6 Mar 2023 23:42:09 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DCDD4D2A8; Mon, 6 Mar 2023 20:42:07 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3271d9st031755; Tue, 7 Mar 2023 04:42:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=XBPRNAZneLZ4Yl5TEKdkiVHlGZOLkyWr3Kl0exPMpxQ=; b=psliBcIP3mt3ZCUUYnPm+o+KRXhyc7KOkRoVyJL9wNqYoLoe+t+QjRErmQod+OzAAsWU 5Wq7EO+4z1M0GCGU7tNqBxKiUlunKx9HpkDBElUT5hUslwFfOv0X3jhiAwLHoCRxrFTO +eHgeLcZuG6ZQj4fsb5uoIbrszgCvXOR7DPycjwixK+D2417YUCOP5Wf7UWz2MzGzH9T j1dWoUJ5envFoeqKMrZIkmI3ILYrZQogLnbrdJyNbeVZ+t7CTdjOluOvnOS82insXItK OhdcMezzgtxHA7P8GU2d+b2RJGYO7RgO0/bqIQi7mrCk7cqdIRh5atRjt5/EA5NRG5C2 Sg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p5usx0bs6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Mar 2023 04:42:02 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3274g1Ew015474 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Mar 2023 04:42:01 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:41:53 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 01/11] dt-bindings: remoteproc: qcom: Add support for multipd model Date: Tue, 7 Mar 2023 10:11:27 +0530 Message-ID: <1678164097-13247-2-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PjmmK0zM-eXZk0COFo05An71-hy74X8O X-Proofpoint-GUID: PjmmK0zM-eXZk0COFo05An71-hy74X8O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add new binding document for multipd model remoteproc. IPQ5018, IPQ9574 follows multipd model. Signed-off-by: Manikanta Mylavarapu --- .../bindings/remoteproc/qcom,multipd-pil.yaml | 282 ++++++++++++++++++ 1 file changed, 282 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml new file mode 100644 index 000000000000..b788607f5abd --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,multipd-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multipd Secure Peripheral Image Loader + +maintainers: + - Bjorn Andersson + - Mathieu Poirier + +description: + Multipd Peripheral Image Loader loads firmware and boots Q6 pd, WCSS pd + remoteproc's on the Qualcomm IPQ5018, IPQ9574 SoC. + +properties: + compatible: + enum: + - qcom,ipq5018-q6-mpd + - qcom,ipq9574-q6-mpd + + '#address-cells': true + + '#size-cells': true + + 'ranges': true + + reg: + maxItems: 1 + + interrupts-extended: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + clocks: + minItems: 25 + maxItems: 25 + + clock-names: + minItems: 25 + maxItems: 25 + + assigned-clocks: + minItems: 13 + maxItems: 13 + + assigned-clock-rates: + minItems: 13 + maxItems: 13 + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remoteprocessor + items: + - description: Shutdown Q6 + - description: Stop Q6 + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remoteprocessor + items: + - const: shutdown + - const: stop + + memory-region: + items: + - description: Q6 pd reserved region + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + +patternProperties: + "^remoteproc_pd1|remoteproc_pd2|remoteproc_pd3": + type: object + description: + In Multipd model, WCSS pd depends on Q6 pd i.e Q6 pd should be up before + WCSS. It can be achieved by keeping wcss pd node as subnode of Q6 + device node. + + properties: + compatible: + enum: + - "qcom,ipq5018-wcss-ahb-mpd" + - "qcom,ipq9574-wcss-ahb-mpd" + - "qcom,ipq5018-wcss-pcie-mpd" + + interrupts-extended: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn-ack + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remoteprocessor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remoteprocessor + items: + - const: shutdown + - const: stop + - const: spawn + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + - memory-region + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + enum: + - qcom,ipq9574-q6-mpd + then: + properties: + assigned-clocks: + items: + - description: Phandle, clock specifier of GCC_ANOC_WCSS_AXI_M_CLK + - description: Phandle, clock specifier of GCC_WCSS_AHB_S_CLK + - description: Phandle, clock specifier of GCC_WCSS_ECAHB_CLK + - description: Phandle, clock specifier of GCC_WCSS_ACMT_CLK + - description: Phandle, clock specifier of GCC_WCSS_AXI_M_CLK + - description: Phandle, clock specifier of GCC_Q6_AXIM_CLK + - description: Phandle, clock specifier of GCC_Q6_AXIM2_CLK + - description: Phandle, clock specifier of GCC_Q6_AHB_CLK + - description: Phandle, clock specifier of GCC_Q6_AHB_S_CLK + - description: Phandle, clock specifier of GCC_Q6SS_BOOT_CLK + - description: Phandle, clock specifier of GCC_MEM_NOC_Q6_AXI_CLK + - description: Phandle, clock specifier of GCC_WCSS_Q6_TBU_CLK + - description: Phandle, clock specifier of GCC_SYS_NOC_WCSS_AHB_CLK + assigned-clock-rates: + items: + - description: Must be 266666667 HZ + - description: Must be 133333333 HZ + - description: Must be 133333333 HZ + - description: Must be 133333333 HZ + - description: Must be 266666667 HZ + - description: Must be 533000000 HZ + - description: Must be 342857143 HZ + - description: Must be 133333333 HZ + - description: Must be 133333333 HZ + - description: Must be 342857143 HZ + - description: Must be 533000000 HZ + - description: Must be 533000000 HZ + - description: Must be 133333333 HZ + +examples: + - | + #include + #include + #include + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq5018-q6-mpd"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0cd00000 0x4040>; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + q6_wcss_pd1: remoteproc_pd1 { + compatible = "qcom,ipq5018-wcss-ahb-mpd"; + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + + q6_wcss_pd2: remoteproc_pd2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "okay"; + }; + + q6_wcss_pd3: remoteproc_pd3 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "okay"; + }; + }; From patchwork Tue Mar 7 04:41:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 660631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3303C6FA99 for ; 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Signed-off-by: Manikanta Mylavarapu --- .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 9a46dbc6d03f..91f4e0454fe3 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -23,6 +23,7 @@ properties: - const: qcom,ipq6018-apcs-apps-global - items: - enum: + - qcom,ipq5018-apcs-apps-global - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,msm8996-apcs-hmss-global @@ -152,6 +153,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5018-apcs-apps-global - qcom,ipq6018-apcs-apps-global - qcom,ipq8074-apcs-apps-global then: From patchwork Tue Mar 7 04:41:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 659999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E8F5C6FD1B for ; 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Tue, 7 Mar 2023 04:42:24 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:16 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 04/11] dt-bindings: arm: qcom: Add ipq5018-mp03.5-c1 Date: Tue, 7 Mar 2023 10:11:30 +0530 Message-ID: <1678164097-13247-5-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6US3MriLCV3Y67_5Y8a-l_CC9HsizNHk X-Proofpoint-GUID: 6US3MriLCV3Y67_5Y8a-l_CC9HsizNHk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=867 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add entries in the device tree binding for ipq5018-mp03.5-c1. Signed-off-by: Manikanta Mylavarapu --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c49513749ac1..6b8d17afb3f5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -327,6 +327,7 @@ properties: - items: - enum: - qcom,ipq5018-mp03 + - qcom,ipq5018-mp03.5-c1 - const: qcom,ipq5018 - items: From patchwork Tue Mar 7 04:41:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 659998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51481C6FD1B for ; Tue, 7 Mar 2023 04:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230155AbjCGEnI (ORCPT ); Mon, 6 Mar 2023 23:43:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230012AbjCGEnH (ORCPT ); Mon, 6 Mar 2023 23:43:07 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF60A60AA1; Mon, 6 Mar 2023 20:42:37 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3273n3f9020699; Tue, 7 Mar 2023 04:42:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=JQeNRrwYtr2vH6Iky9agQw6s53kZMPOauSsNLT2ysbo=; b=Doo1uyz3hkbGSvZbK0PMAaF6oP1aBKKzrkF+17nnogrjSsAfQn5BbVi82hnQ3BdoZZiy pLp9AaBRf27+QPbXpcnK8NK+i/aHH1arZbBoiHeB5ymtN8cVvUTg4NraS7yzBlAJ5rh4 VoeKPwOD0iTYn59pYJiHNKzePWUuEL41zU6ZLaAkGAsNGJPpXDCnOKu/iYOAu51xJMZj p7aQrmfJVfBbvkX/F5Ea0MTuWLrYmZxUr58V6Fv57ZJLhGB87n0Qvsb9Pg3leJHGypN2 z/vFg2gsOfXTej+CcrRw4K+aKiCVsCPpV9CM74cqDHYG4eV8dYQ/5XN3C8TnAhKCBvG1 LA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p41916wvn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Mar 2023 04:42:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3274gWuZ015267 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Mar 2023 04:42:32 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:24 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 05/11] dt-bindings: clock: qcom: gcc-ipq9574: Add Q6 gcc clock control Date: Tue, 7 Mar 2023 10:11:31 +0530 Message-ID: <1678164097-13247-6-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MJZN75W-QjS2EK8URj73BECtwnKpC8xu X-Proofpoint-GUID: MJZN75W-QjS2EK8URj73BECtwnKpC8xu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 phishscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for the QDSP6 gcc clock control used on IPQ9574 based devices. This would allow mpd remoteproc driver to control the required gcc clocks to bring the subsystem out of reset. Signed-off-by: Manikanta Mylavarapu --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 159 ++++++++++--------- 1 file changed, 83 insertions(+), 76 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index c89e96d568c6..8bd6350ecd56 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -138,80 +138,87 @@ #define WCSS_AHB_CLK_SRC 129 #define GCC_Q6_AHB_CLK 130 #define GCC_Q6_AHB_S_CLK 131 -#define GCC_WCSS_ECAHB_CLK 132 -#define GCC_WCSS_ACMT_CLK 133 -#define GCC_SYS_NOC_WCSS_AHB_CLK 134 -#define WCSS_AXI_M_CLK_SRC 135 -#define GCC_ANOC_WCSS_AXI_M_CLK 136 -#define QDSS_AT_CLK_SRC 137 -#define GCC_Q6SS_ATBM_CLK 138 -#define GCC_WCSS_DBG_IFC_ATB_CLK 139 -#define GCC_NSSNOC_ATB_CLK 140 -#define GCC_QDSS_AT_CLK 141 -#define GCC_SYS_NOC_AT_CLK 142 -#define GCC_PCNOC_AT_CLK 143 -#define GCC_USB0_EUD_AT_CLK 144 -#define GCC_QDSS_EUD_AT_CLK 145 -#define QDSS_STM_CLK_SRC 146 -#define GCC_QDSS_STM_CLK 147 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 148 -#define QDSS_TRACECLKIN_CLK_SRC 149 -#define GCC_QDSS_TRACECLKIN_CLK 150 -#define QDSS_TSCTR_CLK_SRC 151 -#define GCC_Q6_TSCTR_1TO2_CLK 152 -#define GCC_WCSS_DBG_IFC_NTS_CLK 153 -#define GCC_QDSS_TSCTR_DIV2_CLK 154 -#define GCC_QDSS_TS_CLK 155 -#define GCC_QDSS_TSCTR_DIV4_CLK 156 -#define GCC_NSS_TS_CLK 157 -#define GCC_QDSS_TSCTR_DIV8_CLK 158 -#define GCC_QDSS_TSCTR_DIV16_CLK 159 -#define GCC_Q6SS_PCLKDBG_CLK 160 -#define GCC_Q6SS_TRIG_CLK 161 -#define GCC_WCSS_DBG_IFC_APB_CLK 162 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 163 -#define GCC_QDSS_DAP_CLK 164 -#define GCC_QDSS_APB2JTAG_CLK 165 -#define GCC_QDSS_TSCTR_DIV3_CLK 166 -#define QPIC_IO_MACRO_CLK_SRC 167 -#define GCC_QPIC_IO_MACRO_CLK 168 -#define Q6_AXI_CLK_SRC 169 -#define GCC_Q6_AXIM_CLK 170 -#define GCC_WCSS_Q6_TBU_CLK 171 -#define GCC_MEM_NOC_Q6_AXI_CLK 172 -#define Q6_AXIM2_CLK_SRC 173 -#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 174 -#define GCC_NSSNOC_MEMNOC_CLK 175 -#define GCC_NSSNOC_MEM_NOC_1_CLK 176 -#define GCC_NSS_TBU_CLK 177 -#define GCC_MEM_NOC_NSSNOC_CLK 178 -#define LPASS_AXIM_CLK_SRC 179 -#define LPASS_SWAY_CLK_SRC 180 -#define ADSS_PWM_CLK_SRC 181 -#define GCC_ADSS_PWM_CLK 182 -#define GP1_CLK_SRC 183 -#define GP2_CLK_SRC 184 -#define GP3_CLK_SRC 185 -#define DDRSS_SMS_SLOW_CLK_SRC 186 -#define GCC_XO_CLK_SRC 187 -#define GCC_XO_CLK 188 -#define GCC_NSSNOC_QOSGEN_REF_CLK 189 -#define GCC_NSSNOC_TIMEOUT_REF_CLK 190 -#define GCC_XO_DIV4_CLK 191 -#define GCC_UNIPHY0_SYS_CLK 192 -#define GCC_UNIPHY1_SYS_CLK 193 -#define GCC_UNIPHY2_SYS_CLK 194 -#define GCC_CMN_12GPLL_SYS_CLK 195 -#define GCC_NSSNOC_XO_DCD_CLK 196 -#define GCC_Q6SS_BOOT_CLK 197 -#define UNIPHY_SYS_CLK_SRC 198 -#define NSS_TS_CLK_SRC 199 -#define GCC_ANOC_PCIE0_1LANE_M_CLK 200 -#define GCC_ANOC_PCIE1_1LANE_M_CLK 201 -#define GCC_ANOC_PCIE2_2LANE_M_CLK 202 -#define GCC_ANOC_PCIE3_2LANE_M_CLK 203 -#define GCC_SNOC_PCIE0_1LANE_S_CLK 204 -#define GCC_SNOC_PCIE1_1LANE_S_CLK 205 -#define GCC_SNOC_PCIE2_2LANE_S_CLK 206 -#define GCC_SNOC_PCIE3_2LANE_S_CLK 207 +#define GCC_WCSS_AHB_S_CLK 132 +#define GCC_WCSS_ECAHB_CLK 133 +#define GCC_WCSS_ACMT_CLK 134 +#define GCC_SYS_NOC_WCSS_AHB_CLK 135 +#define WCSS_AXI_M_CLK_SRC 136 +#define GCC_WCSS_AXI_M_CLK 137 +#define GCC_ANOC_WCSS_AXI_M_CLK 138 +#define QDSS_AT_CLK_SRC 139 +#define GCC_Q6SS_ATBM_CLK 140 +#define GCC_WCSS_DBG_IFC_ATB_CLK 141 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 142 +#define GCC_NSSNOC_ATB_CLK 143 +#define GCC_QDSS_AT_CLK 144 +#define GCC_SYS_NOC_AT_CLK 145 +#define GCC_PCNOC_AT_CLK 146 +#define GCC_USB0_EUD_AT_CLK 147 +#define GCC_QDSS_EUD_AT_CLK 148 +#define QDSS_STM_CLK_SRC 149 +#define GCC_QDSS_STM_CLK 150 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 151 +#define QDSS_TRACECLKIN_CLK_SRC 152 +#define GCC_QDSS_TRACECLKIN_CLK 153 +#define QDSS_TSCTR_CLK_SRC 154 +#define GCC_Q6_TSCTR_1TO2_CLK 155 +#define GCC_WCSS_DBG_IFC_NTS_CLK 156 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 157 +#define GCC_QDSS_TSCTR_DIV2_CLK 158 +#define GCC_QDSS_TS_CLK 159 +#define GCC_QDSS_TSCTR_DIV4_CLK 160 +#define GCC_NSS_TS_CLK 161 +#define GCC_QDSS_TSCTR_DIV8_CLK 162 +#define GCC_QDSS_TSCTR_DIV16_CLK 163 +#define GCC_Q6SS_PCLKDBG_CLK 164 +#define GCC_Q6SS_TRIG_CLK 165 +#define GCC_WCSS_DBG_IFC_APB_CLK 166 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 167 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 168 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 169 +#define GCC_QDSS_DAP_CLK 170 +#define GCC_QDSS_APB2JTAG_CLK 171 +#define GCC_QDSS_TSCTR_DIV3_CLK 172 +#define QPIC_IO_MACRO_CLK_SRC 173 +#define GCC_QPIC_IO_MACRO_CLK 174 +#define Q6_AXI_CLK_SRC 175 +#define GCC_Q6_AXIM_CLK 176 +#define GCC_Q6_AXIM2_CLK 177 +#define GCC_WCSS_Q6_TBU_CLK 178 +#define GCC_MEM_NOC_Q6_AXI_CLK 179 +#define Q6_AXIM2_CLK_SRC 180 +#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 181 +#define GCC_NSSNOC_MEMNOC_CLK 182 +#define GCC_NSSNOC_MEM_NOC_1_CLK 183 +#define GCC_NSS_TBU_CLK 184 +#define GCC_MEM_NOC_NSSNOC_CLK 185 +#define LPASS_AXIM_CLK_SRC 186 +#define LPASS_SWAY_CLK_SRC 187 +#define ADSS_PWM_CLK_SRC 188 +#define GCC_ADSS_PWM_CLK 189 +#define GP1_CLK_SRC 190 +#define GP2_CLK_SRC 191 +#define GP3_CLK_SRC 192 +#define DDRSS_SMS_SLOW_CLK_SRC 193 +#define GCC_XO_CLK_SRC 194 +#define GCC_XO_CLK 195 +#define GCC_NSSNOC_QOSGEN_REF_CLK 196 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 197 +#define GCC_XO_DIV4_CLK 198 +#define GCC_UNIPHY0_SYS_CLK 199 +#define GCC_UNIPHY1_SYS_CLK 200 +#define GCC_UNIPHY2_SYS_CLK 201 +#define GCC_CMN_12GPLL_SYS_CLK 202 +#define GCC_NSSNOC_XO_DCD_CLK 203 +#define GCC_Q6SS_BOOT_CLK 204 +#define UNIPHY_SYS_CLK_SRC 205 +#define NSS_TS_CLK_SRC 206 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 207 +#define GCC_ANOC_PCIE1_1LANE_M_CLK 208 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 209 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 210 +#define GCC_SNOC_PCIE0_1LANE_S_CLK 211 +#define GCC_SNOC_PCIE1_1LANE_S_CLK 212 +#define GCC_SNOC_PCIE2_2LANE_S_CLK 213 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 214 #endif From patchwork Tue Mar 7 04:41:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 660629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C01AC678DB for ; Tue, 7 Mar 2023 04:43:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjCGEn3 (ORCPT ); Mon, 6 Mar 2023 23:43:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbjCGEnV (ORCPT ); Mon, 6 Mar 2023 23:43:21 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2574C58C02; Mon, 6 Mar 2023 20:42:50 -0800 (PST) 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04:42:40 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3274gdGG015335 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Mar 2023 04:42:39 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:32 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 06/11] clk: qcom: IPQ9574: Add q6/wcss clocks Date: Tue, 7 Mar 2023 10:11:32 +0530 Message-ID: <1678164097-13247-7-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mZWUR098l_tCIeSe2qFSFw0ydKT1-148 X-Proofpoint-ORIG-GUID: mZWUR098l_tCIeSe2qFSFw0ydKT1-148 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 mlxscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=981 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some of the clocks required for q6/wcss bring up are missing. So this patch adds clocks. Signed-off-by: Manikanta Mylavarapu --- drivers/clk/qcom/gcc-ipq9574.c | 119 +++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 1bf33d582dc2..355f2e12d9c6 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2697,6 +2697,22 @@ static struct clk_branch gcc_wcss_acmt_clk = { }, }; +static struct clk_branch gcc_wcss_ahb_s_clk = { + .halt_reg = 0x25060, + .clkr = { + .enable_reg = 0x25060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_ahb_s_clk", + .parent_hws = (const struct clk_hw *[]){ + &wcss_ahb_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { .halt_reg = 0x2e030, .clkr = { @@ -2734,6 +2750,22 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { }, }; +static struct clk_branch gcc_wcss_axi_m_clk = { + .halt_reg = 0x25064, + .clkr = { + .enable_reg = 0x25064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_axi_m_clk", + .parent_hws = (const struct clk_hw *[]){ + &wcss_axi_m_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_anoc_wcss_axi_m_clk = { .halt_reg = 0x2e0a8, .clkr = { @@ -2803,6 +2835,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { + .halt_reg = 0x2504C, + .clkr = { + .enable_reg = 0x2504C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_at_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_atb_clk = { .halt_reg = 0x17014, .clkr = { @@ -3073,6 +3121,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { + .halt_reg = 0x25050, + .clkr = { + .enable_reg = 0x25050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_tsctr_div2_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_tsctr_div2_clk = { .halt_reg = 0x2d044, .clkr = { @@ -3315,6 +3379,38 @@ static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { + .halt_reg = 0x25048, + .clkr = { + .enable_reg = 0x25048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { + .halt_reg = 0x25054, + .clkr = { + .enable_reg = 0x25054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x2d058, .clkr = { @@ -3513,6 +3609,22 @@ static struct clk_rcg2 q6_axim2_clk_src = { }, }; +static struct clk_branch gcc_q6_axim2_clk = { + .halt_reg = 0x25010, + .clkr = { + .enable_reg = 0x25010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_q6_axim2_clk", + .parent_hws = (const struct clk_hw *[]){ + &q6_axim2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = { F(533333333, P_GPLL0, 1.5, 0, 0), { } @@ -4037,14 +4149,17 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, + [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, + [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, @@ -4059,6 +4174,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, @@ -4068,7 +4184,9 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, + [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, + [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, @@ -4076,6 +4194,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, + [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, From patchwork Tue Mar 7 04:41:33 2023 Content-Type: text/plain; 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Tue, 7 Mar 2023 04:42:47 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:39 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 07/11] mailbox: qcom-apcs-ipc: Add IPQ5018 APCS IPC support Date: Tue, 7 Mar 2023 10:11:33 +0530 Message-ID: <1678164097-13247-8-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Mx0wM2SsvOVpiYZr-IBROUEqjewnafnm X-Proofpoint-ORIG-GUID: Mx0wM2SsvOVpiYZr-IBROUEqjewnafnm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable IPQ5018 APCS IPC support by adding the compatible. Signed-off-by: Manikanta Mylavarapu --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 6bbf87c6d60b..0b873c76fd7e 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -141,6 +141,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { + { .compatible = "qcom,ipq5018-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq5332-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data }, From patchwork Tue Mar 7 04:41:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 660628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2A2DC6FA99 for ; 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Tue, 07 Mar 2023 04:42:56 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3274gtMv016443 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Mar 2023 04:42:55 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:47 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 08/11] remoteproc: qcom: Add Hexagon based multipd rproc driver Date: Tue, 7 Mar 2023 10:11:34 +0530 Message-ID: <1678164097-13247-9-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xpN7XLEQK10gLz1uXHYu77F_cSPwMlsK X-Proofpoint-GUID: xpN7XLEQK10gLz1uXHYu77F_cSPwMlsK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APSS brings Q6 out of reset and then Q6 brings WCSS block (wifi radio's) out of reset. --------------- --> |WiFi 2G radio| | -------------- | -------- ------- | | APSS | ---> |QDSP6| -----| --------- ------- | | | | -------------- --> |WiFi 5G radio| -------------- Problem here is if any radio crashes, subsequently other radio also should crash because Q6 crashed. Let's say 2G radio crashed, Q6 should pass this info to APSS. Only Q6 processor interrupts registered with APSS. Obviously Q6 should crash and raise fatal interrupt to APSS. Due to this 5G radio also crashed. But no issue in 5G radio, because of 2G radio crash 5G radio also impacted. In multi pd model, this problem is resolved. Here WCSS functionality (WiFi radio's) moved out from Q6 root pd to a separate user pd. Due to this, radio's independently pass their status info to APPS with out crashing Q6. So other radio's won't be impacted. --------- |WiFi | --> |2G radio| | --------- ------ Start Q6 ------- | | | ------------------> | | | | | Start WCSS PD1 (2G) | | | |APSS| ----------------------->|QDSP6|-----| | | Start WCSS PD1 (5G) | | | | ----------------------->| |-----| ------ ------- | | | ----------- |-->|WiFi | |5G radio | ----------- According to linux terminology, here consider Q6 as root i.e it provide all services, WCSS (wifi radio's) as user i.e it uses services provided by root. Since Q6 root & WCSS user pd's able to communicate with APSS individually, multipd remoteproc driver registers each PD with rproc framework. Here clients (Wifi host drivers) intrested on WCSS PD rproc, so multipd driver start's root pd in the context of WCSS user pd rproc start. Similarly on down path, root pd will be stopped after wcss user pd stopped. Here WCSS(user) PD is dependent on Q6(root) PD, so first q6 pd should be up before wcss pd. After wcss pd goes down, q6 pd should be turned off. rproc->ops->start(userpd_rproc) { /* Boot root pd rproc */ rproc_boot(upd_dev->parent); --- /* user pd rproc start sequence */ --- --- } With this way we ensure that root pd brought up before userpd. rproc->ops->stop(userpd_rproc) { --- --- /* user pd rproc stop sequence */ --- --- /* Shutdown root pd rproc */ rproc_shutdown(upd_dev->parent); } After userpd rproc stops, root pd rproc will be stopped. IPQ5018, IPQ9574 supports multipd remoteproc driver. Signed-off-by: Manikanta Mylavarapu --- drivers/firmware/qcom_scm.c | 114 +++++ drivers/firmware/qcom_scm.h | 6 + drivers/remoteproc/Kconfig | 20 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/qcom_common.c | 23 + drivers/remoteproc/qcom_common.h | 1 + drivers/remoteproc/qcom_q6v5.c | 41 +- drivers/remoteproc/qcom_q6v5.h | 15 +- drivers/remoteproc/qcom_q6v5_adsp.c | 5 +- drivers/remoteproc/qcom_q6v5_mpd.c | 668 +++++++++++++++++++++++++ drivers/remoteproc/qcom_q6v5_mss.c | 4 +- drivers/remoteproc/qcom_q6v5_pas.c | 3 +- drivers/soc/qcom/mdt_loader.c | 314 ++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 3 + include/linux/soc/qcom/mdt_loader.h | 19 + 15 files changed, 1228 insertions(+), 9 deletions(-) create mode 100644 drivers/remoteproc/qcom_q6v5_mpd.c diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index d88c5f14bd54..d69560963353 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -654,6 +654,120 @@ int qcom_scm_pas_shutdown(u32 peripheral) } EXPORT_SYMBOL(qcom_scm_pas_shutdown); +/** + * qti_scm_int_radio_powerup - Bring up internal radio userpd + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qti_scm_int_radio_powerup(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_UP_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerup); + +/** + * qti_scm_int_radio_powerdown() - Shut down internal radio userpd + * + * @peripheral: peripheral id + * + * Returns 0 on success. + */ +int qti_scm_int_radio_powerdown(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_DN_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerdown); + +/** + * qti_scm_pdseg_memcpy_v2() - copy userpd PIL segments data to dma blocks + * + * @peripheral: peripheral id + * @phno: program header no + * @dma: handle of dma region + * @seg_cnt: no of dma blocks + * + * Returns 0 if trustzone successfully loads userpd PIL segments from dma + * blocks to DDR + */ +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, + int seg_cnt) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_PD_LOAD_V2_CMD_ID, + .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_RW, QCOM_SCM_VAL), + .args[0] = peripheral, + .args[1] = phno, + .args[2] = dma, + .args[3] = seg_cnt, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_pdseg_memcpy_v2); + /** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index e6e512bd57d1..99e3ab2f1986 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -132,6 +132,12 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 +#define QCOM_SCM_PD_LOAD_SVC_ID 0x2 +#define QCOM_SCM_PD_LOAD_CMD_ID 0x16 +#define QCOM_SCM_PD_LOAD_V2_CMD_ID 0x19 +#define QCOM_SCM_INT_RAD_PWR_UP_CMD_ID 0x17 +#define QCOM_SCM_INT_RAD_PWR_DN_CMD_ID 0x18 + #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a850e9f486dd..44af5c36f67e 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -234,6 +234,26 @@ config QCOM_Q6V5_PAS CDSP (Compute DSP), MPSS (Modem Peripheral SubSystem), and SLPI (Sensor Low Power Island). +config QCOM_Q6V5_MPD + tristate "Qualcomm Hexagon based MPD model Peripheral Image Loader" + depends on OF && ARCH_QCOM + depends on QCOM_SMEM + depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n + depends on QCOM_SYSMON || QCOM_SYSMON=n + depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n + select MFD_SYSCON + select QCOM_MDT_LOADER + select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM + help + Say y here to support the Qualcomm Secure Peripheral Image Loader + for the Hexagon based MultiPD model remote processors on e.g. IPQ5018. + This is trustZone wireless subsystem. + config QCOM_Q6V5_WCSS tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader" depends on OF && ARCH_QCOM diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 91314a9b43ce..b64051080ec1 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o +obj-$(CONFIG_QCOM_Q6V5_MPD) += qcom_q6v5_mpd.o obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index a0d4238492e9..b72fbda02242 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -510,5 +510,28 @@ void qcom_remove_ssr_subdev(struct rproc *rproc, struct qcom_rproc_ssr *ssr) } EXPORT_SYMBOL_GPL(qcom_remove_ssr_subdev); +/** + * qcom_get_pd_asid() - get the pd asid number from DT node + * @node: device tree node + * + * Returns asid if node name has 'pd' string + */ +s8 qcom_get_pd_asid(struct device_node *node) +{ + char *str; + u8 pd_asid; + + if (!node) + return -EINVAL; + + str = strstr(node->name, "pd"); + if (!str) + return 0; + + str += strlen("pd"); + return kstrtos8(str, 10, &pd_asid) ? -EINVAL : pd_asid; +} +EXPORT_SYMBOL(qcom_get_pd_asid); + MODULE_DESCRIPTION("Qualcomm Remoteproc helper driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/remoteproc/qcom_common.h b/drivers/remoteproc/qcom_common.h index 9ef4449052a9..9f3fb11224aa 100644 --- a/drivers/remoteproc/qcom_common.h +++ b/drivers/remoteproc/qcom_common.h @@ -75,5 +75,6 @@ static inline bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon) return false; } #endif +s8 qcom_get_pd_asid(struct device_node *node); #endif diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 192c7aa0e39e..b88bf3a8e53b 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -118,7 +118,7 @@ static irqreturn_t q6v5_wdog_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) +irqreturn_t q6v5_fatal_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; size_t len; @@ -139,7 +139,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_ready_interrupt(int irq, void *data) +irqreturn_t q6v5_ready_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -183,7 +183,16 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_stop_interrupt(int irq, void *data) +irqreturn_t q6v5_spawn_interrupt(int irq, void *data) +{ + struct qcom_q6v5 *q6v5 = data; + + complete(&q6v5->spawn_done); + + return IRQ_HANDLED; +} + +irqreturn_t q6v5_stop_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -220,6 +229,28 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) } EXPORT_SYMBOL_GPL(qcom_q6v5_request_stop); +/** + * qcom_q6v5_request_spawn() - request the remote processor to spawn + * @q6v5: reference to qcom_q6v5 context + * + * Return: 0 on success, negative errno on failure + */ +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5) +{ + int ret; + + ret = qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), BIT(q6v5->spawn_bit)); + + ret = wait_for_completion_timeout(&q6v5->spawn_done, 5 * HZ); + + qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), 0); + + return ret == 0 ? -ETIMEDOUT : 0; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_request_spawn); + /** * qcom_q6v5_panic() - panic handler to invoke a stop on the remote * @q6v5: reference to qcom_q6v5 context @@ -250,7 +281,8 @@ EXPORT_SYMBOL_GPL(qcom_q6v5_panic); * Return: 0 on success, negative errno on failure */ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, - struct rproc *rproc, int crash_reason, const char *load_state, + struct rproc *rproc, int remote_id, int crash_reason, + const char *load_state, void (*handover)(struct qcom_q6v5 *q6v5)) { int ret; @@ -258,6 +290,7 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, q6v5->rproc = rproc; q6v5->dev = &pdev->dev; q6v5->crash_reason = crash_reason; + q6v5->remote_id = remote_id; q6v5->handover = handover; init_completion(&q6v5->start_done); diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h index 5a859c41896e..d00568339d46 100644 --- a/drivers/remoteproc/qcom_q6v5.h +++ b/drivers/remoteproc/qcom_q6v5.h @@ -18,22 +18,29 @@ struct qcom_q6v5 { struct qcom_smem_state *state; struct qmp *qmp; + struct qcom_smem_state *shutdown_state; + struct qcom_smem_state *spawn_state; struct icc_path *path; unsigned stop_bit; + unsigned shutdown_bit; + unsigned spawn_bit; int wdog_irq; int fatal_irq; int ready_irq; int handover_irq; int stop_irq; + int spawn_irq; bool handover_issued; struct completion start_done; struct completion stop_done; + struct completion spawn_done; + int remote_id; int crash_reason; bool running; @@ -43,14 +50,20 @@ struct qcom_q6v5 { }; int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev, - struct rproc *rproc, int crash_reason, const char *load_state, + struct rproc *rproc, int remote_id, int crash_reason, + const char *load_state, void (*handover)(struct qcom_q6v5 *q6v5)); void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5); int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5); int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5); +irqreturn_t q6v5_fatal_interrupt(int irq, void *data); +irqreturn_t q6v5_ready_interrupt(int irq, void *data); +irqreturn_t q6v5_spawn_interrupt(int irq, void *data); +irqreturn_t q6v5_stop_interrupt(int irq, void *data); #endif diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 08d8dad22ca7..bf8909ad5ff5 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -733,8 +733,9 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto disable_pm; - ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, - desc->load_state, qcom_adsp_pil_handover); + ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, QCOM_SMEM_HOST_ANY, + desc->crash_reason_smem, desc->load_state, + qcom_adsp_pil_handover); if (ret) goto disable_pm; diff --git a/drivers/remoteproc/qcom_q6v5_mpd.c b/drivers/remoteproc/qcom_q6v5_mpd.c new file mode 100644 index 000000000000..853aa3bc5859 --- /dev/null +++ b/drivers/remoteproc/qcom_q6v5_mpd.c @@ -0,0 +1,668 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Linaro Ltd. + * Copyright (C) 2014 Sony Mobile Communications AB + * Copyright (c) 2012-2018, 2021 The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qcom_common.h" +#include "qcom_q6v5.h" + +#include "remoteproc_internal.h" + +#define WCSS_CRASH_REASON 421 +#define WCSS_SMEM_HOST 1 + +#define WCNSS_PAS_ID 6 +#define MPD_WCNSS_PAS_ID 0xD + +#define BUF_SIZE 35 + +/** + * enum state - state of a wcss (private) + * @WCSS_NORMAL: subsystem is operating normally + * @WCSS_CRASHED: subsystem has crashed and hasn't been shutdown + * @WCSS_RESTARTING: subsystem has been shutdown and is now restarting + * @WCSS_SHUTDOWN: subsystem has been shutdown + * + */ +enum q6_wcss_state { + WCSS_NORMAL, + WCSS_CRASHED, + WCSS_RESTARTING, + WCSS_SHUTDOWN, +}; + +enum { + Q6_IPQ, + WCSS_AHB_IPQ, + WCSS_PCIE_IPQ, +}; + +struct q6_wcss { + struct device *dev; + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_q6v5 q6; + phys_addr_t mem_phys; + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; + int crash_reason_smem; + u32 version; + s8 pd_asid; + enum q6_wcss_state state; +}; + +struct wcss_data { + int (*init_irq)(struct qcom_q6v5 *q6, struct platform_device *pdev, + struct rproc *rproc, int remote_id, + int crash_reason, const char *load_state, + void (*handover)(struct qcom_q6v5 *q6)); + const char *q6_firmware_name; + int crash_reason_smem; + int remote_id; + u32 version; + const char *ssr_name; + const struct rproc_ops *ops; + bool need_auto_boot; + bool glink_subdev_required; + s8 pd_asid; + bool reset_seq; + u32 pasid; + int (*mdt_load_sec)(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base); +}; + +static int q6_wcss_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + int ret; + struct device_node *upd_np; + struct platform_device *upd_pdev; + struct rproc *upd_rproc; + struct q6_wcss *upd_wcss; + const struct wcss_data *desc; + + desc = of_device_get_match_data(wcss->dev); + if (!desc) + return -EINVAL; + + qcom_q6v5_prepare(&wcss->q6); + + ret = qcom_scm_pas_auth_and_reset(desc->pasid); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, 5 * HZ); + if (ret == -ETIMEDOUT) + dev_err(wcss->dev, "start timed out\n"); + + /* Bring userpd wcss state to default value */ + for_each_available_child_of_node(wcss->dev->of_node, upd_np) { + if (!strstr(upd_np->name, "pd")) + continue; + upd_pdev = of_find_device_by_node(upd_np); + upd_rproc = platform_get_drvdata(upd_pdev); + upd_wcss = upd_rproc->priv; + upd_wcss->state = WCSS_NORMAL; + } + return ret; +} + +static int q6_wcss_spawn_pd(struct rproc *rproc) +{ + int ret; + struct q6_wcss *wcss = rproc->priv; + + ret = qcom_q6v5_request_spawn(&wcss->q6); + if (ret == -ETIMEDOUT) { + pr_err("%s spawn timedout\n", rproc->name); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, msecs_to_jiffies(10000)); + if (ret == -ETIMEDOUT) { + pr_err("%s start timedout\n", rproc->name); + wcss->q6.running = false; + return ret; + } + wcss->q6.running = true; + return ret; +} + +static int wcss_ahb_pcie_pd_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + const struct wcss_data *desc = of_device_get_match_data(wcss->dev); + int ret; + + if (desc->reset_seq) { + ret = qti_scm_int_radio_powerup(desc->pasid); + if (ret) { + dev_err(wcss->dev, "failed to power up ahb pd\n"); + return ret; + } + } + + if (wcss->q6.spawn_bit) { + ret = q6_wcss_spawn_pd(rproc); + if (ret) + return ret; + } + + wcss->state = WCSS_NORMAL; + return 0; +} + +static int q6_wcss_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + int ret; + const struct wcss_data *desc = + of_device_get_match_data(wcss->dev); + + if (!desc) + return -EINVAL; + + ret = qcom_scm_pas_shutdown(desc->pasid); + if (ret) { + dev_err(wcss->dev, "not able to shutdown\n"); + return ret; + } + qcom_q6v5_unprepare(&wcss->q6); + + return 0; +} + +static int wcss_ahb_pcie_pd_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + const struct wcss_data *desc = of_device_get_match_data(wcss->dev); + int ret; + + if (rproc->state != RPROC_CRASHED && wcss->q6.stop_bit) { + ret = qcom_q6v5_request_stop(&wcss->q6, NULL); + if (ret) { + dev_err(&rproc->dev, "pd not stopped\n"); + return ret; + } + } + + if (desc->reset_seq) { + ret = qti_scm_int_radio_powerdown(desc->pasid); + if (ret) { + dev_err(wcss->dev, "failed to power down pd\n"); + return ret; + } + } + + if (rproc->state != RPROC_CRASHED) + rproc_shutdown(rpd_rproc); + + wcss->state = WCSS_SHUTDOWN; + return 0; +} + +static void *q6_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, + bool *is_iomem) +{ + struct q6_wcss *wcss = rproc->priv; + int offset; + + offset = da - wcss->mem_reloc; + if (offset < 0 || offset + len > wcss->mem_size) + return NULL; + + return wcss->mem_region + offset; +} + +static int q6_wcss_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv; + const struct firmware *m3_fw; + int ret; + const char *m3_fw_name; + struct device_node *upd_np; + struct platform_device *upd_pdev; + const struct wcss_data *desc = + of_device_get_match_data(wcss->dev); + + if (!desc) + return -EINVAL; + + /* load m3 firmware */ + for_each_available_child_of_node(wcss->dev->of_node, upd_np) { + if (!strstr(upd_np->name, "pd")) + continue; + upd_pdev = of_find_device_by_node(upd_np); + + ret = of_property_read_string(upd_np, "m3_firmware", + &m3_fw_name); + if (!ret && m3_fw_name) { + ret = request_firmware(&m3_fw, m3_fw_name, + &upd_pdev->dev); + if (ret) + continue; + + ret = qcom_mdt_load_no_init(wcss->dev, m3_fw, + m3_fw_name, 0, + wcss->mem_region, + wcss->mem_phys, + wcss->mem_size, + &wcss->mem_reloc); + + release_firmware(m3_fw); + + if (ret) { + dev_err(wcss->dev, + "can't load m3_fw.bXX ret:%d\n", ret); + return ret; + } + } + } + + return qcom_mdt_load(wcss->dev, fw, rproc->firmware, + desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); +} + +static int wcss_ahb_pcie_pd_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv, *wcss_rpd; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + int ret; + const struct wcss_data *desc = + of_device_get_match_data(wcss->dev); + + if (!desc) + return -EINVAL; + + wcss_rpd = rpd_rproc->priv; + + /* Boot rootpd rproc */ + ret = rproc_boot(rpd_rproc); + if (ret || wcss->state == WCSS_NORMAL) + return ret; + + return desc->mdt_load_sec(wcss->dev, fw, rproc->firmware, + desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); +} + +static unsigned long q6_wcss_panic(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + + return qcom_q6v5_panic(&wcss->q6); +} + +static const struct rproc_ops wcss_ahb_pcie_ipq5018_ops = { + .start = wcss_ahb_pcie_pd_start, + .stop = wcss_ahb_pcie_pd_stop, + .load = wcss_ahb_pcie_pd_load, +}; + +static const struct rproc_ops q6_wcss_ipq5018_ops = { + .start = q6_wcss_start, + .stop = q6_wcss_stop, + .da_to_va = q6_wcss_da_to_va, + .load = q6_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .panic = q6_wcss_panic, +}; + +static int q6_alloc_memory_region(struct q6_wcss *wcss) +{ + struct reserved_mem *rmem = NULL; + struct device_node *node; + struct device *dev = wcss->dev; + + if (wcss->version == Q6_IPQ) { + node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (node) + rmem = of_reserved_mem_lookup(node); + + of_node_put(node); + + if (!rmem) { + dev_err(dev, "unable to acquire memory-region\n"); + return -EINVAL; + } + } else { + struct rproc *rpd_rproc = dev_get_drvdata(dev->parent); + struct q6_wcss *rpd_wcss = rpd_rproc->priv; + + wcss->mem_phys = rpd_wcss->mem_phys; + wcss->mem_reloc = rpd_wcss->mem_reloc; + wcss->mem_size = rpd_wcss->mem_size; + wcss->mem_region = rpd_wcss->mem_region; + return 0; + } + + wcss->mem_phys = rmem->base; + wcss->mem_reloc = rmem->base; + wcss->mem_size = rmem->size; + wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); + if (!wcss->mem_region) { + dev_err(dev, "unable to map memory region: %pa+%pa\n", + &rmem->base, &rmem->size); + return -EBUSY; + } + + return 0; +} + +static int q6_get_inbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name, + irqreturn_t (*handler)(int irq, void *data)) +{ + int ret, irq; + char *interrupt, *tmp = (char *)int_name; + struct q6_wcss *wcss = q6->rproc->priv; + + irq = platform_get_irq_byname(pdev, int_name); + if (irq < 0) { + if (irq != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to retrieve %s IRQ: %d\n", + int_name, irq); + return irq; + } + + if (!strcmp(int_name, "fatal")) { + q6->fatal_irq = irq; + } else if (!strcmp(int_name, "stop-ack")) { + q6->stop_irq = irq; + tmp = "stop_ack"; + } else if (!strcmp(int_name, "ready")) { + q6->ready_irq = irq; + } else if (!strcmp(int_name, "handover")) { + q6->handover_irq = irq; + } else if (!strcmp(int_name, "spawn-ack")) { + q6->spawn_irq = irq; + tmp = "spawn_ack"; + } else { + dev_err(&pdev->dev, "unknown interrupt\n"); + return -EINVAL; + } + + interrupt = devm_kzalloc(&pdev->dev, BUF_SIZE, GFP_KERNEL); + if (!interrupt) + return -ENOMEM; + + snprintf(interrupt, BUF_SIZE, "q6v5_wcss_userpd%d", wcss->pd_asid); + strlcat(interrupt, "_", BUF_SIZE); + strlcat(interrupt, tmp, BUF_SIZE); + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + interrupt, q6); + if (ret) { + dev_err(&pdev->dev, "failed to acquire %s irq\n", interrupt); + return ret; + } + return 0; +} + +static int q6_get_outbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name) +{ + struct qcom_smem_state *tmp_state; + unsigned bit; + + tmp_state = qcom_smem_state_get(&pdev->dev, int_name, &bit); + if (IS_ERR(tmp_state)) { + dev_err(&pdev->dev, "failed to acquire %s state\n", int_name); + return PTR_ERR(tmp_state); + } + + if (!strcmp(int_name, "stop")) { + q6->state = tmp_state; + q6->stop_bit = bit; + } else if (!strcmp(int_name, "spawn")) { + q6->spawn_state = tmp_state; + q6->spawn_bit = bit; + } + + return 0; +} + +static int init_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, struct rproc *rproc, + int remote_id, int crash_reason, const char *load_state, + void (*handover)(struct qcom_q6v5 *q6)) +{ + int ret; + + q6->rproc = rproc; + q6->dev = &pdev->dev; + q6->crash_reason = crash_reason; + q6->remote_id = remote_id; + q6->handover = handover; + + init_completion(&q6->start_done); + init_completion(&q6->stop_done); + init_completion(&q6->spawn_done); + + ret = q6_get_inbound_irq(q6, pdev, "fatal", + q6v5_fatal_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "ready", + q6v5_ready_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "stop-ack", + q6v5_stop_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "spawn-ack", + q6v5_spawn_interrupt); + if (ret) + return ret; + + ret = q6_get_outbound_irq(q6, pdev, "stop"); + if (ret) + return ret; + + ret = q6_get_outbound_irq(q6, pdev, "spawn"); + if (ret) + return ret; + + return 0; +} + +static int q6_wcss_probe(struct platform_device *pdev) +{ + const struct wcss_data *desc; + struct q6_wcss *wcss; + struct rproc *rproc; + int ret; + char *subdev_name; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, + desc->q6_firmware_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; + } + wcss = rproc->priv; + wcss->dev = &pdev->dev; + wcss->version = desc->version; + + ret = q6_alloc_memory_region(wcss); + if (ret) + goto free_rproc; + + wcss->pd_asid = qcom_get_pd_asid(wcss->dev->of_node); + if (wcss->pd_asid < 0) + goto free_rproc; + + if (desc->init_irq) { + ret = desc->init_irq(&wcss->q6, pdev, rproc, desc->remote_id, + desc->crash_reason_smem, NULL, NULL); + if (ret) { + if (wcss->version == Q6_IPQ) + goto free_rproc; + else + dev_info(wcss->dev, + "userpd irq registration failed\n"); + } + } + + if (desc->glink_subdev_required) + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name); + + subdev_name = (char *)(desc->ssr_name ? desc->ssr_name : pdev->name); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, subdev_name); + + rproc->auto_boot = desc->need_auto_boot; + ret = rproc_add(rproc); + if (ret) + goto free_rproc; + + platform_set_drvdata(pdev, rproc); + + ret = of_platform_populate(wcss->dev->of_node, NULL, + NULL, wcss->dev); + if (ret) { + dev_err(&pdev->dev, "failed to populate wcss pd nodes\n"); + goto free_rproc; + } + return 0; + +free_rproc: + rproc_free(rproc); + + return ret; +} + +static int q6_wcss_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct q6_wcss *wcss = rproc->priv; + + if (wcss->version == Q6_IPQ) + qcom_q6v5_deinit(&wcss->q6); + + rproc_del(rproc); + rproc_free(rproc); + + return 0; +} + +static const struct wcss_data q6_ipq5018_res_init = { + .init_irq = qcom_q6v5_init, + .q6_firmware_name = "IPQ5018/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .remote_id = WCSS_SMEM_HOST, + .ssr_name = "q6wcss", + .ops = &q6_wcss_ipq5018_ops, + .version = Q6_IPQ, + .glink_subdev_required = true, + .pasid = MPD_WCNSS_PAS_ID, +}; + +static const struct wcss_data q6_ipq9574_res_init = { + .init_irq = qcom_q6v5_init, + .q6_firmware_name = "IPQ9574/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .remote_id = WCSS_SMEM_HOST, + .ssr_name = "q6wcss", + .ops = &q6_wcss_ipq5018_ops, + .version = Q6_IPQ, + .glink_subdev_required = true, + .pasid = WCNSS_PAS_ID, +}; + +static const struct wcss_data wcss_ahb_ipq5018_res_init = { + .init_irq = init_irq, + .q6_firmware_name = "IPQ5018/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .remote_id = WCSS_SMEM_HOST, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_AHB_IPQ, + .pasid = MPD_WCNSS_PAS_ID, + .reset_seq = true, + .mdt_load_sec = qcom_mdt_load_pd_seg, +}; + +static const struct wcss_data wcss_ahb_ipq9574_res_init = { + .init_irq = init_irq, + .q6_firmware_name = "IPQ9574/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .remote_id = WCSS_SMEM_HOST, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_AHB_IPQ, + .pasid = WCNSS_PAS_ID, + .mdt_load_sec = qcom_mdt_load, +}; + +static const struct wcss_data wcss_pcie_ipq5018_res_init = { + .init_irq = init_irq, + .q6_firmware_name = "IPQ5018/q6_fw.mdt", + .crash_reason_smem = WCSS_CRASH_REASON, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_PCIE_IPQ, + .mdt_load_sec = qcom_mdt_load_pd_seg, + .pasid = MPD_WCNSS_PAS_ID, +}; + +static const struct of_device_id q6_wcss_of_match[] = { + { .compatible = "qcom,ipq5018-q6-mpd", .data = &q6_ipq5018_res_init }, + { .compatible = "qcom,ipq9574-q6-mpd", .data = &q6_ipq9574_res_init }, + { .compatible = "qcom,ipq5018-wcss-ahb-mpd", + .data = &wcss_ahb_ipq5018_res_init }, + { .compatible = "qcom,ipq9574-wcss-ahb-mpd", + .data = &wcss_ahb_ipq9574_res_init }, + { .compatible = "qcom,ipq5018-wcss-pcie-mpd", + .data = &wcss_pcie_ipq5018_res_init }, + { }, +}; +MODULE_DEVICE_TABLE(of, q6_wcss_of_match); + +static struct platform_driver q6_wcss_driver = { + .probe = q6_wcss_probe, + .remove = q6_wcss_remove, + .driver = { + .name = "qcom-q6-mpd", + .of_match_table = q6_wcss_of_match, + }, +}; +module_platform_driver(q6_wcss_driver); + +MODULE_DESCRIPTION("Hexagon WCSS Multipd Peripheral Image Loader"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index ab053084f7a2..48685bb85718 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "remoteproc_internal.h" #include "qcom_common.h" @@ -2070,7 +2071,8 @@ static int q6v5_probe(struct platform_device *pdev) qproc->need_mem_protection = desc->need_mem_protection; qproc->has_mba_logs = desc->has_mba_logs; - ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem", + ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, QCOM_SMEM_HOST_ANY, + MPSS_CRASH_REASON_SMEM, "modem", qcom_msa_handover); if (ret) goto detach_proxy_pds; diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 0871108fb4dc..7408218042e5 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -723,7 +723,8 @@ static int adsp_probe(struct platform_device *pdev) goto free_rproc; adsp->proxy_pd_count = ret; - ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, desc->load_state, + ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, QCOM_SMEM_HOST_ANY, + desc->crash_reason_smem, desc->load_state, qcom_pas_handover); if (ret) goto detach_proxy_pds; diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 33dd8c315eb7..a5ca5a078943 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -16,6 +16,40 @@ #include #include #include +#include + +#include "../../remoteproc/qcom_common.h" +#define PDSEG_PAS_ID 0xD + +/** + * struct region - structure passed to TrustZone + * @addr: address of dma region, where dma blocks/chunks address resides + * @blk_size: size of each block + */ +struct region { + u64 addr; + unsigned blk_size; +}; + +/** + * struct pdseg_dma_mem_info + * @tz_addr: reference to structure passed to trustzone + * @blocks: no of blocks + * @tz_dma: dma handle of tz_addr + * @dma_blk_arr_addr_phys: dma handle of dma_blk_arr_addr + * @dma_blk_arr_addr: VA of dma array, where each index points to + * dma block PA + * @pt: stores VA of each block + */ + +struct pdseg_dma_mem_info { + struct region *tz_addr; + int blocks; + dma_addr_t tz_dma; + dma_addr_t dma_blk_arr_addr_phys; + u64 *dma_blk_arr_addr; + void **pt; +}; static bool mdt_phdr_valid(const struct elf32_phdr *phdr) { @@ -358,6 +392,259 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, return ret; } +static int allocate_dma_mem(struct device *dev, + struct pdseg_dma_mem_info *pd_dma, + int max_size) +{ + dma_addr_t dma_tmp = 0; + int i; + + pd_dma->blocks = DIV_ROUND_UP(max_size, PAGE_SIZE); + + /* Allocate dma memory for structure passed to trust zone */ + pd_dma->tz_addr = dma_alloc_coherent(dev, sizeof(struct region), + &pd_dma->tz_dma, GFP_DMA); + if (!pd_dma->tz_addr) { + pr_err("Error in dma alloc\n"); + return -ENOMEM; + } + + /* Allocate dma memory to store array of blocks PA */ + pd_dma->dma_blk_arr_addr = + dma_alloc_coherent(dev, (pd_dma->blocks * sizeof(u64)), + &pd_dma->dma_blk_arr_addr_phys, GFP_DMA); + if (!pd_dma->dma_blk_arr_addr) { + pr_err("Error in dma alloc\n"); + goto free_tz_dma_alloc; + } + + /* Assign dma block array PA to trustzone structure addr variable */ + memcpy(&pd_dma->tz_addr->addr, &pd_dma->dma_blk_arr_addr_phys, + sizeof(dma_addr_t)); + + /* Allocate memory to store array of blocks VA */ + pd_dma->pt = kzalloc(pd_dma->blocks * sizeof(void *), GFP_KERNEL); + if (!pd_dma->pt) { + pr_err("Error in memory alloc\n"); + goto free_dma_blk_arr_alloc; + } + + for (i = 0; i < pd_dma->blocks; i++) { + /* Allocate dma memory for blocks with PAGE_SIZE each */ + pd_dma->pt[i] = dma_alloc_coherent(dev, PAGE_SIZE, + &dma_tmp, GFP_DMA); + if (!pd_dma->pt[i]) { + pr_err("Error in dma alloc i:%d - blocks:%d\n", i, + pd_dma->blocks); + goto free_mem_alloc; + } + + /* Assign dma block PA to dma_blk_arr_addr */ + memcpy(&pd_dma->dma_blk_arr_addr[i], &dma_tmp, + sizeof(dma_addr_t)); + } + pd_dma->tz_addr->blk_size = PAGE_SIZE; + return 0; + +free_mem_alloc: + i = 0; + while (i < pd_dma->blocks && pd_dma->pt[i]) { + memcpy(&dma_tmp, &pd_dma->dma_blk_arr_addr[i], + sizeof(dma_addr_t)); + dma_free_coherent(dev, PAGE_SIZE, pd_dma->pt[i], dma_tmp); + i++; + } + kfree(pd_dma->pt); +free_dma_blk_arr_alloc: + dma_free_coherent(dev, (pd_dma->blocks * sizeof(u64)), + pd_dma->dma_blk_arr_addr, + pd_dma->dma_blk_arr_addr_phys); +free_tz_dma_alloc: + dma_free_coherent(dev, sizeof(struct region), pd_dma->tz_addr, + pd_dma->tz_dma); + + return -ENOMEM; +} + +static void free_dma_mem(struct device *dev, struct pdseg_dma_mem_info *pd_dma) +{ + int i; + dma_addr_t dma_tmp = 0; + + for (i = 0; i < pd_dma->blocks; i++) { + memcpy(&dma_tmp, &pd_dma->dma_blk_arr_addr[i], + sizeof(dma_addr_t)); + dma_free_coherent(dev, PAGE_SIZE, pd_dma->pt[i], + dma_tmp); + } + + dma_free_coherent(dev, (pd_dma->blocks * sizeof(u64)), + pd_dma->dma_blk_arr_addr, + pd_dma->dma_blk_arr_addr_phys); + + dma_free_coherent(dev, sizeof(struct region), pd_dma->tz_addr, + pd_dma->tz_dma); + kfree(pd_dma->pt); +} + +static int memcpy_pdseg_to_dma_blk(const char *fw_name, struct device *dev, + int ph_no, struct pdseg_dma_mem_info *pd_dma) +{ + const struct firmware *seg_fw; + int ret, offset_tmp = 0, tmp = 0; + size_t size = 0; + + ret = request_firmware(&seg_fw, fw_name, dev); + if (ret) { + dev_err(dev, "failed to load %s\n", fw_name); + return ret; + } + size = seg_fw->size < PAGE_SIZE ? + seg_fw->size : PAGE_SIZE; + while (tmp < pd_dma->blocks && size) { + memset_io(pd_dma->pt[tmp], 0, PAGE_SIZE); + memcpy_toio(pd_dma->pt[tmp], seg_fw->data + offset_tmp, size); + tmp++; + offset_tmp += size; + if ((seg_fw->size - offset_tmp) < PAGE_SIZE) + size = seg_fw->size - offset_tmp; + } + release_firmware(seg_fw); + ret = qti_scm_pdseg_memcpy_v2(PDSEG_PAS_ID, ph_no, pd_dma->tz_dma, + tmp); + if (ret) { + dev_err(dev, "pd seg memcpy scm failed\n"); + return ret; + } + return ret; +} + +static int __qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base, bool pas_init) +{ + const struct elf32_phdr *phdrs; + const struct elf32_phdr *phdr; + const struct elf32_hdr *ehdr; + phys_addr_t mem_reloc; + phys_addr_t min_addr = PHYS_ADDR_MAX; + ssize_t offset; + bool relocate = false; + int ret = 0; + int i; + u8 pd_asid; + int max_size = 0; + struct pdseg_dma_mem_info pd_dma = {0}; + char *firmware_name; + size_t fw_name_len = strlen(fw_name); + + if (!fw || !mem_region || !mem_phys || !mem_size) + return -EINVAL; + + firmware_name = kstrdup(fw_name, GFP_KERNEL); + if (!firmware_name) + return -ENOMEM; + + pd_asid = qcom_get_pd_asid(dev->of_node); + + ehdr = (struct elf32_hdr *)fw->data; + phdrs = (struct elf32_phdr *)(ehdr + 1); + + for (i = 0; i < ehdr->e_phnum; i++) { + phdr = &phdrs[i]; + + if (!mdt_phdr_valid(phdr)) + continue; + /* + * While doing PD specific reloading, load only that PD + * specific writeable entries. Skip others + */ + if ((QCOM_MDT_PF_ASID(phdr->p_flags) != pd_asid) || + ((phdr->p_flags & PF_W) == 0)) + continue; + + if (phdr->p_flags & QCOM_MDT_RELOCATABLE) + relocate = true; + + if (phdr->p_paddr < min_addr) + min_addr = phdr->p_paddr; + + if (max_size < phdr->p_memsz) + max_size = phdr->p_memsz; + } + + /** + * During userpd PIL segments reloading, Q6 is live. Due to + * this we can't access memory region of PIL segments. So + * create DMA chunks/blocks to store PIL segments data. + */ + ret = allocate_dma_mem(dev, &pd_dma, max_size); + if (ret) + goto out; + + if (relocate) { + /* + * The image is relocatable, so offset each segment based on + * the lowest segment address. + */ + mem_reloc = min_addr; + } else { + /* + * Image is not relocatable, so offset each segment based on + * the allocated physical chunk of memory. + */ + mem_reloc = mem_phys; + } + + for (i = 0; i < ehdr->e_phnum; i++) { + phdr = &phdrs[i]; + + if (!mdt_phdr_valid(phdr)) + continue; + + /* + * While doing PD specific reloading, load only that PD + * specific writeable entries. Skip others + */ + if ((QCOM_MDT_PF_ASID(phdr->p_flags) != pd_asid) || + ((phdr->p_flags & PF_W) == 0)) + continue; + + offset = phdr->p_paddr - mem_reloc; + if (offset < 0 || offset + phdr->p_memsz > mem_size) { + dev_err(dev, "segment outside memory range\n"); + ret = -EINVAL; + break; + } + + if (phdr->p_filesz > phdr->p_memsz) { + dev_err(dev, + "refusing to load segment %d with p_filesz > p_memsz\n", + i); + ret = -EINVAL; + break; + } + + if (phdr->p_filesz) { + snprintf(firmware_name + fw_name_len - 3, 4, "b%02d", i); + + /* copy PIL segments data to dma blocks */ + ret = memcpy_pdseg_to_dma_blk(firmware_name, dev, i, &pd_dma); + if (ret) + goto free_dma; + } + } +free_dma: + free_dma_mem(dev, &pd_dma); + +out: + if (reloc_base) + *reloc_base = mem_reloc; + + return ret; +} + /** * qcom_mdt_load() - load the firmware which header is loaded as fw * @dev: device handle to associate resources with @@ -410,5 +697,32 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, } EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init); +/** + * qcom_mdt_load_pd_seg() - load userpd specific PIL segements + * @dev: device handle to associate resources with + * @fw: firmware object for the mdt file + * @firmware: name of the firmware, for construction of segment file names + * @pas_id: PAS identifier + * @mem_region: allocated memory region to load firmware into + * @mem_phys: physical address of allocated memory region + * @mem_size: size of the allocated memory region + * @reloc_base: adjusted physical address after relocation + * + * Here userpd PIL segements are stitched with rootpd firmware. + * This function reloads userpd specific PIL segments during SSR + * of userpd. + * + * Returns 0 on success, negative errno otherwise. + */ +int qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *firmware, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base) +{ + return __qcom_mdt_load_pd_seg(dev, fw, firmware, pas_id, mem_region, mem_phys, + mem_size, reloc_base, true); +} +EXPORT_SYMBOL_GPL(qcom_mdt_load_pd_seg); + MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 1e449a5d7f5c..0bdb9b506ad1 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -81,6 +81,9 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); extern bool qcom_scm_pas_supported(u32 peripheral); +int qti_scm_int_radio_powerup(u32 peripheral); +int qti_scm_int_radio_powerdown(u32 peripheral); +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, int seg_cnt); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h index 9e8e60421192..57021236dfc9 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -7,6 +7,11 @@ #define QCOM_MDT_TYPE_MASK (7 << 24) #define QCOM_MDT_TYPE_HASH (2 << 24) #define QCOM_MDT_RELOCATABLE BIT(27) +#define QCOM_MDT_ASID_MASK 0xfu +#define QCOM_MDT_PF_ASID_SHIFT 16 +#define QCOM_MDT_PF_ASID_MASK (QCOM_MDT_ASID_MASK << QCOM_MDT_PF_ASID_SHIFT) +#define QCOM_MDT_PF_ASID(x) \ + (((x) >> QCOM_MDT_PF_ASID_SHIFT) & QCOM_MDT_ASID_MASK) struct device; struct firmware; @@ -27,6 +32,10 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); +int qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *firmware, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base); void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, const char *fw_name, struct device *dev); @@ -62,6 +71,16 @@ static inline int qcom_mdt_load_no_init(struct device *dev, return -ENODEV; } +static inline int qcom_mdt_load_pd_seg(struct device *dev, + const struct firmware *fw, + const char *fw_name, int pas_id, + void *mem_region, phys_addr_t mem_phys, + size_t mem_size, + phys_addr_t *reloc_base) +{ + return -ENODEV; +} + static inline void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, const char *fw_name, struct device *dev) From patchwork Tue Mar 7 04:41:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 659996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8EBCC678D5 for ; Tue, 7 Mar 2023 04:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230271AbjCGEoK (ORCPT ); Mon, 6 Mar 2023 23:44:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbjCGEn4 (ORCPT ); Mon, 6 Mar 2023 23:43:56 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC4FD4344C; Mon, 6 Mar 2023 20:43:26 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3273ktmC020223; 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Tue, 7 Mar 2023 04:43:03 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:42:55 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 09/11] arm64: dtsi: qcom: ipq5018: enable nodes required for multipd Date: Tue, 7 Mar 2023 10:11:35 +0530 Message-ID: <1678164097-13247-10-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: d15xTPv3UfwuBtOMlPu1eInsqlpyi_09 X-Proofpoint-ORIG-GUID: d15xTPv3UfwuBtOMlPu1eInsqlpyi_09 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=841 lowpriorityscore=0 suspectscore=0 mlxscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable nodes required for multipd remoteproc bring up Signed-off-by: Manikanta Mylavarapu --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 130 ++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 084fb7b30dfd..4fa0990ab543 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -95,6 +95,24 @@ tz: tz@4ac00000 { reg = <0x0 0x4ac00000 0x0 0x00400000>; no-map; }; + + q6_region: wcnss@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x01700000>; + }; + + smem@4ab00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; + }; }; timer { @@ -105,6 +123,30 @@ timer { ; }; + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; @@ -217,5 +259,93 @@ frame@b128000 { status = "disabled"; }; }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x8000>; + #hwlock-cells = <1>; + }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + #mbox-cells = <1>; + }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq5018-q6-mpd"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0cd00000 0x4040>; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + q6_wcss_pd1: remoteproc_pd1 { + compatible = "qcom,ipq5018-wcss-ahb-mpd"; + }; + + q6_wcss_pd2: remoteproc_pd2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + + q6_wcss_pd3: remoteproc_pd3 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + }; }; }; From patchwork Tue Mar 7 04:41:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 660627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0725C6FD1B for ; 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Tue, 07 Mar 2023 04:43:11 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3274hBhk001297 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Mar 2023 04:43:11 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:43:03 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 10/11] arm64: dts: qcom: ipq5018: Add MP03.5-c1 board support Date: Tue, 7 Mar 2023 10:11:36 +0530 Message-ID: <1678164097-13247-11-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rRJWM63lxOYuyoqSDftPibPW5n_HN8jd X-Proofpoint-GUID: rRJWM63lxOYuyoqSDftPibPW5n_HN8jd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add initial device tree support for the MP03.5-C1 board. Signed-off-by: Manikanta Mylavarapu --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-mp03.5-c1.dts | 64 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.5-c1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b77a95e97a56..10d1eafe57e4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.5-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.5-c1.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.5-c1.dts new file mode 100644 index 000000000000..51ddd7367ac6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.5-c1.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 CP01 board device tree source + * + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.5-C1"; + compatible = "qcom,ipq5018-mp03.5-c1", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + bootargs = "console=ttyMSM0,115200,n8 rw init=/init swiotlb=1 coherent_pool=2M"; + stdout-path = "serial0:115200n8"; + }; +}; + +&tlmm { + blsp0_uart_pins: uart_pins { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; + bias-disable; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&blsp0_uart_pins>; + pinctrl-names = "default"; + status = "ok"; +}; + +&q6v5_wcss { + q6_wcss_pd1: remoteproc_pd1 { + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + q6_wcss_pd2: remoteproc_pd2 { + status = "okay"; + }; + + q6_wcss_pd3: remoteproc_pd3 { + status = "okay"; + }; +}; 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Tue, 7 Mar 2023 04:43:18 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 6 Mar 2023 20:43:11 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 11/11] arm64: dtsi: qcom: ipq9574: Add nodes to bring up multipd Date: Tue, 7 Mar 2023 10:11:37 +0530 Message-ID: <1678164097-13247-12-git-send-email-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> References: <1678164097-13247-1-git-send-email-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qPS7C2bFnGGR52C9N5WSF0b_6SJO9qhe X-Proofpoint-ORIG-GUID: qPS7C2bFnGGR52C9N5WSF0b_6SJO9qhe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-06_14,2023-03-06_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=666 lowpriorityscore=0 suspectscore=0 mlxscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303070041 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable nodes required for multipd remoteproc bring up. Signed-off-by: Manikanta Mylavarapu --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 145 ++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2bb4053641da..e0645bc39db4 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -201,6 +201,11 @@ tz_region: tz@4a600000 { no-map; }; + q6_region: wcnss@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x02b00000>; + no-map; + }; + smem@4aa00000 { compatible = "qcom,smem"; reg = <0x0 0x4aa00000 0x0 0x00100000>; @@ -209,6 +214,30 @@ smem@4aa00000 { }; }; + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -829,6 +858,122 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ msi-parent = <&v2m0>; status = "disabled"; }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq9574-q6-mpd"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0cd00000 0x4040>; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_ANOC_WCSS_AXI_M_CLK>, + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6SS_BOOT_CLK>, + <&gcc GCC_WCSS_DBG_IFC_APB_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_ATB_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_NTS_BDG_CLK>, + <&gcc GCC_WCSS_DBG_IFC_APB_CLK>, + <&gcc GCC_WCSS_DBG_IFC_ATB_CLK>, + <&gcc GCC_WCSS_DBG_IFC_DAPBUS_CLK>, + <&gcc GCC_WCSS_DBG_IFC_NTS_CLK>, + <&gcc GCC_Q6_TSCTR_1TO2_CLK>, + <&gcc GCC_Q6SS_ATBM_CLK>, + <&gcc GCC_Q6SS_PCLKDBG_CLK>, + <&gcc GCC_Q6SS_TRIG_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>, + <&gcc GCC_WCSS_Q6_TBU_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>; + + clock-names = "anoc_wcss_axi_m", + "wcss_ahb_s", + "wcss_ecahb", + "wcss_acmt", + "wcss_axi_m", + "q6_axim", + "q6_axim2", + "q6_ahb", + "q6_ahb_s", + "q6ss_boot", + "dbg-apb-bdg", + "dbg-atb-bdg", + "dbg-dapbus-bdg", + "dbg-nts-bdg", + "dbg-apb", + "dbg-atb", + "dbg-dapbus", + "dbg-nts", + "q6_tsctr_1to2_clk", + "q6ss_atbm_clk", + "q6ss_pclkdbg_clk", + "q6ss_trig_clk", + "mem_noc_q6_axi", + "wcss_q6_tbu", + "sys_noc_wcss_ahb"; + + assigned-clocks = <&gcc GCC_ANOC_WCSS_AXI_M_CLK>, + <&gcc GCC_WCSS_AHB_S_CLK>, + <&gcc GCC_WCSS_ECAHB_CLK>, + <&gcc GCC_WCSS_ACMT_CLK>, + <&gcc GCC_WCSS_AXI_M_CLK>, + <&gcc GCC_Q6_AXIM_CLK>, + <&gcc GCC_Q6_AXIM2_CLK>, + <&gcc GCC_Q6_AHB_CLK>, + <&gcc GCC_Q6_AHB_S_CLK>, + <&gcc GCC_Q6SS_BOOT_CLK>, + <&gcc GCC_MEM_NOC_Q6_AXI_CLK>, + <&gcc GCC_WCSS_Q6_TBU_CLK>, + <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>; + + assigned-clock-rates = <266666667>, + <133333333>, + <133333333>, + <133333333>, + <266666667>, + <533000000>, + <342857143>, + <133333333>, + <133333333>, + <342857143>, + <533000000>, + <533000000>, + <133333333>; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + q6_wcss_pd1: remoteproc_pd1 { + compatible = "qcom,ipq9574-wcss-ahb-mpd"; + }; + }; }; rpm-glink {