From patchwork Thu May 30 09:11:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 165401 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp701925ili; Thu, 30 May 2019 02:11:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqxS0pLylDdQas8uSozRZSB6/GL9ujJQdbQ5TFjjJuqYu+ghsxPw2ZBeJyE+b9o8tindJgyJ X-Received: by 2002:a17:902:403:: with SMTP id 3mr2784720ple.66.1559207512267; Thu, 30 May 2019 02:11:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559207512; cv=none; d=google.com; s=arc-20160816; b=zZWEn6mWSiz5RVP2YVrY1P312SJ55N9d82CRDqO57/nbaklCujUU2DDjexNyD2rS9N n8BY027TfRQNtuRA/GI9iJ4tfp3s7gPFw2sXubFux0wwJBzd6OxvqTclDlGwDM2mRhp4 ToJDIju1LEoeArxqFvSk1rulhIZ3pYeWAOAfjFgvY4r7DbugCFHduYSzvt3vkIJ+fZJO KB4yF74kZJavUpPgfp3Y7v4Dwz1nTKcfPS2xocPjr0LXAu3T8NEtezoyKOxkN2i1cvDD rmJFbtWuE3oPmvl7XByFOqHTEAOfUMkAywrkbwJbu7OUODqtclPRlZWvYQ+5YQ6zCMhs xhpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=dKt0iuaTxML+nt0o//xPbPNWm1XgMBDX83RDLylOoYc=; b=Rs3m4y5iZLzpVS8YLe2hyCxaK403OceseMRdkWVD8oZqGVJ8vwS2VG1hyZmS1NCYwy S7nDzz2A2pzLIHWdE8ik8ZZetmOzE+MuTLdDXt/z26yeKVG5lFnNeeNcAVc5uN9yAje0 ve4w7VeT5Al9B8Ic/45LS+egqlZpYrQpvCe2/hCuxdV647L1vHYFBz2NOSXuQwRcAiou ZH45p5frTXkmZPN3IPFUykNm/GM1d5HXnnQNhGV0phW0z3iKc9JFzGO9pG7WGAwP5Nym Sb2uzz3B3Yf9Xjre5E45lEyHULdk8pQRGRYENDheafyvtjT2otJWrUdj+m3Lkd5mreyx iY+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g75si1873482pje.45.2019.05.30.02.11.52; Thu, 30 May 2019 02:11:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727123AbfE3JLv (ORCPT + 7 others); Thu, 30 May 2019 05:11:51 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:32796 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725913AbfE3JLv (ORCPT ); Thu, 30 May 2019 05:11:51 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C54C4A78; Thu, 30 May 2019 02:11:50 -0700 (PDT) Received: from usa.arm.com (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9125D3F59C; Thu, 30 May 2019 02:11:49 -0700 (PDT) From: Sudeep Holla To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Sudeep Holla , Liviu Dudau , Linus Walleij , Lorenzo Pieralisi Subject: [PATCH] arm: dts: vexpress-v2p-ca15_a7: disable NOR flash node by default Date: Thu, 30 May 2019 10:11:39 +0100 Message-Id: <20190530091139.11643-1-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Accessing the NOR flash memory from the kernel will disrupt CPU sleep/ idles states and CPU hotplugging. We need to disable this DT node by default. Setups that want to access the flash can modify this entry to enable the flash again but also ensuring to disable CPU idle states and CPU hotplug. The platform firmware assumes the flash is always in read mode while Linux kernel driver leaves NOR flash in "read id" mode after initialization. If it gets used actively, it can be in some other state. So far we had not seen this issue as the NOR flash drivers in kernel were not enabled by default. However it was enable in multi_v7 config by Commit 5f068190cc10 ("ARM: multi_v7_defconfig: Enable support for CFI NOR FLASH") So, let's mark the NOR flash disabled so that the platform can boot again. This based on: Commit 980bbff018f6 ("ARM64: juno: disable NOR flash node by default") Cc: Liviu Dudau Cc: Linus Walleij Cc: Lorenzo Pieralisi Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Linus Walleij diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index d3963e9eaf48..1b5bc536c547 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -30,7 +30,7 @@ #interrupt-cells = <1>; ranges; - flash@0,00000000 { + nor_flash: flash@0,00000000 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 164c904c9992..1de0a658adf1 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -680,3 +680,12 @@ <0 3 &gic 0 39 4>; }; }; + +&nor_flash { + /* + * Unfortunately, accessing the flash disturbs the CPU idle states + * (suspend) and CPU hotplug of this platform. For this reason, flash + * hardware access is disabled by default on this platform alone. + */ + status = "disabled"; +};