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Tue, 18 Apr 2023 04:35:33 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr 2023 04:35:32 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Tue, 18 Apr 2023 04:35:28 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 1/6] cpufreq: use correct unit when verify cur freq Date: Tue, 18 Apr 2023 17:04:54 +0530 Message-ID: <20230418113459.12860-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT007:EE_|DS7PR12MB8323:EE_ X-MS-Office365-Filtering-Correlation-Id: 8705403d-37c3-4767-d523-08db400107b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199021)(40470700004)(46966006)(36840700001)(356005)(82740400003)(7696005)(7636003)(34020700004)(6666004)(40460700003)(110136005)(54906003)(2906002)(478600001)(40480700001)(83380400001)(426003)(336012)(47076005)(107886003)(186003)(2616005)(26005)(82310400005)(36860700001)(36756003)(4326008)(5660300002)(70586007)(316002)(7416002)(15650500001)(1076003)(70206006)(86362001)(41300700001)(8676002)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:35:36.9684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8705403d-37c3-4767-d523-08db400107b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8323 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Sanjay Chandrashekara cpufreq_verify_current_freq checks if the frequency returned by the hardware has a slight delta with the valid frequency value last set and returns "policy->cur" if the delta is within "1 MHz". In the comparison, "policy->cur" is in "kHz" but it's compared against HZ_PER_MHZ. So, the comparison range becomes "1 GHz". Fix this by comparing against KHZ_PER_MHZ instead of HZ_PER_MHZ. Fixes: f55ae08c8987 ("cpufreq: Avoid unnecessary frequency updates due to mismatch") Signed-off-by: Sanjay Chandrashekara [ sumit gupta: Commit message update ] Signed-off-by: Sumit Gupta --- drivers/cpufreq/cpufreq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 8b0509f89f1b..6b52ebe5a890 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1732,7 +1732,7 @@ static unsigned int cpufreq_verify_current_freq(struct cpufreq_policy *policy, b * MHz. In such cases it is better to avoid getting into * unnecessary frequency updates. */ - if (abs(policy->cur - new_freq) < HZ_PER_MHZ) + if (abs(policy->cur - new_freq) < KHZ_PER_MHZ) return policy->cur; cpufreq_out_of_sync(policy, new_freq); From patchwork Tue Apr 18 11:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 674938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C29EC77B78 for ; Tue, 18 Apr 2023 11:35:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbjDRLfz (ORCPT ); Tue, 18 Apr 2023 07:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229627AbjDRLfy (ORCPT ); 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Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 022e3555407c..15c2cbb7a50e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -43,10 +43,13 @@ static LIST_HEAD(cpu_data_list); static bool boost_supported; +static void cppc_check_hisi_workaround(void); + struct cppc_workaround_oem_info { char oem_id[ACPI_OEM_ID_SIZE + 1]; char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; u32 oem_revision; + void (*apply_wa_func)(void); }; static struct cppc_workaround_oem_info wa_info[] = { @@ -54,10 +57,12 @@ static struct cppc_workaround_oem_info wa_info[] = { .oem_id = "HISI ", .oem_table_id = "HIP07 ", .oem_revision = 0, + .apply_wa_func = cppc_check_hisi_workaround, }, { .oem_id = "HISI ", .oem_table_id = "HIP08 ", .oem_revision = 0, + .apply_wa_func = cppc_check_hisi_workaround, } }; @@ -938,6 +943,13 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) } static void cppc_check_hisi_workaround(void) +{ + /* Overwrite the get() callback */ + cppc_cpufreq_driver.get = hisi_cppc_cpufreq_get_rate; + fie_disabled = FIE_DISABLED; +} + +static void cppc_apply_workarounds(void) { struct acpi_table_header *tbl; acpi_status status = AE_OK; @@ -951,9 +963,8 @@ static void cppc_check_hisi_workaround(void) if (!memcmp(wa_info[i].oem_id, tbl->oem_id, ACPI_OEM_ID_SIZE) && !memcmp(wa_info[i].oem_table_id, tbl->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && wa_info[i].oem_revision == tbl->oem_revision) { - /* Overwrite the get() callback */ - cppc_cpufreq_driver.get = hisi_cppc_cpufreq_get_rate; - fie_disabled = FIE_DISABLED; + /* call work around function which matched from the table */ + wa_info[i].apply_wa_func(); break; } } @@ -968,7 +979,7 @@ static int __init cppc_cpufreq_init(void) if (!acpi_cpc_valid()) return -ENODEV; - cppc_check_hisi_workaround(); + cppc_apply_workarounds(); cppc_freq_invariance_init(); populate_efficiency_class(); From patchwork Tue Apr 18 11:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 675534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48F31C77B76 for ; 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Tue, 18 Apr 2023 04:35:48 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 3/6] irqchip/gicv3: Export arm_smccc_get_soc_id_xx funcs Date: Tue, 18 Apr 2023 17:04:56 +0530 Message-ID: <20230418113459.12860-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|DS0PR12MB7677:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f8ab61c-bcb5-4082-8f5c-08db400118f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uAxee32bW8mTzQtRktY3rVzZLGKRQDTL8RTKxlyOMqZtZWpwQuAn0iu1rIiRc+rF4P8chJESto3dGr+8rXuF3UaZceuDnwopJqvD0DeteaaBu7iLxZ0hHLr69wzul+ejhYm2jpycfqqwy58IWeBrYopl1avq91FYFkce+Lqz1c2jbdOv8LzDw2ee54CquldtHstTG0R+GdOqQOHhHtwDk+RegcArdng3EDbHcaoZCVPlNXtxkoRma0I8KmxwdChf/OV0/EEIVUTqfKzCTa4T0TNQvEcekiGZRJA/drspTmnukntYfNfX5wmhrcJzANES4wTamyfWPM8rTTkJnImSZ5T7xU+tpUeL2MzOfsqIPrgxFmLFQap/5/ZEbxfd3bpDBIuY9ecLZUfP7Skzru5U8Aq3ZlX301VuHjOQ1ENOX7ET6DqpM3HsNWNnt+x+JVpKRGFLTuAP4SOCYRVFzAM/CFtoOzwEpQF527esyhTFux2/Cml6VATOcfWRxIMHCbrsPp8Z4q0nPnks7wolYwAJf6LGTJyPLtZHGw34m1y/kpF3pOcm+VpqKWVNO2ghpuFw+huI5iNTHEfxtypTGKpiBNCVydfDBoqpXUm6G9BiCRgEPijywOicmi/839B5LRIhiLbfybL/TaKI0EUdMsBGdxLX0R1kLYKQudKAl6Aqn70ZfQKe4NYBXvV+OgKww9/RSxl4xu1b4JoNLW8LbAZp8Km0Cy2VXGBBpMcipvgDa4uQjVBNEIDspP0j0g9GqG5sgEAPGTbGpqZpNSiIUHi95HcPg+Vmg3PTRaxy+gliLMI= X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Also, exporting arm_smccc_get_soc_id_revision() function as it might be needed in future. Signed-off-by: Sumit Gupta --- drivers/firmware/smccc/smccc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c index db818f9dcb8e..b4224da46988 100644 --- a/drivers/firmware/smccc/smccc.c +++ b/drivers/firmware/smccc/smccc.c @@ -64,11 +64,13 @@ s32 arm_smccc_get_soc_id_version(void) { return smccc_soc_id_version; } +EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_version); s32 arm_smccc_get_soc_id_revision(void) { return smccc_soc_id_revision; } +EXPORT_SYMBOL_GPL(arm_smccc_get_soc_id_revision); static int __init smccc_devices_init(void) { From patchwork Tue Apr 18 11:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 674937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 790D5C77B78 for ; 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Tue, 18 Apr 2023 04:35:55 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 4/6] cpufreq: CPPC: update sampling window for Tegra241 Date: Tue, 18 Apr 2023 17:04:57 +0530 Message-ID: <20230418113459.12860-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|IA1PR12MB8239:EE_ X-MS-Office365-Filtering-Correlation-Id: 54dba8fa-0b4a-42e6-60db-08db40011a93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sWLzIF/dyzrTctyvfFqGYEVvgHqq+rU8VXEL/gvNkUDM1zYvB/K5q+WB1048aHyLxX/GFNgnL1jyv2UP1D5S1x86aK0FRWOiCRSYXUR1MSphhTW74Zdxu/PlRR8Z5TdqlwcXt0MBYGCvctR2cDLH3iM95u0jzPHtOWH2ynzk8YsQ0rqvBtLvhDpGuhhZV7K2zul1hKSIH/ZDMlbkrZQUGxThNjG2nSQ0t0Vixv3FuhI3OS3DsKurLSLK60AX++7GmeoIynlpoReE7KeFQf1283+e8Hfnt3Pvh6cyp811sEPFbbtxgVz+uFVFRtbqKT/jR44D5N4mICeoUFjgxfF32SxRwCIT+ZlL57krFthKdt/cFho56QJHlG3H7xu8P0oBpHosMDInAoTCc5xNVJlTzOyJvR1zwkW7DVZqKXwMP/LD5Lt/0oKeBZPb5TGm2QjZLyVv1uqCtt3Er93Ulj6Z8zYv6d/9OyspvBwnir+QocwDoLpP1bZ/A8UK1gvucD/MRh0AIGLfuP1z42AoqKrCUqzlJaNg92hVNXvzJugHw8yhP0ze/rH6wBqAEw1+TKGgg1DrcoUH7eS7YMJ5w+gVfn81v1054465mJCglw1TSXfN8Oaf53wDM9VYJ0kj+pRISJwmgvrb5+l909L+kVXjeiGMGsgOaPX2wC4qIKvqFmUNCMoOBRe6ooe8eH2lIyWwsu9WRIPRhgEhZfUR5DYqjp7oeqiRTEaLbtmqTEuauX3UCp/HXwrdvYB6QP7lrfAOGIEKGOtpTxcwoogSO3B4kHkHLmT/AUu9wEraRQ0i9Mk= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199021)(36840700001)(46966006)(40470700004)(36756003)(54906003)(110136005)(4326008)(316002)(70586007)(70206006)(478600001)(7696005)(40480700001)(82310400005)(8936002)(8676002)(5660300002)(41300700001)(2906002)(7416002)(82740400003)(34020700004)(356005)(86362001)(7636003)(426003)(336012)(2616005)(1076003)(26005)(107886003)(186003)(40460700003)(36860700001)(47076005)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:08.6037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54dba8fa-0b4a-42e6-60db-08db40011a93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8239 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In Tegra241, the Activity Monitor Unit's (AMU) constant counter (i.e. reference clock counter) increment happens in bursts and not incremented in the steps of one. For example reference counter may increment by '0x20' every '32' periods of ARM periphclk. This quantization of the reference counter is a source of error when reconstructing the frequency from the AMU counter data. To fix, increase the observation time interval so the error percentage becomes less. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 15c2cbb7a50e..5e6a132a525e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -43,12 +43,17 @@ static LIST_HEAD(cpu_data_list); static bool boost_supported; +/* default 2usec delay between sampling */ +static unsigned int sampling_delay_us = 2; + static void cppc_check_hisi_workaround(void); +static void cppc_nvidia_workaround(void); struct cppc_workaround_oem_info { char oem_id[ACPI_OEM_ID_SIZE + 1]; char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; u32 oem_revision; + u32 smcc_soc_id; void (*apply_wa_func)(void); }; @@ -63,6 +68,10 @@ static struct cppc_workaround_oem_info wa_info[] = { .oem_table_id = "HIP08 ", .oem_revision = 0, .apply_wa_func = cppc_check_hisi_workaround, + }, { + .oem_id = "NVIDIA", + .smcc_soc_id = 0x036b0241, /* JEP106 code for NVIDIA T241 chip (036b:0241) */ + .apply_wa_func = cppc_nvidia_workaround, } }; @@ -856,7 +865,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) if (ret) return ret; - udelay(2); /* 2usec delay between sampling */ + udelay(sampling_delay_us); ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1); if (ret) @@ -942,6 +951,11 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) return cppc_cpufreq_perf_to_khz(cpu_data, desired_perf); } +static void cppc_nvidia_workaround(void) +{ + sampling_delay_us = 25; +} + static void cppc_check_hisi_workaround(void) { /* Overwrite the get() callback */ @@ -953,8 +967,21 @@ static void cppc_apply_workarounds(void) { struct acpi_table_header *tbl; acpi_status status = AE_OK; + s32 soc_id; int i; +#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY + for (i = 0; i < ARRAY_SIZE(wa_info); i++) { + if (wa_info[i].smcc_soc_id) { + soc_id = arm_smccc_get_soc_id_version(); + if (wa_info[i].smcc_soc_id == soc_id) { + wa_info[i].apply_wa_func(); + return; + } + } + } +#endif + status = acpi_get_table(ACPI_SIG_PCCT, 0, &tbl); if (ACPI_FAILURE(status) || !tbl) return; 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Tue, 18 Apr 2023 04:36:12 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr 2023 04:36:11 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Tue, 18 Apr 2023 04:36:07 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 5/6] arm64: cpufeature: Export get_cpu_with_amu_feat func Date: Tue, 18 Apr 2023 17:04:58 +0530 Message-ID: <20230418113459.12860-6-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|PH8PR12MB6914:EE_ X-MS-Office365-Filtering-Correlation-Id: 1831378e-dd9b-4a39-b9e7-08db40011df0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199021)(46966006)(36840700001)(40470700004)(36756003)(4326008)(110136005)(54906003)(316002)(70586007)(70206006)(7696005)(478600001)(6666004)(41300700001)(5660300002)(82310400005)(8676002)(8936002)(40480700001)(2906002)(7416002)(4744005)(34020700004)(82740400003)(86362001)(356005)(426003)(2616005)(336012)(107886003)(40460700003)(1076003)(26005)(186003)(36860700001)(47076005)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:14.3267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1831378e-dd9b-4a39-b9e7-08db40011df0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6914 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Export the get_cpu_with_amu_feat() function for use by "cppc_cpufreq" to check if any CPU implements ARM's Activity Monitor Unit (AMU). If AMU is available, then for re-constructing the current CPU freq from its counters, queue work on target CPU to read the counters in a single call instead of reading them in separate smp calls. Signed-off-by: Sumit Gupta --- arch/arm64/kernel/cpufeature.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d9345e9c0226..ec31da7043eb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1917,6 +1917,7 @@ int get_cpu_with_amu_feat(void) { return cpumask_any(&amu_cpus); } +EXPORT_SYMBOL_GPL(get_cpu_with_amu_feat); static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) { From patchwork Tue Apr 18 11:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 674936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64901C77B7D for ; Tue, 18 Apr 2023 11:36:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231496AbjDRLgk (ORCPT ); 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Tue, 18 Apr 2023 04:36:18 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 18 Apr 2023 04:36:18 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Tue, 18 Apr 2023 04:36:13 -0700 From: Sumit Gupta To: , , , , , , , CC: , , , , , , , , , , , Subject: [Patch 6/6] cpufreq: CPPC: use wq to read amu counters on target cpu Date: Tue, 18 Apr 2023 17:04:59 +0530 Message-ID: <20230418113459.12860-7-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230418113459.12860-1-sumitg@nvidia.com> References: <20230418113459.12860-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT098:EE_|DS7PR12MB5767:EE_ X-MS-Office365-Filtering-Correlation-Id: 9409800e-d1b8-4413-9990-08db4001233d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199021)(40470700004)(36840700001)(46966006)(2906002)(34020700004)(2616005)(36860700001)(40460700003)(478600001)(6666004)(86362001)(82310400005)(26005)(1076003)(107886003)(7696005)(186003)(36756003)(40480700001)(426003)(336012)(41300700001)(82740400003)(356005)(7636003)(54906003)(8936002)(8676002)(47076005)(110136005)(316002)(70586007)(70206006)(83380400001)(4326008)(5660300002)(7416002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 11:36:23.2191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9409800e-d1b8-4413-9990-08db4001233d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5767 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org ARM cores which implement the Activity Monitor Unit (AMU) use Functional Fixed Hardware (FFH) to map AMU counters to Delivered_Counter and Reference_Counter registers. Each sysreg is read separately with a smp_call_function_single call. So, total four IPI's are used, one per register. Due to this, the AMU's core counter and constant counter sampling can happen at a non-consistent time interval if an IPI is handled late. This results in unstable frequency value from "cpuinfo_cur_req" node sometimes. To fix, queue work on target CPU to read all counters synchronously in sequence. This helps to remove the inter-IPI latency and make sure that both the counters are sampled at a close time interval. Without this change we observed that the re-generated value of CPU Frequency from AMU counters sometimes deviates by ~25% as the counters are read at non-determenistic time. Currently, kept the change specific to Tegra241. It can be applied to other SoC's having AMU if same issue is observed. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 53 +++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 5e6a132a525e..52b93ac6225e 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -46,6 +46,8 @@ static bool boost_supported; /* default 2usec delay between sampling */ static unsigned int sampling_delay_us = 2; +static bool get_rate_use_wq; + static void cppc_check_hisi_workaround(void); static void cppc_nvidia_workaround(void); @@ -99,6 +101,12 @@ struct cppc_freq_invariance { static DEFINE_PER_CPU(struct cppc_freq_invariance, cppc_freq_inv); static struct kthread_worker *kworker_fie; +struct feedback_ctrs { + u32 cpu; + struct cppc_perf_fb_ctrs fb_ctrs_t0; + struct cppc_perf_fb_ctrs fb_ctrs_t1; +}; + static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu); static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, struct cppc_perf_fb_ctrs *fb_ctrs_t0, @@ -851,28 +859,44 @@ static int cppc_perf_from_fbctrs(struct cppc_cpudata *cpu_data, return (reference_perf * delta_delivered) / delta_reference; } +static int cppc_get_perf_ctrs_sync(void *fb_ctrs) +{ + struct feedback_ctrs *ctrs = fb_ctrs; + int ret; + + ret = cppc_get_perf_ctrs(ctrs->cpu, &(ctrs->fb_ctrs_t0)); + if (ret) + return ret; + + udelay(sampling_delay_us); + + ret = cppc_get_perf_ctrs(ctrs->cpu, &(ctrs->fb_ctrs_t1)); + if (ret) + return ret; + + return ret; +} + static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) { - struct cppc_perf_fb_ctrs fb_ctrs_t0 = {0}, fb_ctrs_t1 = {0}; struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); struct cppc_cpudata *cpu_data = policy->driver_data; + struct feedback_ctrs fb_ctrs = {0}; u64 delivered_perf; int ret; cpufreq_cpu_put(policy); + fb_ctrs.cpu = cpu; - ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t0); - if (ret) - return ret; - - udelay(sampling_delay_us); - - ret = cppc_get_perf_ctrs(cpu, &fb_ctrs_t1); + if (get_rate_use_wq) + ret = smp_call_on_cpu(cpu, cppc_get_perf_ctrs_sync, &fb_ctrs, false); + else + ret = cppc_get_perf_ctrs_sync(&fb_ctrs); if (ret) return ret; - delivered_perf = cppc_perf_from_fbctrs(cpu_data, &fb_ctrs_t0, - &fb_ctrs_t1); + delivered_perf = cppc_perf_from_fbctrs(cpu_data, &(fb_ctrs.fb_ctrs_t0), + &(fb_ctrs.fb_ctrs_t1)); return cppc_cpufreq_perf_to_khz(cpu_data, delivered_perf); } @@ -953,7 +977,16 @@ static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpu) static void cppc_nvidia_workaround(void) { + int cpu; + sampling_delay_us = 25; + +#ifdef CONFIG_ARM64_AMU_EXTN + cpu = get_cpu_with_amu_feat(); + + if (cpu < nr_cpu_ids) + get_rate_use_wq = true; +#endif } static void cppc_check_hisi_workaround(void)