From patchwork Tue Jun 4 07:19:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165705 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5474000ili; Tue, 4 Jun 2019 00:20:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzakbsNDmyKMhX7jOwgZYc5hnjVGh72ZscMDkVIyrLJ1ZKoLPHrEvlDplL25CBCMwadK/vv X-Received: by 2002:a63:a34c:: with SMTP id v12mr32579652pgn.198.1559632807947; Tue, 04 Jun 2019 00:20:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559632807; cv=none; d=google.com; s=arc-20160816; b=xTlm+wq+BI4bPVwUuDzMhPpfWEh8BYw6xA030sERVfDhEKHampvmvrgdoVHeuXfJti LqHOLjdl83iV29yVqtjIE0hc2KzPVIla0jZZtc/ANelp5QgnqX4IAl1oVwvQqcX7UhDM 1HH57AxGkNGbtSCJtkavIGLZyUe/elpMvnR2MV5sgeFBktZAynCKrzdT5LrnLBnudBlr CxvtH1KcA/QcOxh9QAkTV32tCFUt8W8pinCKxXZdxxZKxMXbk3ghVyjD7mhtiHT2dvMo v2JNDtODeRmxaXtCYOZ7U8juVUIQzdMmseccKSw/kHz8SxXAmJasbBY/qbmlpI7pHe1H KSEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ViYa7F9UtMEME21J5BQzy3vs+Cq1vhzXOpNQ8GRwj90=; b=TJ+YENIy3055k+8gYfiaQ2JjXZstvQycK/1uVR+80pM3cFGhuExEhlWehaA8Yf4+R4 LxtI2fGi3jZsLdHecWQJ0dsj+NMVsZONhIspCWfoE/zSimRaayVrQjTjgce0Y0de78kS idAZLy2v071syVx1c0w4WjAp+CvtZbBePLV0M1+b15CpcldBCo3YCkBJW3tRGpT/xEck LybdmVjslOmCuddIlKXmYoIfWe2+g+Q8QCfmz2ymlX2FoUqom+Se9D+vQ+LrdIkK9Jw8 I6ujm2VUqm6mhFD7MEnqM1Xv2lKcxbR54QnwMOmFN5G7Oafrxjk29fd41xhJCViFHNJw xW2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IQHyypeL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k29si22042385pgl.157.2019.06.04.00.20.07; Tue, 04 Jun 2019 00:20:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IQHyypeL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726862AbfFDHUH (ORCPT + 7 others); Tue, 4 Jun 2019 03:20:07 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34989 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726861AbfFDHUG (ORCPT ); Tue, 4 Jun 2019 03:20:06 -0400 Received: by mail-pf1-f195.google.com with SMTP id d126so12147937pfd.2 for ; Tue, 04 Jun 2019 00:20:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ViYa7F9UtMEME21J5BQzy3vs+Cq1vhzXOpNQ8GRwj90=; b=IQHyypeLvlM4iPMqI4K31qIccqyDXJUNAkUxaVhwli/2GjylIzF6dAawwqwChEpKAy aaIKSnnA4n1FcjHAefxCe1pHccyedHAO8oXGSu8TWcR4F7rdgAWWgfh6SL68CEVAZHEv Pp9dp0tsP/1Z8C7VLNUOy9xy5En5PaGeNIKDrpW/8sBu5ARxEBLxLSXkMlkk2WGmrOM/ dLEUx4SM/+JAjA6Konl0hOJ4xF+4x1Da+dMN95qPZL+CjTbTd+DAKjYgtNdbVRZdCvtR lAR9K2wXfF7DIWiapg1VyBBCVFcJ1kUI68o0j99J1vfebfnVlxDaUu46CRCBEiCYLVoc BF5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ViYa7F9UtMEME21J5BQzy3vs+Cq1vhzXOpNQ8GRwj90=; b=JNa+9PHNRC3asttRMcRHEJeMk32K1g6I0bOQIc93unkjRUqF3+3JoADvoFPneWCvJe a4zwILGmDZkiWTMdpeeThQ1pEE0ijHg3FsHqozWJkwg+BKhuOjMZwAkDSiU6nMn+/BbQ gHLjRnrINuORoHL7+R3DIVOfXPQTD0eWOX2aQjuZ0LucZb43H0gqTay+AnvABaB+tIIf AP4mNfFPnhXXGzXHx5+qNf05GyyH2dWVrKHmuEAeO5B5qMti4AxZYAqU1BKOb0SkBUMX x6xV+S6Yst2wbSCAY4x6xXro1447t4NSc94uTJoquB1QK5hy8MPJGRzWbU2dnXDWSDC1 PBpg== X-Gm-Message-State: APjAAAU95GviKXq4Ap6kMM38uDbxzDdIzqiralxIPWC8S9EEYa9YPogR 4Bh+eALOQN00z9G0pUMq3m8QtqT8rqs= X-Received: by 2002:a17:90a:2648:: with SMTP id l66mr6801082pje.65.1559632805532; Tue, 04 Jun 2019 00:20:05 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id d6sm17747446pgv.4.2019.06.04.00.20.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jun 2019 00:20:05 -0700 (PDT) From: Bjorn Andersson To: Linus Walleij , Rob Herring Cc: Andy Gross , Mark Rutland , Pedro Sousa , "James E.J. Bottomley" , "Martin K. Petersen" , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH 1/3] pinctrl: qcom: sdm845: Expose ufs_reset as gpio Date: Tue, 4 Jun 2019 00:19:59 -0700 Message-Id: <20190604072001.9288-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190604072001.9288-1-bjorn.andersson@linaro.org> References: <20190604072001.9288-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pinr Reorder the pins and expose it as gpio 150, so that the UFS driver can toggle it. Signed-off-by: Bjorn Andersson --- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 2 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 665aadb5ea28..33ae08aa4b89 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -79,7 +79,7 @@ to specify in a pin configuration subnode: gpio0-gpio149 Supports mux, bias and drive-strength - sdc2_clk, sdc2_cmd, sdc2_data + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset Supports bias and drive-strength - function: diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index c97f20fca5fd..e4e5acade086 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -420,10 +420,10 @@ DECLARE_MSM_GPIO_PINS(147); DECLARE_MSM_GPIO_PINS(148); DECLARE_MSM_GPIO_PINS(149); -static const unsigned int sdc2_clk_pins[] = { 150 }; -static const unsigned int sdc2_cmd_pins[] = { 151 }; -static const unsigned int sdc2_data_pins[] = { 152 }; -static const unsigned int ufs_reset_pins[] = { 153 }; +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc2_clk_pins[] = { 151 }; +static const unsigned int sdc2_cmd_pins[] = { 152 }; +static const unsigned int sdc2_data_pins[] = { 153 }; enum sdm845_functions { msm_mux_gpio, @@ -1271,10 +1271,10 @@ static const struct msm_pingroup sdm845_groups[] = { PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99f000), SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6), SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3), SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0), - UFS_RESET(ufs_reset, 0x99f000), }; static const struct msm_pinctrl_soc_data sdm845_pinctrl = { @@ -1284,7 +1284,7 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .nfunctions = ARRAY_SIZE(sdm845_functions), .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), - .ngpios = 150, + .ngpios = 151, }; static int sdm845_pinctrl_probe(struct platform_device *pdev)