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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:46 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Date: Fri, 5 May 2023 11:02:13 +1000 Message-Id: <20230505010241.21812-62-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 16 +++++++--------- target/riscv/cpu_helper.c | 33 ++++++++++++++++----------------- target/riscv/translate.c | 32 ++++++++++---------------------- 3 files changed, 33 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51d39687fe..ab64d5f92d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -644,19 +644,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 20, 2) +FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) -FIELD(TB_FLAGS, VTA, 24, 1) -FIELD(TB_FLAGS, VMA, 25, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 26, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8412ef26ee..e3e620137b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, { CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); - + RISCVExtStatus fs, vs; uint32_t flags = 0; *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; @@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #ifdef CONFIG_USER_ONLY - flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); - flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); + fs = EXT_STATUS_DIRTY; + vs = EXT_STATUS_DIRTY; #else flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags = FIELD_DP32(flags, TB_FLAGS, FS, - get_field(env->mstatus, MSTATUS_FS)); - } - if (riscv_cpu_vector_enabled(env)) { - flags = FIELD_DP32(flags, TB_FLAGS, VS, - get_field(env->mstatus, MSTATUS_VS)); - } + fs = get_field(env->mstatus, MSTATUS_FS); + vs = get_field(env->mstatus, MSTATUS_VS); if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || @@ -100,18 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, - get_field(env->mstatus_hs, MSTATUS_VS)); - flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled); + if (env->virt_enabled) { + flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } } if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif + flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 411e771e6f..3092c942ab 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -66,8 +66,6 @@ typedef struct DisasContext { uint32_t opcode; RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; - RISCVExtStatus mstatus_hs_fs; - RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -620,16 +618,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs = EXT_STATUS_DIRTY; - tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } } } #else @@ -653,16 +647,12 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs = EXT_STATUS_DIRTY; - tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } } } #else @@ -1171,8 +1161,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->cfg_ptr = &(cpu->cfg); - ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); - ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); From patchwork Fri May 5 01:02:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679284 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92699wrs; Thu, 4 May 2023 18:16:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ah8LbAOOnN5M7Ga0nN3jLXSSxF+2/eUyR/MWXov6fd8RZQHjvO4ixogYy+ygjyn28mjWc X-Received: by 2002:a05:6214:4017:b0:5ef:48c7:3f62 with SMTP id kd23-20020a056214401700b005ef48c73f62mr11352917qvb.15.1683249394553; Thu, 04 May 2023 18:16:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249394; cv=none; d=google.com; s=arc-20160816; b=QCpOTEj/snnDtKwHxP9IwX0YZd9puBMuKk8RkZ2r/qHRsQ4+xwZtUeB0ekASXIREHY /FJWe8gDULSNdeGulrPRaL9hbZUgrkwtcDksaWX8C6dl+AeOZwwLIH3ndoEIzSDpBcbA hGe7rDZKCqADSD3CQjVkISghqvsT3J4fbY24K5pvbOLMrLlUuFlSz9AL4eWtDYBfkkgK PS+iPls/zUqGBkStjrYZSNvkKfdsU7mAr5SIbGf9Ip6e5Fdp2cQQB03fhU9yOHP0TRl8 xTLgQD2zbcTfSPJg6Q0vXiIrw9Q2G27yucij08JV3a2F4LUP2CZBnEb/VYHGAZYogHOe Y7Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=APvvZooxKzMDjU/SEAU1BSPZSDT4yDNWxKxwghZLWeA=; b=XYBCu+YPQBY2e0EGSHX2WkgYzRvczxO6GLDj3P/JKTbcw1sVx+N+q8xubiwgNHmZOZ 62ELe1sf89NjSlIGLQr5tUDexsiT6Q88auFkEXL4/YSWYoSYM1W6OD/mhFJB4oC0oK73 aXSgwTUoDHGVSE2dYZoFMUsrxXhOVsT3Echw8XNkyWyYJ05roCnqrEieG+Fktlgsz640 7S2n9eRwaH1k5u11ZrflM4Q++KFmqY9h6do9sWwwJEZB4daFXErNEHPonALejVhTFZWY glX6447nFjYR/4DcXlhry93OCBG+Grpg8imQzxOKWCQkPJ4XnYhgUaGdMiKL29gCbTYA /pxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=YnSPJFDi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Date: Fri, 5 May 2023 11:02:17 +1000 Message-Id: <20230505010241.21812-66-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0adfd1ca9a..49179e7a5a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } +/* + * TODO: These implementations are not quite correct. They perform the + * access using execute permission just fine, but the final PMP check + * is supposed to have read permission as well. Without replicating + * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx + * which would imply that exact check in tlb_fill. + */ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldw_code_mmu(env, address, oi, GETPC()); } target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldl_code_mmu(env, address, oi, GETPC()); } #endif /* !CONFIG_USER_ONLY */ From patchwork Fri May 5 01:02:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679291 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93244wrs; Thu, 4 May 2023 18:18:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4WyMxo25jVif80RZvbFYSyCFX9+pGsq97vrFw8gqgQK6wPxxfd+KkzcHzl7iRAawdgfn9b X-Received: by 2002:a05:622a:1786:b0:3ef:5733:29f5 with SMTP id s6-20020a05622a178600b003ef573329f5mr214829qtk.15.1683249509501; Thu, 04 May 2023 18:18:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249509; cv=none; d=google.com; s=arc-20160816; b=m/5xo1Q3SFE0yC6aQ/h4gUrP/weVgh/nByC+Hpa5y4v7xzSPW/0eDQljdzQnuoyGEF VHSLXzcmZnk7hh/hEGpK+jnEsHs8U0c21PJIbTWDGNWR/wGZzZiH3n0boXxb5Gy4r+Ui AHNciF3vMwkrO7Mv6E2gXMAFFHG2dMlwmiyWFZvMW1u4wlzKiTLQBUM4XGu0qCCMZbz7 pD0aSZHG0m0RJ4hwKKuIMpNmIlgk3REE1pegg+B5ioVTOrglA5e12bKFeOWRXcbNCEVJ rRv1uuJwyl/RyP1DuegMJadpWo4H/F6A6tIUkfGVKYY/sy79EnyCoZZ1i/GWPNdCzb41 MfcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9GsRgbG59YHzRaQ19aeOdQ0BEV/yRG7KWuiP+B9mq64=; b=eU1uwcez9N+CYXxE+TDmOo+Od4+BfOxT+vSuGQZxGd1x0i7L28RSUV+RlEF3YHvt3P 54oyr/jUKJI45Jef1guWauJhklkGl20/8Xd9nbxnvS+5IS/GZbWd8GytcYZTbh61CNRF yvnR9hFdd9yqErOYawHLiaEMV8yW0Uvo7mugYp5QQAMk35DsJ4FYEVZt6JICB6J3OWbA rhJLuMN87ug/alcFJug6rsQ/IHs3KHlTNSILh5rhvksiCmu9oHYUVpJMI0u9+XxfivHJ D1cwP7YRc05dKPB5OH8ZUht3WCRvQWZDUfdHSA2GU5IlQyGvUZsY1tosUGcx2Ao1YOvE yEKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=PLb6uwTG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Date: Fri, 5 May 2023 11:02:18 +1000 Message-Id: <20230505010241.21812-67-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 +- target/riscv/helper.h | 12 ++- target/riscv/cpu_helper.c | 26 ++--- target/riscv/op_helper.c | 99 ++++++++++++++++-- target/riscv/translate.c | 2 - target/riscv/insn_trans/trans_rvh.c.inc | 129 ++++++++++-------------- 6 files changed, 165 insertions(+), 109 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6239c99f4c..35cf2e2691 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -639,8 +639,7 @@ FIELD(TB_FLAGS, LMUL, 7, 3) FIELD(TB_FLAGS, SEW, 10, 3) FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) -/* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ @@ -652,8 +651,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) -FIELD(TB_FLAGS, PRIV, 25, 2) +FIELD(TB_FLAGS, PRIV, 24, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1880e95c50..98e97810fd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) -DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl) #endif /* Vector functions */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 174a77706b..abf275d2c6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -102,24 +102,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, fs = get_field(env->mstatus, MSTATUS_FS); vs = get_field(env->mstatus, MSTATUS_VS); - if (riscv_has_ext(env, RVH)) { - if (env->priv == PRV_M || - (env->priv == PRV_S && !env->virt_enabled) || - (env->priv == PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { - flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - if (env->virt_enabled) { - flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } + if (env->virt_enabled) { + flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 49179e7a5a..7f83395370 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,6 +427,91 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } +static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) +{ + if (env->priv == PRV_M) { + /* always allowed */ + } else if (env->virt_enabled) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); + } else if (env->priv == PRV_U && !get_field(env->hstatus, HSTATUS_HU)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + } + + return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; +} + +target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + + return cpu_ldb_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); + + return cpu_ldw_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); + + return cpu_ldl_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); + + return cpu_ldq_mmu(env, addr, oi, ra); +} + +void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); + + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); + + cpu_stw_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); + + cpu_stl_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) +{ + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, false, ra); + MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); + + cpu_stq_mmu(env, addr, val, oi, ra); +} + /* * TODO: These implementations are not quite correct. They perform the * access using execute permission just fine, but the final PMP check @@ -434,20 +519,22 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx * which would imply that exact check in tlb_fill. */ -target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) { - int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, true, ra); MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); - return cpu_ldw_code_mmu(env, address, oi, GETPC()); + return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } -target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) { - int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra = GETPC(); + int mmu_idx = check_access_hlsv(env, true, ra); MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); - return cpu_ldl_code_mmu(env, address, oi, GETPC()); + return cpu_ldl_code_mmu(env, addr, oi, ra); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d59348f0c..928da0d3f0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,6 @@ typedef struct DisasContext { bool virt_inst_excp; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool hlsx; /* vector extension */ bool vill; /* @@ -1163,7 +1162,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->cfg_ptr = &(cpu->cfg); - ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index ae98b45e5e..3e9322130f 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,158 +16,131 @@ * this program. If not, see . */ -#ifndef CONFIG_USER_ONLY -static bool check_access(DisasContext *ctx) -{ - if (!ctx->hlsx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - if (ctx->virt_enabled) { - generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); - } else { - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); - } - return false; - } +#ifdef CONFIG_USER_ONLY +#define do_hlv(ctx, a, func) false +#define do_hsv(ctx, a, func) false +#else +static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_bu(r, e, a); + tcg_gen_ext8s_tl(r, r); +} + +static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_hu(r, e, a); + tcg_gen_ext16s_tl(r, r); +} + +static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_wu(r, e, a); + tcg_gen_ext32s_tl(r, r); +} + +static bool do_hlv(DisasContext *ctx, arg_r2 *a, + void (*func)(TCGv, TCGv_env, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); + + decode_save_opc(ctx); + func(dest, cpu_env, addr); + gen_set_gpr(ctx, a->rd, dest); return true; } -#endif -static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, + void (*func)(TCGv_env, TCGv, TCGv)) { -#ifdef CONFIG_USER_ONLY - return false; -#else + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest = dest_gpr(ctx, a->rd); - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); - gen_set_gpr(ctx, a->rd, dest); - } + func(cpu_env, addr, data); return true; -#endif } +#endif /* CONFIG_USER_ONLY */ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_SB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_b); } static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESW); + return do_hlv(ctx, a, gen_helper_hyp_hlv_h); } static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_w); } static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_UB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_bu); } static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUW); -} - -static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) -{ -#ifdef CONFIG_USER_ONLY - return false; -#else - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx = ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); - } - return true; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlv_hu); } static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_SB); + return do_hsv(ctx, a, gen_helper_hyp_hsv_b); } static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESW); + return do_hsv(ctx, a, gen_helper_hyp_hsv_h); } static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESL); + return do_hsv(ctx, a, gen_helper_hyp_hsv_w); } static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_wu); } static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUQ); + return do_hlv(ctx, a, gen_helper_hyp_hlv_d); } static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TEUQ); -} - -#ifndef CONFIG_USER_ONLY -static bool do_hlvx(DisasContext *ctx, arg_r2 *a, - void (*func)(TCGv, TCGv_env, TCGv)) -{ - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest = dest_gpr(ctx, a->rd); - TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); - func(dest, cpu_env, addr); - gen_set_gpr(ctx, a->rd, dest); - } - return true; + return do_hsv(ctx, a, gen_helper_hyp_hsv_d); } -#endif static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu); } static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu); } static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) From patchwork Fri May 5 01:02:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679281 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp91979wrs; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Date: Fri, 5 May 2023 11:02:19 +1000 Message-Id: <20230505010241.21812-68-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index abf275d2c6..291a1acbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7f83395370..6122f5fbe5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) From patchwork Fri May 5 01:02:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679289 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93047wrs; Thu, 4 May 2023 18:17:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4zFRm0fi2RouyGHdYFvT7g/0tT9ZP+dWQUO9VrUOW93dyUWbNoJvjfK2lXL8r8ouq2Lpfz X-Received: by 2002:a05:6214:c47:b0:616:58f1:2844 with SMTP id r7-20020a0562140c4700b0061658f12844mr18654927qvj.45.1683249466979; Thu, 04 May 2023 18:17:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249466; cv=none; d=google.com; s=arc-20160816; b=lhAHH0jKy+ZQ/A9WrbiKKxGYMWOAlatD538q3gRkemm1XlLM8+a4xEkuzlhorcwUb+ NDUDuKLMO3vKbt7tqkLWkGVDKZv7EltNfdD2HTou+05pC+iyDR20NX6+SnK+kCqDPMA7 SMftvTAdTd8AxJDtv0tY/wg/kKpED8vtavb2kff06jPuZnC0f7ukJj2mOVCv05pht8o/ KbZmNpAlKaBFKpSRHEf8odzeAxXT3MZVtjp/yRIOWG0TBOnmknVQ1z3PUwGsxSqieyyL 1HBk5MECQB9KcG/zBFVow7UX43s6CXz43NDSrgrDh14MPH5uvbtk5PFeO7SxXYuy5d9D HWQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hnAT6rPeWHhnyQGQh4TsIFOiMxMNe6JrOBOWyeNI6yQ=; b=nEalAkukMuXvz6DKZc9CwDcclOQxBUh6jNlnENklY1PwPOR2Lx8NAyJ1XFNxO4XcdR zss9RtnFMPYdyT2m4OdE65qwKiZNrRbJjNS6TZtXWV8+MywuvR6KT9cvtzoMONORTr0+ iYcWH0p2bDv+GoMV3pj6HIw5xksBgcVooHQJKViK6e5C/2zRfuW18JeNe0O3JcAB1Ztv tYo2keCftUALCubroFNApatMZVObVbnSyV7sDTnX5c0zKQiOmkFlyoSUzI010L5xCojT cqK1ceQl3fuZR9DEUzex2BDUGJAd/gBPvcArIeed7bPgA1MCt7voSJKUyEfWxHPOMbYK tG6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=WBSIhKit; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 68/89] target/riscv: Introduce mmuidx_sum Date: Fri, 5 May 2023 11:02:20 +1000 Message-Id: <20230505010241.21812-69-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 7b63c0f1b6..0b61f337dd 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,11 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +static inline bool mmuidx_sum(int mmu_idx) +{ + return (mmu_idx & 3) == MMUIdx_S_SUM; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 291a1acbf7..29ee9b1b42 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -842,7 +842,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, widened = 2; } /* status.SUM will be ignored if execute on background */ - sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug; + sum = mmuidx_sum(mmu_idx) || use_background || is_debug; switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; From patchwork Fri May 5 01:02:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679288 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93037wrs; Thu, 4 May 2023 18:17:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6iDUuIxmqZRW0s9wAGEWU4QAtqmRqyOTFdeX79IB6Jw5eGLJOX0HmvAGBc03hPxXA1IAzS X-Received: by 2002:a05:6214:27e3:b0:5ef:4ecf:3cb0 with SMTP id jt3-20020a05621427e300b005ef4ecf3cb0mr22815458qvb.25.1683249464479; Thu, 04 May 2023 18:17:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249464; cv=none; d=google.com; s=arc-20160816; b=TVqUB0xVmG41tXx7fuESEAj6ZpPEFam5eHWP4ybao26pZv+Tnh4R9c0gY3FXg3YNDR Pe+ZrT5VOyCUJNUu7A9agozSA8huECdN3xGdI3nPV0M4aS7XClmaiUwTdY6WkIdIMGGa A+QHsDVUQak6X42De6L4urCvyiyylL6HOJd2PBv5k4yHd4oKFec1ud4eIktijqxM4yx0 K2Qeiv//jtZdUBPy1FCFJmAvYMwdn9aSJHfJaZsjvpmeSzduM0o/qbrYjrLF6GUmOLWn s5+9fviqbg3JJzOAQA2251U5KpSM6a5ZUugGxD+HcHV5a5SD/mVPOySRTJHs+X2GFIop 6UFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RGNIw9bc7Cyb4tZyzwGyzD9oYOSakGAm6uS/tG53Jdc=; b=GCte8srko/Hbc4+fofGKoynkLtdfnbd5X8IVNO24cMv5IsQ+sw1phJ3ySa2xAvuoIz CI+22+c9RaPwJ0tjM0VeNzEwY6nlfmWEH+7M9fseQ+a9H57b+/X92PX3fx2+R1S8k8pp 0C1sZKjZGh4ilrreULZvqRZ/2IzDaBZUGKWlug2qp+Z4e1M2KWEcxczIKxTVoA6qS2RW C7cbBOt+DxYJ45VdKmtbzzDp23TYc99F6wDy0U707NxLtXR35VPsQzgsOHIfve6O4CQ/ bwKqbweFvQjqxa93RxEzYbGSz126RJ0svPpz0wSZHR1DxI1g16xqf+rARnYVq8IgB5rL WWgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=GXERoG+d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:15 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 69/89] target/riscv: Introduce mmuidx_priv Date: Fri, 5 May 2023 11:02:21 +1000 Message-Id: <20230505010241.21812-70-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 9 +++++++++ target/riscv/cpu_helper.c | 6 +----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0b61f337dd..4aa1cb409f 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,15 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +static inline int mmuidx_priv(int mmu_idx) +{ + int ret = mmu_idx & 3; + if (ret == MMUIdx_S_SUM) { + ret = PRV_S; + } + return ret; +} + static inline bool mmuidx_sum(int mmu_idx) { return (mmu_idx & 3) == MMUIdx_S_SUM; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ee9b1b42..57bb19c76e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ MemTxResult res; MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; - int mode = env->priv; + int mode = mmuidx_priv(mmu_idx); bool use_background = false; hwaddr ppn; int napot_bits = 0; @@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); - } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode = get_field(env->mstatus, MSTATUS_MPP); - } } if (first_stage == false) { From patchwork Fri May 5 01:02:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679287 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92845wrs; Thu, 4 May 2023 18:17:03 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ55LNKEJVPvgodi5gGU5ilKAs/dB+gfdKCOFteHPS4FmnH8rpV8APVhVVQxOd+8GBEavFcm X-Received: by 2002:ac8:4e86:0:b0:3e8:b9a0:babf with SMTP id 6-20020ac84e86000000b003e8b9a0babfmr300930qtp.12.1683249423723; Thu, 04 May 2023 18:17:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249423; cv=none; d=google.com; s=arc-20160816; b=XAFj1pywd7zB8yxqXt3/YV2KUW4EYI50yM/kGDpIk1Atjb/YCni5HaW0xNOCWbIfEx VDrZKVl1/GjzaKg9emCuvGdwi+++tVw7JJVHgSFGdJRmXzbpdq8VzQusiKwT2Kyv9kM2 MCv+qOHg3X99DYbIdJs1rPfgQdEdfb4YN0xW2gx1L1s/kZaOLRvZN6XsVGV+THTAnrbc 7qR+AarcpBNZZN4YxN5ad4D+2zLwiasWL48Xf8hIRkEifnlvnlCkqHMXfI1cGek1Eas4 VaOjXdCLME/A5ro3FVhOryIhMm43rBblB9kGvp2SQ1kIeQ9dJLqm8BG49vzOo8WSy7un 7U1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Wi+1v00zCXgIbo5ZQUE7RzeAN6+AZmd0gp2h5NJhB9o=; b=N0GqX/CnCOuhZFD8YF8z2xOgtan9ghqyq7+JlC+b8DQ2ybgNDgw67Mv5Tthnu6Smp2 mMKhFrxDY2YdVIdmMIj6fwmUqHQo/Sga3FoysS1HusVlNE3OIQ2ZucWKlUwZEcTXZbK8 u9Omw/UJZGg/xJHS+FlveRBGMzbkoprH6GqUkrsyqL9p77yv2dUhfd3Z2NqU9LM5oaLy 683zYZDY5BZLF1SENDng9uiEk+j+GXPEyPoBDH3Zcyk/Ya+tTCS6i3qT4W5XEhc70p/k CfUeAVxSr5noMR+N4UxfQ+7LB7oKhkrKQu6ByxUwSzRPJOKk4NBwTr/Gf+ywJwkNpALY JwgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=Oeo5StD3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:18 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 70/89] target/riscv: Introduce mmuidx_2stage Date: Fri, 5 May 2023 11:02:22 +1000 Message-Id: <20230505010241.21812-71-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 20 ++++++-------------- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35cf2e2691..d1f888a790 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -581,7 +581,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 4aa1cb409f..b5f823c7ec 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx) return (mmu_idx & 3) == MMUIdx_S_SUM; } +static inline bool mmuidx_2stage(int mmu_idx) +{ + return mmu_idx & MMU_2STAGE_BIT; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57bb19c76e..9dfd1d739b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) } } -bool riscv_cpu_two_stage_lookup(int mmu_idx) -{ - return mmu_idx & MMU_2STAGE_BIT; -} - int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env = &cpu->env; @@ -779,7 +774,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); } @@ -1175,8 +1170,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } env->badaddr = addr; - env->two_stage_lookup = env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1201,8 +1195,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; - env->two_stage_lookup = env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1256,7 +1249,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { @@ -1268,7 +1261,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, pmu_tlb_fill_incr_ctr(cpu, access_type); if (env->virt_enabled || - ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + ((mmuidx_2stage(mmu_idx) || two_stage_lookup) && access_type != MMU_INST_FETCH)) { /* Two stage lookup */ ret = get_physical_address(env, &pa, &prot, address, @@ -1366,8 +1359,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx), + env->virt_enabled || mmuidx_2stage(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } From patchwork Fri May 5 01:02:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679286 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92808wrs; Thu, 4 May 2023 18:16:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5Tzx3QtfbJ531/VJ/vx4zbQC08GaIslx4zMy6OElLQlSdLqCe2wJaF5HzNBDIoTO9iQFpU X-Received: by 2002:a05:622a:510:b0:3ef:2eab:3451 with SMTP id l16-20020a05622a051000b003ef2eab3451mr9144528qtx.20.1683249413202; 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[209.51.188.17]) by mx.google.com with ESMTPS id d14-20020a05620a136e00b007485d5c4a8bsi252969qkl.411.2023.05.04.18.16.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 May 2023 18:16:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=TB8kMYmx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvH-0000kW-8B; Thu, 04 May 2023 21:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujuw-0000Hw-1n for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:26 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujut-0007lb-W6 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:25 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64115eef620so16307806b3a.1 for ; Thu, 04 May 2023 18:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248843; x=1685840843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0lZiXeB7ApdXEaksXsIhLSnMPRCJzB+5QIy3AM8RHG4=; b=TB8kMYmxMqnXINYyfwqLCwl+2DfOjA++zXtWZajsPhL68XhqOb7gmms3zwn4Ln2gCu 8/rYZzHoE3NXHesVG7P8Nt8l7iZ30ynKKUN5+knS4EtAE2V0S+wcFeCzZmHv6u+jqEZU RVJd5q1Eg8ZOzGdWZFkQCVrky3pjBFGt9/N3SzbguDI+1T8f3ysWkxmD7X07bVwrWfSP JZW8XxD2SbbesGlP0eSLtuCTAYaU7nxb2lw9nJ8u/U6SfsGuo2eAxhCJT3gkiqn3hnYZ ozRy/4+YjvsitA+8in84Xr8f/hZ3PEvnBrGPZcj1OCqdT2VIik35p5LHdmLJeqSRPhmx XF+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248843; x=1685840843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0lZiXeB7ApdXEaksXsIhLSnMPRCJzB+5QIy3AM8RHG4=; b=J8AO0uf9Lr16RA+Lo84uqRPnrHUtlu9xzA1OIzFtUGU5EO7QHd2FWyClAqRV32nOfu LnqpaUCW2E1H6Mpci7j+EsuvdrcsHqCxLjIvRE2YR+1tM+yZ6ur1n4JrLH6KC1z653uN 8tPS1hT4GE82nI1JfltUkXEKg4ZjjYYkPg81SgYhD96lotaeUvpf9dDKlFUC325eLyhF K0KNtdU8sFCBZw17CcTCv9dHF9y+kQjKqBMV39GYPP+D7lS/CVuvagfpMpIOPQup4vIS hD9Bj07tBMD6KcFqUz2CWtJ9TjbdxAIaxa5HftIZMKs1IfeYW7iYmlizz2TObIdu4LaQ 8/cw== X-Gm-Message-State: AC+VfDw3UC7GvuEnFR3K16Sam0fgCju9cefanqKcGv5/PRXMCcPk5b48 ZRk7J22EoOjTu30tMzWO76muDlW3N4TTKA== X-Received: by 2002:a17:903:2443:b0:1ab:197c:b510 with SMTP id l3-20020a170903244300b001ab197cb510mr6078789pls.31.1683248842940; Thu, 04 May 2023 18:07:22 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:22 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Date: Fri, 5 May 2023 11:02:23 +1000 Message-Id: <20230505010241.21812-72-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 10 +--------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d739b..ccba3c45e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage == false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode = get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode == PRV_M && access_type != MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6122f5fbe5..f83f7b5347 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) From patchwork Fri May 5 01:02:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679293 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93551wrs; Thu, 4 May 2023 18:19:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5RpWQ9O7ggzzmiZEBvH03TAJzCGWDp0OMHF9f8Bl1flUlIxOXoWqPTCpw1Y02daCpHuFth X-Received: by 2002:a05:622a:1048:b0:3ef:3ff5:ce28 with SMTP id f8-20020a05622a104800b003ef3ff5ce28mr191693qte.39.1683249577842; Thu, 04 May 2023 18:19:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249577; cv=none; d=google.com; s=arc-20160816; b=gQd1KV7Y9mEpqohpbYI+Q6efZb5/qbfuJYPsGEq5FSbtrjVINlFVV5DiGlGclrnrFr 49mnRAoUjne0Cw6fKrCJCmzG4zXAzn+rFnBJyT8r/qlVr3XcsBJUR+zr7gX1YSGdImVC /XhLNfW2Vd0ZCpauX7fBCKX91LCkBFKTFXtmHwKOm8TYYB8pAfx4nr5Uo09Ud/u/PpW1 /tFO8/8SBGhlHXWGdRPSotJx3Ug0mkogklNU2D6V5ewHemf9tvuN0rVgw/JrtUYUTj60 6Pj9ef1x0uGq47PJs0gTFUQoSAPyyRU+btF/HyqKR9sgR5EaAIXLA/aRP9JXOQmHvZi/ Bssw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aFHu1wXGTKi/8OHzVpdxexLxvjVZdWMnanU8CAAQbkg=; b=sgXgal6nrRcmqqJya72yqLgtZYrZgTujQ1x3AIH3BKMjJzRQfM0pWvMrsaOHhmqUl8 ISLSSdKCYwaFmK8JkkN38AZ2ZiicV7wuSA7Tsd4I9EhYDgWUlhZsIzLLEecDTVmSo4RZ 6ym++JVWOZgKv38nuEx6+kjHKPXt0MgH860Nufga/mZ9Eb5/vk9U6p3GhgjixnDE6Rd+ KltQNH4SPiDb/jmF8ZkZfzIAVyUqV8nrqeJrOkhj0jQsg0eumzbZU+HftSMJnHoqcaua INtEpNQaT/LoHKqSH2CXx75cDXnxvWY1MkoFIFOIifG+WUqAc+eBkH5SozB5WAMQeQW+ rIvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=agYuLICf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Date: Fri, 5 May 2023 11:02:24 +1000 Message-Id: <20230505010241.21812-73-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 49 ++++++++++++++------------------------- target/riscv/csr.c | 6 +---- 2 files changed, 18 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ccba3c45e7..baa4b3a1d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,19 +37,21 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else - if (ifetch) { - return env->priv; - } + bool virt = env->virt_enabled; + int mode = env->priv; /* All priv -> mmu_idx mapping are here */ - int mode = env->priv; - if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { - mode = get_field(env->mstatus, MSTATUS_MPP); - } - if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { - return MMUIdx_S_SUM; + if (!ifetch) { + if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode = get_field(env->mstatus, MSTATUS_MPP); + virt = get_field(env->mstatus, MSTATUS_MPV); + } + if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + mode = MMUIdx_S_SUM; + } } - return mode; + + return mode | (virt ? MMU_2STAGE_BIT : 0); #endif } @@ -1162,7 +1164,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, } env->badaddr = addr; - env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup = mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1187,7 +1189,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, g_assert_not_reached(); } env->badaddr = addr; - env->two_stage_lookup = env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup = mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup = false; cpu_loop_exit_restore(cs, retaddr); } @@ -1225,7 +1227,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int prot, prot2, prot_pmp; bool pmp_violation = false; bool first_stage_error = true; - bool two_stage_lookup = false; + bool two_stage_lookup = mmuidx_2stage(mmu_idx); bool two_stage_indirect_error = false; int ret = TRANSLATE_FAIL; int mode = mmu_idx; @@ -1237,24 +1239,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - ; - } else if (mode == PRV_M && access_type != MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV)) { - mode = get_field(env->mstatus, MSTATUS_MPP); - if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV)) { - two_stage_lookup = true; - } - } - pmu_tlb_fill_incr_ctr(cpu, access_type); - if (env->virt_enabled || - ((mmuidx_2stage(mmu_idx) || two_stage_lookup) && - access_type != MMU_INST_FETCH)) { + if (two_stage_lookup) { /* Two stage lookup */ ret = get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_type, @@ -1350,8 +1336,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } else { raise_mmu_exception(env, address, access_type, pmp_violation, - first_stage_error, - env->virt_enabled || mmuidx_2stage(mmu_idx), + first_stage_error, two_stage_lookup, two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4a4d852bd1..865ee9efda 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1294,7 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); /* flush tlb on mstatus fields that affect VM */ - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) { + if ((val ^ mstatus) & MSTATUS_MXR) { tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | @@ -1342,10 +1342,6 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno, uint64_t valh = (uint64_t)val << 32; uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; - if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { - tlb_flush(env_cpu(env)); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:29 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 73/89] target/riscv: Check SUM in the correct register Date: Fri, 5 May 2023 11:02:25 +1000 Message-Id: <20230505010241.21812-74-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual. However, it matches the behavior for MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++++---- target/riscv/op_helper.c | 6 +++++- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index baa4b3a1d2..38bd83f66d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -42,11 +42,16 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) /* All priv -> mmu_idx mapping are here */ if (!ifetch) { - if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + uint64_t status = env->mstatus; + + if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { mode = get_field(env->mstatus, MSTATUS_MPP); virt = get_field(env->mstatus, MSTATUS_MPV); + if (virt) { + status = env->vsstatus; + } } - if (mode == PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + if (mode == PRV_S && get_field(status, MSTATUS_SUM)) { mode = MMUIdx_S_SUM; } } @@ -826,8 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 2; } - /* status.SUM will be ignored if execute on background */ - sum = mmuidx_sum(mmu_idx) || use_background || is_debug; + sum = mmuidx_sum(mmu_idx) || is_debug; switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f83f7b5347..f563dc3981 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,11 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; + int mode = get_field(env->hstatus, HSTATUS_SPVP); + if (!x && mode == PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { + mode = MMUIdx_S_SUM; + } + return mode | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) From patchwork Fri May 5 01:02:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679285 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92799wrs; Thu, 4 May 2023 18:16:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7o6UvZvbHfraGcFJKsYDeRCs3op640inEufkZS+RJ/MqurGFKOb1r1g/AzJmXXizZCCHJf X-Received: by 2002:ac8:7f4b:0:b0:3d9:b59f:1ba9 with SMTP id g11-20020ac87f4b000000b003d9b59f1ba9mr272239qtk.12.1683249411753; Thu, 04 May 2023 18:16:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249411; cv=none; d=google.com; s=arc-20160816; b=d+yHhHbzDt4dfQVLPj/AFpK/hXfJJ2HjLIasnZvQ9xY0aEZ9Eh5viJ9qthnXldX7NJ exiIqC+72TPp9RpeZLH5Ew4pLtFfGxK6iez8skQFODEFKFhypOjwkJHabLZ13SsCtMAM EkJ26W2ZBs58+wT0iL0Q1PoCdbmB4DWpdNoBVw86XisrgogPiVGuzF6u7wmzgJEg0rQc r7xZE6lkNNpmj2ua9f8cJAwnh9lLFfCSqAb4XdXnZY9R5qz0vpgtSDP1oYaNyPKOmy2i MhbFE37N9PvJtK7GR18xZGiNA+qU0Zot7TyIdcdj5C3RKcTQnLaik2qN3KY6PHv4bn+g q5UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rNZtPPrKtoAPNdvExZgKDefGNHGLbWUnU+i+ILhcCsA=; b=1AvUlqDcR3yRtDa2yQtyEPRobA+i2/qdR5HYHJZNA9Kx0W6lifV5mmmv8WL50rTm3L Zsy6MJ1nEIeNPc7fiyD6zgMzfgBELfwNZ1BssOCOSck4bAyBuuIf3ni/aV22iL+caX78 v4bWboa4uJFtmH8KxkmLvNhC41cSJA6OkyqKg+QwMEZSjH3SKKalNmS92k3Ica4qcvwP q9kYaouTLNSrD+zdE9TNeWeb+m7EImIlPcQyyQ9kMTe6jYCwjMKRVycpD2Awx/ZLs4P2 xPcF4ZlG5vS7AS/RrOuVxgsAEK+7gBzWEoxCC9JqkMtKCrPEF4QICpMpFzIuPcLnFDcW UgOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=OpMiUtBR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:33 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 74/89] target/riscv: Hoist second stage mode change to callers Date: Fri, 5 May 2023 11:02:26 +1000 Message-Id: <20230505010241.21812-75-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 38bd83f66d..5753e4e612 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, use_background = true; } - if (first_stage == false) { - /* - * We are in stage 2 translation, this is similar to stage 1. - * Stage 2 is always taken as U-mode - */ - mode = PRV_U; - } - if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -890,7 +882,7 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret = get_physical_address(env, &vbase, &vbase_prot, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true, + MMUIdx_U, false, true, is_debug); if (vbase_ret != TRANSLATE_SUCCESS) { @@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, im_address = pa; ret = get_physical_address(env, &pa, &prot2, im_address, NULL, - access_type, mmu_idx, false, true, + access_type, MMUIdx_U, false, true, false); qemu_log_mask(CPU_LOG_MMU, From patchwork Fri May 5 01:02:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679283 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92374wrs; Thu, 4 May 2023 18:15:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4dcZfxkaqq00xBxFgjeNYmyuizoY3qW1HfdVDpjO7STaQN8S/YMLZRkLHwsgUyTN/sZe4W X-Received: by 2002:a05:622a:1826:b0:3ef:3057:62db with SMTP id t38-20020a05622a182600b003ef305762dbmr260526qtc.4.1683249320864; Thu, 04 May 2023 18:15:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249320; cv=none; d=google.com; s=arc-20160816; b=IPI9OzAN1BPNwt5DoCIfSzg6kCvwKyI03bBcxzuy+6Tx9SQXMQv6963geiGuqfpS6b Jc5k5lpkBAln/4ODhWC7w/H7hsT8n8b749CxgulKIaM217h8CvXk3BTQo+p0Uj624jM/ geSWupJ9iTuDVxhdsfhY/PVgnCWK4fCkeHYfiIqc07rar5lGJn41H9u8LCT1Ynwtrnd4 1lV88ZV40fy2A6rzt8KZIdnsEOH1qwyf9WGU07lt2lnDJlrpcl+QrE7pIP6qthGpAmHd ZgB3pPGxC76LSeJvQEwQGbAEN87HJ2dBtSrs5VJA7sGRCkdR/28efKv0NJLGKMcBSPTd QDAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kQOvu3VF8tFauxUlZuL69IHK6L45Rg+xcZox/q0Oz7g=; b=o338Fc/Tx/YNBKG73PfASiytMZzL87qpGaVT3NzcKBR3zAePuJW7CPLtp2DRQgikUp qFVYYTPnC2NP1iFXUg1hIG4fp4KULMK5oL5vhl3Q79Xk1UtRrg5jSq63yxhiMdspfFtn KU/X6rcJPEXfbPXSNo6vGcNHWwBdddIX1/WdRwv9M5WgUMDBaQBNWOTRpGxdHVZoD/Y8 36+etfd77S0zES/IzzKKH1T3izsgu1TFo3SJlNkpzFrfVJb9S1f1WZ/I6jmYS9ANAELo vdZLy2zQGWvxs7NgyuldPUgPhSLUKoZmAyiFGd3xBKgqI8ebEW6sVxNpY+NS/GR25S6M 1BUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=AMUerAx9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:36 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Date: Fri, 5 May 2023 11:02:27 +1000 Message-Id: <20230505010241.21812-76-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5753e4e612..7c9f89d4d3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -856,6 +856,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, return TRANSLATE_FAIL; } + bool pbmte = env->menvcfg & MENVCFG_PBMTE; + bool hade = env->menvcfg & MENVCFG_HADE; + + if (first_stage && two_stage && env->virt_enabled) { + pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); + hade = hade && (env->henvcfg & HENVCFG_HADE); + } + int ptshift = (levels - 1) * ptidxbits; int i; @@ -916,14 +924,6 @@ restart: return TRANSLATE_FAIL; } - bool pbmte = env->menvcfg & MENVCFG_PBMTE; - bool hade = env->menvcfg & MENVCFG_HADE; - - if (first_stage && two_stage && env->virt_enabled) { - pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade = hade && (env->henvcfg & HENVCFG_HADE); - } - if (riscv_cpu_sxl(env) == MXL_RV32) { ppn = pte >> PTE_PPN_SHIFT; } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { From patchwork Fri May 5 01:02:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679290 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93084wrs; Thu, 4 May 2023 18:17:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7i00lPrIBozDtWIg0J+EIvMlPWWqJqRRTz4Jw31ZKzxQzJ+wHol5KTobAmcyWMt6NPgAGx X-Received: by 2002:ac8:5910:0:b0:3ef:6e57:b424 with SMTP id 16-20020ac85910000000b003ef6e57b424mr130274qty.52.1683249475551; Thu, 04 May 2023 18:17:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249475; cv=none; d=google.com; s=arc-20160816; b=m4FOOg3rrP7QfaIlkc/TkPycvhmta/CvMnf72wMYWsAb7ricKdEWIyHYLEAtG5iYWf 6bH7ewzbMOawhr8TBaIfFfflkC3Peu0GyqL3ku3Qc21eZmwSTVInJRn4/Ak+zeEA3le5 qxW0BbSN9GZfaFpjraMBjc2zFlB+na+mk5fE+QSJgs4+tV0mBLkBswd1f1GrK8wlFOyA RIMXGbxeajmByjTsucwwpOi8Otfo29Q6ckRYdfh5mLd6mn0X8C0cYaGTHxywzWBtbI8m LUm+lS/kVI/NAqDHWy0wSgi1IQfgrWHUb6duFaIKCAgJXKLuheR7Q2sHSqDhBVsvqwdn HsKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1HdwrRbA/OYW6yPcUFcCFbJJAD4gHx1WdvFufjwwivA=; b=nVVdTici1fzCiQOdyWjVEJ5XBmeQsvpLxAozxCdyN/vXT+B9YVh6VTLu+5v05jfIv3 3nGqB4nn2mE5xsvvb16MM9q7ka492l1g2sDeAZqvgahG6/QywrQSJwfAORF5Xcl9PCwH JFD7aac1nTixpJHhogyrw/CqN0nlrVpF0elxpho9YnltsOf1mpZ/nN9NtwHpt4ETspQk 2G1ZeNFqMKeXkO1mN6u3F0/wKazIotwd21oLdJz8y3Li8YztiGZ5lXz93pYed/tAEEAe In9/XypfKchSePyxMD97+ySR2ajIstWaYJxtlqgq4E1T5uaHHu4cwxC+CmJuGQCiVzCv Gq9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=Wre2+t5G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:40 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 76/89] target/riscv: Move leaf pte processing out of level loop Date: Fri, 5 May 2023 11:02:28 +1000 Message-Id: <20230505010241.21812-77-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 234 ++++++++++++++++++++------------------ 1 file changed, 123 insertions(+), 111 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7c9f89d4d3..c2d083f029 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -865,6 +865,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } int ptshift = (levels - 1) * ptidxbits; + target_ulong pte; + hwaddr pte_addr; int i; #if !TCG_OVERSIZED_GUEST @@ -881,7 +883,6 @@ restart: } /* check that physical address of PTE is legal */ - hwaddr pte_addr; if (two_stage && first_stage) { int vbase_prot; @@ -913,7 +914,6 @@ restart: return TRANSLATE_PMP_FAIL; } - target_ulong pte; if (riscv_cpu_mxl(env) == MXL_RV32) { pte = address_space_ldl(cs->as, pte_addr, attrs, &res); } else { @@ -938,128 +938,140 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!pbmte && (pte & PTE_PBMT)) { - return TRANSLATE_FAIL; - } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { - /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { - return TRANSLATE_FAIL; - } - base = ppn << PGSHIFT; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ - return TRANSLATE_FAIL; - } else if ((pte & PTE_U) && ((mode != PRV_U) && - (!sum || access_type == MMU_INST_FETCH))) { - /* User PTE flags when not U mode and mstatus.SUM is not set, - or the access type is an instruction fetch */ - return TRANSLATE_FAIL; - } else if (!(pte & PTE_U) && (mode != PRV_S)) { - /* Supervisor PTE flags when not S mode */ - return TRANSLATE_FAIL; - } else if (ppn & ((1ULL << ptshift) - 1)) { - /* Misaligned PPN */ - return TRANSLATE_FAIL; - } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || - ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ + } + if (pte & (PTE_R | PTE_W | PTE_X)) { + goto leaf; + } + + /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { return TRANSLATE_FAIL; - } else { - /* if necessary, set accessed and dirty bits. */ - target_ulong updated_pte = pte | PTE_A | + } + base = ppn << PGSHIFT; + } + + /* No leaf pte at any translation level. */ + return TRANSLATE_FAIL; + + leaf: + if (ppn & ((1ULL << ptshift) - 1)) { + /* Misaligned PPN */ + return TRANSLATE_FAIL; + } + if (!pbmte && (pte & PTE_PBMT)) { + /* Reserved without Svpbmt. */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } + if ((pte & PTE_U) && + ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { + /* + * User PTE flags when not U mode and mstatus.SUM is not set, + * or the access type is an instruction fetch. + */ + return TRANSLATE_FAIL; + } + if (!(pte & PTE_U) && (mode != PRV_S)) { + /* Supervisor PTE flags when not S mode */ + return TRANSLATE_FAIL; + } + if (access_type == MMU_DATA_LOAD && + !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } + if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } + if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; + } + + /* If necessary, set accessed and dirty bits. */ + target_ulong updated_pte = pte | PTE_A | (access_type == MMU_DATA_STORE ? PTE_D : 0); - /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte != pte) { - if (!hade) { - return TRANSLATE_FAIL; - } + /* Page table updates need to be atomic with MTTCG enabled */ + if (updated_pte != pte) { + if (!hade) { + return TRANSLATE_FAIL; + } - /* - * - if accessed or dirty bits need updating, and the PTE is - * in RAM, then we do so atomically with a compare and swap. - * - if the PTE is in IO space or ROM, then it can't be updated - * and we return TRANSLATE_FAIL. - * - if the PTE changed by the time we went to update it, then - * it is no longer valid and we must re-walk the page table. - */ - MemoryRegion *mr; - hwaddr l = sizeof(target_ulong), addr1; - mr = address_space_translate(cs->as, pte_addr, &addr1, &l, - false, MEMTXATTRS_UNSPECIFIED); - if (memory_region_is_ram(mr)) { - target_ulong *pte_pa = - qemu_map_ram_ptr(mr->ram_block, addr1); + /* + * - if accessed or dirty bits need updating, and the PTE is + * in RAM, then we do so atomically with a compare and swap. + * - if the PTE is in IO space or ROM, then it can't be updated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, then + * it is no longer valid and we must re-walk the page table. + */ + MemoryRegion *mr; + hwaddr l = sizeof(target_ulong), addr1; + mr = address_space_translate(cs->as, pte_addr, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (memory_region_is_ram(mr)) { + target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa = pte = updated_pte; + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ + *pte_pa = pte = updated_pte; #else - target_ulong old_pte = - qatomic_cmpxchg(pte_pa, pte, updated_pte); - if (old_pte != pte) { - goto restart; - } else { - pte = updated_pte; - } -#endif - } else { - /* - * misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically - */ - return TRANSLATE_FAIL; - } + target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte); + if (old_pte != pte) { + goto restart; } - + pte = updated_pte; +#endif + } else { /* - * for superpage mappings, make a fake leaf PTE for the TLB's - * benefit. + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. */ - target_ulong vpn = addr >> PGSHIFT; - - if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - napot_bits = ctzl(ppn) + 1; - if ((i != (levels - 1)) || (napot_bits != 4)) { - return TRANSLATE_FAIL; - } - } + return TRANSLATE_FAIL; + } + } - napot_mask = (1 << napot_bits) - 1; - *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | - (vpn & (((target_ulong)1 << ptshift) - 1)) - ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + /* For superpage mappings, make a fake leaf PTE for the TLB's benefit. */ + target_ulong vpn = addr >> PGSHIFT; - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |= PAGE_READ; - } - if (pte & PTE_X) { - *prot |= PAGE_EXEC; - } - /* - * add write permission on stores or if the page is already dirty, - * so that we TLB miss on later writes to update the dirty bit - */ - if ((pte & PTE_W) && - (access_type == MMU_DATA_STORE || (pte & PTE_D))) { - *prot |= PAGE_WRITE; - } - return TRANSLATE_SUCCESS; + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + napot_bits = ctzl(ppn) + 1; + if ((i != (levels - 1)) || (napot_bits != 4)) { + return TRANSLATE_FAIL; } } - return TRANSLATE_FAIL; + + napot_mask = (1 << napot_bits) - 1; + *physical = (((ppn & ~napot_mask) | (vpn & napot_mask) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { + *prot |= PAGE_READ; + } + if (pte & PTE_X) { + *prot |= PAGE_EXEC; + } + /* + * Add write permission on stores or if the page is already dirty, + * so that we TLB miss on later writes to update the dirty bit. + */ + if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) { + *prot |= PAGE_WRITE; + } + return TRANSLATE_SUCCESS; } static void raise_mmu_exception(CPURISCVState *env, target_ulong address, From patchwork Fri May 5 01:02:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679280 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp91914wrs; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:44 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 77/89] target/riscv: Suppress pte update with is_debug Date: Fri, 5 May 2023 11:02:29 +1000 Message-Id: <20230505010241.21812-78-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The debugger should not modify PTE_A or PTE_D. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c2d083f029..6dc3fdf594 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1001,7 +1001,7 @@ restart: (access_type == MMU_DATA_STORE ? PTE_D : 0); /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte != pte) { + if (updated_pte != pte && !is_debug) { if (!hade) { return TRANSLATE_FAIL; } From patchwork Fri May 5 01:02:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679279 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp91878wrs; Thu, 4 May 2023 18:13:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7PW6TLja4dnp1rgs14WlRmBvuDbg+aCw/z6gUB+kK5IQ8tv4M9lNkjW8AzRdIi5EljJhvv X-Received: by 2002:ac8:5712:0:b0:3f2:1f2f:dc80 with SMTP id 18-20020ac85712000000b003f21f2fdc80mr289660qtw.9.1683249209428; Thu, 04 May 2023 18:13:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249209; cv=none; d=google.com; s=arc-20160816; b=jxjui5Pkd07CHnoRc6kq8Ic18ZTG/KW5dnliO0VG3dTWoQ/Pm8dIt5OZL+T03wotEy Ya+rp79m/xEcEHdYO4Hk7ETDTdxSWxCluHR7v7nBGR0GsFGcPbJJOwy2eGeU1d/z2j0x Simz2zWL8ui3ONYFWBkLz0yADQsQeJDAsMgU2U/XXa6nuTr1xHqvyZAcdbYexmG2DdAI xORMUmQM0MYXciZxGv8bbFB7N0GP+62/FBEKBugi9HgjUPyc5IXWcJk+8IozAQdagO+u VwJvaXZNfzsvXB1X/uoIYjEda8HETa02a43cT0C262CTNXDRPsCw3t8iTMFUD8RugTCb VHGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rrHxR+eiZh8W9v/w2e7/d7prgivlc2G2D0PUHvIbg2s=; b=0eudwz1m0tv0Vrgxwn/u1f8AZCWUCvB/DDzZmJB5+9KIccuW11ezcD5RbzJ+bMF/Sg ifLqVPQoCO+gV7O3Zxm6ayiEUq7PeLWQfAXFZwT0aii6c9MgCglmhSHnUtt3H/BrZb7F XupoCf0RfJtNpxzAOBE7+QkgPILTdrCLeUck0ggxRXnqeMNecsyrmq4N/0VZHD1FOSGJ 9GRi3H4+O7iy+eIi2kVfifDYkojVw27VTHafowqvCTbyQB3PKCK4gVxcK9GdA7Qk1pSe N5l2K8wSWSXGAISk13OMnK4y4FDGypG8b96fR3fxT+dV6rL3HsExGMLVtL1GmfG7Dx7f PK4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=EtcBpEpM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:47 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 78/89] target/riscv: Don't modify SUM with is_debug Date: Fri, 5 May 2023 11:02:30 +1000 Message-Id: <20230505010241.21812-79-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6dc3fdf594..9a2b944990 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -823,7 +823,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 2; } - sum = mmuidx_sum(mmu_idx) || is_debug; + sum = mmuidx_sum(mmu_idx); switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; From patchwork Fri May 5 01:02:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679282 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp92076wrs; Thu, 4 May 2023 18:14:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Rxu2FzvUzd4Rlhe9yvEG1yC6gnWGzEV90/xJuOgIdFIbA2l39lMJBwSC6spmS7dtjrm+x X-Received: by 2002:a05:622a:15cd:b0:3e6:3929:e9bc with SMTP id d13-20020a05622a15cd00b003e63929e9bcmr311064qty.6.1683249252219; Thu, 04 May 2023 18:14:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249252; cv=none; d=google.com; s=arc-20160816; b=Uzy5sfvy3PHWTwHaS+Mcf0EOYeaabNbpcviglGZ4HViFyOkDYhvoDmMeHOUtRGh+NJ MWanQEbHXihI3P7DzRnngbYnzWMakTX+pvV18PRbR8t5sMuDSlsTXQrx7m6iiA0ZmBrN FnXlGrkcOh2tojrit8XcK1BpdpiqO/6cZ4equCZtWOhOfSFHcu7r3Wj6NF6Rpa6abMyR 6RyNOqtWnLzABj/YRpnWp8JlbWhIaDdRN+MNHppDc+biv3mEm8GEH85qWiBJEBRRo+Gy V7CffNQwyah3puMrOqr3wdqDk/BKro0b1MM7pGFMIK8xhUVrqoQ7ifLTcGdMzoYuXEgq Gkeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ULqMf+DmHpGYNoo8G2xP3dFFiX1NCkBJ2cATdvrFXCY=; b=mAeQUym9E+tDLxjcdQjh1M5Zr9/+rieULeZiYr3nyVHe1OjPmvFtIuxgm2FYvn1SR8 iGneHDUdY4bcJcfkzKYyKTs4jSqCB3eCFmvq4KRAqp1V7ZDw2oiiNDsx6xtB/d81pVhV bRu6gRzGP80YQ9ai0eEcjjU+VwWaj/TMb//ylZI0XH0wiq+6h74xfZr3X1K2NsZgpF4V I7dWiuaGCx9oIUU780FSCZ0/uXGGqW1Ezu+onb1/4Qmnt5gJpPX+MKaE7r1hhJq7/jJR POhX1gLiy7WwawoLhDnyupayfCQBVFrRoyE0Js0ltx7XlGOMYTXEd5FFfHGjft0C6OVj 0C5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=UFpTT5t3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:50 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 79/89] target/riscv: Merge checks for reserved pte flags Date: Fri, 5 May 2023 11:02:31 +1000 Message-Id: <20230505010241.21812-80-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a2b944990..c7c384bae3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -962,14 +962,14 @@ restart: /* Reserved without Svpbmt. */ return TRANSLATE_FAIL; } - if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } - if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ + + /* Check for reserved combinations of RWX flags. */ + switch (pte & (PTE_R | PTE_W | PTE_X)) { + case PTE_W: + case PTE_W | PTE_X: return TRANSLATE_FAIL; } + if ((pte & PTE_U) && ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { /* From patchwork Fri May 5 01:02:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679278 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp91868wrs; Thu, 4 May 2023 18:13:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7NqVws9i0pW9JHcWNuFf7TkOIjzoGED/XPpiJpL5DO6lZQ+ujSXBqtbnzClyRAbh8aXAUb X-Received: by 2002:ac8:7e87:0:b0:3ef:34e1:d380 with SMTP id w7-20020ac87e87000000b003ef34e1d380mr294287qtj.11.1683249207779; Thu, 04 May 2023 18:13:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683249207; cv=none; d=google.com; s=arc-20160816; b=wB3aC2ZjPSrDt2BcyLtaiQhm1PVLucATZiKl9kHZ54tYo2oNV4+amU3mxshFPqgWQT WQf+DjmKn9c7fyw8smR7LISTVJ46YAmZQGeympXXQe4yqEtgXVhXM8dEGoq4loz9vKYk tSGy9CNTfrKAiN6gRAUSpGKtrPOG0cUOBrILslujy/WBv9xn3hSPe70OkvJv0pkXMMjU 00tQxmKclupDO0qtgxU5UAj3/ukP7YkVrhBwKSAuNFasfmcQHj7yJvu2ugkNAg0vLiV5 Svtnj2m1ApnQNmfPJsCPwYJ8BBbQ+dFiLyI/irnoWzjaQUwUjDxF5I8wd3ZbBd0bMrac jCiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X0bxKSCSa5QVRZAElH/ASf7kECM7kPPJ9uPPjJAQxQU=; b=BS3HJ9/WzL39rDBFq2O9CQZUmCaF6uyCbdttHw0CxniBaL0fLDbIEQLVztp+d/byBB lSw/x0Z0tiZ/tZWM7NWQfvtV/EVMXOr8QVJeIG2xU2jduXD1kxBulXEjhxpmxPn268EI mlpN9qNwEB1fZ0iZMG8n4yq7nGMhBNbNkqoNTpTjes4bnSTRP+NDO6rjgjIbvc9d5cdB fRga0sZ2+Rj4Bf1RKXL73iH0iMFD7DQywZbWN5TJIuLV6I6JkleIOdQ/DViWdje6vURB dGyGIURqkPXArFFCuYkAe/46Rg6v8M3JZay2b5ujYEBOGCEAAWKcP0ccr4KxZ/cDEguS ZiAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=Acozb0ky; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 80/89] target/riscv: Reorg access check in get_physical_address Date: Fri, 5 May 2023 11:02:32 +1000 Message-Id: <20230505010241.21812-81-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 69 ++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7c384bae3..7849e18554 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -747,7 +747,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, * @is_debug: Is this access from a debugger or the monitor? */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, - int *prot, vaddr addr, + int *ret_prot, vaddr addr, target_ulong *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, @@ -779,20 +779,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical = addr; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; } - *prot = 0; + *ret_prot = 0; hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, mxr, widened; - - if (first_stage == true) { - mxr = get_field(env->mstatus, MSTATUS_MXR); - } else { - mxr = get_field(env->vsstatus, MSTATUS_MXR); - } + int levels, ptidxbits, ptesize, vm, sum, widened; if (first_stage == true) { if (use_background) { @@ -835,7 +829,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, levels = 5; ptidxbits = 9; ptesize = 8; break; case VM_1_10_MBARE: *physical = addr; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; default: g_assert_not_reached(); @@ -970,6 +964,27 @@ restart: return TRANSLATE_FAIL; } + int prot = 0; + if (pte & PTE_R) { + prot |= PAGE_READ; + } + if (pte & PTE_W) { + prot |= PAGE_WRITE; + } + if (pte & PTE_X) { + bool mxr; + + if (first_stage == true) { + mxr = get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr = get_field(env->vsstatus, MSTATUS_MXR); + } + if (mxr) { + prot |= PAGE_READ; + } + prot |= PAGE_EXEC; + } + if ((pte & PTE_U) && ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { /* @@ -982,17 +997,9 @@ restart: /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; } - if (access_type == MMU_DATA_LOAD && - !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } - if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } - if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ + + if (!((prot >> access_type) & 1)) { + /* Access check failed */ return TRANSLATE_FAIL; } @@ -1057,20 +1064,16 @@ restart: (vpn & (((target_ulong)1 << ptshift) - 1)) ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |= PAGE_READ; - } - if (pte & PTE_X) { - *prot |= PAGE_EXEC; - } /* - * Add write permission on stores or if the page is already dirty, - * so that we TLB miss on later writes to update the dirty bit. + * Remove write permission unless this is a store, or the page is + * already dirty, so that we TLB miss on later writes to update + * the dirty bit. */ - if ((pte & PTE_W) && (access_type == MMU_DATA_STORE || (pte & PTE_D))) { - *prot |= PAGE_WRITE; + if (access_type != MMU_DATA_STORE && !(pte & PTE_D)) { + prot &= ~PAGE_WRITE; } + *ret_prot = prot; + return TRANSLATE_SUCCESS; } From patchwork Fri May 5 01:02:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 679292 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp93418wrs; Thu, 4 May 2023 18:19:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5G9yB44ctJcZJdgH5jEigmpCle3XNArfGMzVvhrqyyU1yH52DBy1Qkco3t6eOQ75Mm6kcn X-Received: by 2002:a05:622a:5:b0:3ef:2db1:6e75 with SMTP id x5-20020a05622a000500b003ef2db16e75mr249195qtw.24.1683249553781; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 81/89] target/riscv: Reorg sum check in get_physical_address Date: Fri, 5 May 2023 11:02:33 +1000 Message-Id: <20230505010241.21812-82-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7849e18554..32a65f8007 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -786,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *ret_prot = 0; hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, widened; + int levels, ptidxbits, ptesize, vm, widened; if (first_stage == true) { if (use_background) { @@ -817,7 +817,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } widened = 2; } - sum = mmuidx_sum(mmu_idx); + switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break; @@ -985,15 +985,15 @@ restart: prot |= PAGE_EXEC; } - if ((pte & PTE_U) && - ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) { - /* - * User PTE flags when not U mode and mstatus.SUM is not set, - * or the access type is an instruction fetch. - */ - return TRANSLATE_FAIL; - } - if (!(pte & PTE_U) && (mode != PRV_S)) { + if (pte & PTE_U) { + if (mode != PRV_U) { + if (!mmuidx_sum(mmu_idx)) { + return TRANSLATE_FAIL; + } + /* SUM allows only read+write, not execute. */ + prot &= PAGE_READ | PAGE_WRITE; + } + } else if (mode != PRV_S) { /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; }