From patchwork Thu May 18 14:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anusha Canchi X-Patchwork-Id: 683485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5194EC7EE2D for ; Thu, 18 May 2023 14:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbjEROMa (ORCPT ); Thu, 18 May 2023 10:12:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231365AbjEROM1 (ORCPT ); Thu, 18 May 2023 10:12:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97A1710EF; Thu, 18 May 2023 07:12:19 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34IBlhPe030578; Thu, 18 May 2023 14:12:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=Ut8u9ZoCNMHxI8qdNpewT+tUFHiAxopR43zWy6qRIk0=; b=O3C5GMD9wlGyhmvmDF+AJ22uFQvrKZB+67hocPXqWGiDVD4XOtxEjH6y6jw6Bxu3NDP4 wpXiFDVS7x2d8aQHVXNs596HzIbftUrgcuNXk5lF+J9hmxaLS10lA24rUCR8rLTDl6Sb aP2XZQOEfg0J8y0lAm5g+nRYDwZZiyQG1QCTVQv/kCGmV4HUeb/eUvmScN3ZoYvQE4Ku xQ5dLpV1ZKMn52D8N2ysvgX+53wSoQtJJdT8X1B3f2n7HxE0D03rnHT4bSMwQ8YWKryG dJsYzoJTxBxpSiZuqrGxz8A4Fq21BnrO+yLZOZ3TlYPB0wLTP3e9GzwtXc/ayo8ZXtAC pg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qn73uspk0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 14:12:10 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34IEC9jF025676 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 14:12:09 GMT Received: from anusha-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 18 May 2023 07:12:02 -0700 From: Anusha Rao To: , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH V3 1/4] dt-bindings: clock: Add crypto clock and reset definitions Date: Thu, 18 May 2023 19:41:02 +0530 Message-ID: <20230518141105.24741-2-quic_anusha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518141105.24741-1-quic_anusha@quicinc.com> References: <20230518141105.24741-1-quic_anusha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: T0bi_-K8qwj9nZl2Gulgo6aJ7rorvsJ_ X-Proofpoint-GUID: T0bi_-K8qwj9nZl2Gulgo6aJ7rorvsJ_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_11,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180113 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski Signed-off-by: Anusha Rao Reviewed-by: Bhupesh Sharma --- Changes in V3: - Added GCC prefix to CRYPTO_CLK_SRC. - Picked up Acked-by tag. include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ include/dt-bindings/reset/qcom,ipq9574-gcc.h | 1 + 2 files changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 5a2961bfe893..b32a7aa65349 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -210,4 +210,8 @@ #define GCC_SNOC_PCIE1_1LANE_S_CLK 201 #define GCC_SNOC_PCIE2_2LANE_S_CLK 202 #define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#define GCC_CRYPTO_CLK_SRC 204 +#define GCC_CRYPTO_CLK 205 +#define GCC_CRYPTO_AXI_CLK 206 +#define GCC_CRYPTO_AHB_CLK 207 #endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h index d01dc6a24cf1..c709d103673d 100644 --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -160,5 +160,6 @@ #define GCC_WCSS_Q6_BCR 151 #define GCC_WCSS_Q6_TBU_BCR 152 #define GCC_TCSR_BCR 153 +#define GCC_CRYPTO_BCR 154 #endif From patchwork Thu May 18 14:11:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anusha Canchi X-Patchwork-Id: 684055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8712CC7EE23 for ; Thu, 18 May 2023 14:12:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231678AbjEROMo (ORCPT ); Thu, 18 May 2023 10:12:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231648AbjEROMc (ORCPT ); Thu, 18 May 2023 10:12:32 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37E20172E; Thu, 18 May 2023 07:12:28 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34ID7MYt032526; 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Thu, 18 May 2023 14:12:16 GMT Received: from anusha-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 18 May 2023 07:12:09 -0700 From: Anusha Rao To: , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH V3 2/4] clk: qcom: gcc-ipq9574: Enable crypto clocks Date: Thu, 18 May 2023 19:41:03 +0530 Message-ID: <20230518141105.24741-3-quic_anusha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518141105.24741-1-quic_anusha@quicinc.com> References: <20230518141105.24741-1-quic_anusha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WJxECJ6gQlfOTSXkm7VqE4eOIw_YMuRg X-Proofpoint-GUID: WJxECJ6gQlfOTSXkm7VqE4eOIw_YMuRg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_11,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180113 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Enable the clocks required for crypto operation. Signed-off-by: Anusha Rao Reviewed-by: Bhupesh Sharma --- Changes in V3: - Added GCC prefix to CRYPTO_CLK_SRC. drivers/clk/qcom/gcc-ipq9574.c | 72 ++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 7b0505f5c255..73663168d72a 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -728,6 +728,41 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = { + F(160000000, P_GPLL0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_crypto_clk_src = { + .cmd_rcgr = 0x16004, + .freq_tbl = ftbl_gcc_crypto_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]) { + &gcc_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_apss_ahb_clk = { .halt_reg = 0x24018, .halt_check = BRANCH_HALT_VOTED, @@ -2071,6 +2106,38 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { }, }; +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16010, + .clkr = { + .enable_reg = 0x16010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16014, + .clkr = { + .enable_reg = 0x16014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nsscfg_clk = { .halt_reg = 0x1702c, .clkr = { @@ -4036,6 +4103,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr, + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { @@ -4193,6 +4264,7 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, + [GCC_CRYPTO_BCR] = { 0x16000, 0 }, }; static const struct of_device_id gcc_ipq9574_match_table[] = { From patchwork Thu May 18 14:11:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anusha Canchi X-Patchwork-Id: 683484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC9EDC7EE2C for ; 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Thu, 18 May 2023 14:12:24 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34IECM3o008443 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 14:12:22 GMT Received: from anusha-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 18 May 2023 07:12:16 -0700 From: Anusha Rao To: , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH V3 3/4] dt-bindings: qcom-qce: add SoC compatible string for ipq9574 Date: Thu, 18 May 2023 19:41:04 +0530 Message-ID: <20230518141105.24741-4-quic_anusha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518141105.24741-1-quic_anusha@quicinc.com> References: <20230518141105.24741-1-quic_anusha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6553Qc8F70EeL00N3RMhhWa-8dg3g1aO X-Proofpoint-GUID: 6553Qc8F70EeL00N3RMhhWa-8dg3g1aO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_11,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=995 malwarescore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180113 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Document the compatible string for ipq9574. Acked-by: Conor Dooley Signed-off-by: Anusha Rao Reviewed-by: Bhupesh Sharma --- Changes in V3: - Picked up Acked-by tag. Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index e375bd981300..0d1deae06e2d 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,ipq6018-qce - qcom,ipq8074-qce + - qcom,ipq9574-qce - qcom,msm8996-qce - qcom,sdm845-qce - const: qcom,ipq4019-qce From patchwork Thu May 18 14:11:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anusha Canchi X-Patchwork-Id: 684054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E57F4C7EE23 for ; Thu, 18 May 2023 14:13:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231752AbjERONK (ORCPT ); Thu, 18 May 2023 10:13:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231703AbjEROMu (ORCPT ); Thu, 18 May 2023 10:12:50 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20B6E171C; Thu, 18 May 2023 07:12:39 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34IDPjQ2030688; Thu, 18 May 2023 14:12:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=8LnI7jv3bEqP+lz6ARSZE9caJfa3XA3FReK2ep5ZFgg=; b=U9bOxex/ED+qxDPShkH4RUiFOwhCet0rH7oWAbuKewcMvuKSkoH3HNJtNvC0n3j9JBRP e+xcSoYPOm/bf9EzwsLMmabd/P4yNJzsaDVdxWOtXYEkuB64W5PBbc+ApZ2HZ02lQWAZ Eeui8qEacpifd6wT5UkEsWGNRAGoFlhy1ft0DuPBlcVG6PwwYuTBOjvD0iIfrTpIclAW nFS0pMh6LkeEuDJrhXGjZolSN1bNlzQ2HDiPe3IbIilvBl76j3p4Wv6Gzxp0+Q3s6QPL vOiIT2f9LRKu2lqmtRXQjMfUNW19gKSUu/oDtvqbAgKSYUJwt9SsQAwhypST3smNvgAL 1A== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qn73uspkt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 14:12:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34IECTlU026219 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 14:12:29 GMT Received: from anusha-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 18 May 2023 07:12:23 -0700 From: Anusha Rao To: , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH V3 4/4] arm64: dts: qcom: ipq9574: Enable crypto nodes Date: Thu, 18 May 2023 19:41:05 +0530 Message-ID: <20230518141105.24741-5-quic_anusha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518141105.24741-1-quic_anusha@quicinc.com> References: <20230518141105.24741-1-quic_anusha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ebYrIL_MKsAgVrXOjDu99Xs1ZD6jDom- X-Proofpoint-GUID: ebYrIL_MKsAgVrXOjDu99Xs1ZD6jDom- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_11,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=838 malwarescore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180113 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Enable crypto support for ipq9574. Signed-off-by: Anusha Rao Reviewed-by: Krzysztof Kozlowski --- Changes in V3: - No change. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index fea15f3cf910..6e52d35a6a15 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -123,6 +123,26 @@ clock-names = "core"; }; + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; + reg = <0x0073a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq9574-tlmm"; reg = <0x01000000 0x300000>;