From patchwork Mon Jun 12 18:24:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E15ACCA9EA0 for ; Mon, 12 Jun 2023 18:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237649AbjFLSa5 (ORCPT ); Mon, 12 Jun 2023 14:30:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237656AbjFLSYq (ORCPT ); Mon, 12 Jun 2023 14:24:46 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC7B910D8 for ; Mon, 12 Jun 2023 11:24:43 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f63a2e1c5fso5589096e87.2 for ; Mon, 12 Jun 2023 11:24:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594282; x=1689186282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SD+82Kp64qdWpl/p0nHwxIb/l/7wz0DuQnwuSSdR/H4=; b=DLAoC+YI5ihmdO8CNl1QejkU5ba9vdx06Z+NI7L/nO1cVIUcxwExm0xIpmipS22YdC GW4AlOmy/eF5P6nOW/I466ueIgqcQxJl5RDYEXdafLMUX5yUvvSWYK6WVVWF09xDY4j1 51JEQkgGY751aEhBDdmqs92WZiP4vBHHbePfmCTHrYzKO7GG6AIlpeCC90hAi5Ria4NP wq9AILrsfen14FoV0pjuxAbG+dMtoSDhp95uIhe4ej+aALqzYIqCERjSOJXpxt9RkXPK izMUxgPCghgJhMKCJ9yluUUzsmLSh4xFevPDe0myB1YI6a8RMKJavfwt8/y/hvovKaeO VMAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594282; x=1689186282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SD+82Kp64qdWpl/p0nHwxIb/l/7wz0DuQnwuSSdR/H4=; b=EeqFy3RK/NBVqxv1jjgPoKqKWpNW3WnV1O1Ab7HgDEJiBVkbI3vLCvM2FwRyqmcuYM Al2Kr4QMD+TPLhmNw6shbMgQlFDa5MNG10HHlrOyglOW7MvN7jqSxx2FFbI0NMIL8ZC9 C6Wa9Lc/q0nsuEu+mBwnypsyvXHkXiSQz0GL62BrfF+ZzyMPSCUIeyAYptP7xcA5ipkl PBa2ut1omVkRbCZD5KiubjWdEtbhTvYi8MC+dgH1Sjo68dxRFLBpUB6cR6f+H780SLY/ IlUmoHFimJy+zpf27ycWpvS5V/zHzCIE0IhW5LJnVeZdbqr+gZvOnncM347saG25RKM3 rrJw== X-Gm-Message-State: AC+VfDzq2hi65e6zDOH9U4b6jUJhfD2bYW6oNxhHs3iXeVrMZme/4j8u 9IciV/b2/OeAJN3fTAOgB3LN7g== X-Google-Smtp-Source: ACHHUZ59M0kdWHSJ7Qy0Nr6BEwWK0DdyxH9NFgW2MzdgoRX+27RfEzHBLG0l7TrgZ5h+3PncdmFzVw== X-Received: by 2002:a05:6512:459:b0:4f6:2e5f:45cc with SMTP id y25-20020a056512045900b004f62e5f45ccmr4498200lfk.3.1686594282057; Mon, 12 Jun 2023 11:24:42 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:41 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:20 +0200 Subject: [PATCH v3 03/23] soc: qcom: smd-rpm: Use tabs for defines MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-3-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=691; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=7uAPa6YDjXHLJZjqpcpTS8PIWFtwDRP9qtCSKC7URyY=; b=ESZpNbzbQ/xt/c2RmUiCpmrjQGbD9w+h5/bdbMHoNBU0InzGeWvrebWATOnYlgBtX2nGiySlm 1vFrFqFhhcGCNGEDWGrdGayN89gbDg6nnUMZG/RFoUgsXDTDqHWaTZN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use tabs for defines to make things spaced consistently. Signed-off-by: Konrad Dybcio --- include/linux/soc/qcom/smd-rpm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index e468f94fa323..99499e4b080e 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -4,8 +4,8 @@ struct qcom_smd_rpm; -#define QCOM_SMD_RPM_ACTIVE_STATE 0 -#define QCOM_SMD_RPM_SLEEP_STATE 1 +#define QCOM_SMD_RPM_ACTIVE_STATE 0 +#define QCOM_SMD_RPM_SLEEP_STATE 1 #define QCOM_SMD_RPM_STATE_NUM 2 /* From patchwork Mon Jun 12 18:24:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AA73CA9EA2 for ; Mon, 12 Jun 2023 18:31:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237550AbjFLSaz (ORCPT ); Mon, 12 Jun 2023 14:30:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237669AbjFLSYq (ORCPT ); Mon, 12 Jun 2023 14:24:46 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01E4BE6B for ; Mon, 12 Jun 2023 11:24:45 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f62b512fe2so5755135e87.1 for ; Mon, 12 Jun 2023 11:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594283; x=1689186283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=o4TG88G8lz+fAZ9zU8d6rxSrHlYur3wUM1VMDavTyKo=; b=loBipD48bZ404WlmVXrHE9OF0fwywsGH/JnBUa99Fda7L2FYBra2kMzYykhiYL74eh 2OAmACB+Nt5QE4OXbVNpeV/2VOwd/Qr3kDkRjwifdpkmSghUHz1Nr5XOzLnOOc/jepf0 vOVvn7pU8gqGnlgQWOhm+TVVQBwIc9QHsCwUY8DM+yzPXaeXHQBAaImt5LOMuj+D9KMR mHTLaUjvJv2uf0WTWubjOZ2pO6qGvmxIhit5PQrXJaby5vdElAjAP8snqdn7ai+A+Euu 82uuyiUio/p9kjATJ09ue/fKVn6j0s/GeXR75nujCfDAga1QRA639M/Lx47/dMF2KKqq tZiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594283; x=1689186283; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o4TG88G8lz+fAZ9zU8d6rxSrHlYur3wUM1VMDavTyKo=; b=FLUpQ5REolBLUvNlu6DqBXxrOkGh4B2ksTSk3bx50qpBZetdwK6znpyjiQTiyfPAi1 LPJUWXIpkVw7XX6TP70CpPSwOVcZwEHirRUb+moB6ZP+2KaiCYulirEsaMlb7AwJcwNM tFa/8kLMVcmXGdy778iUTshhHRGnDEaeyGtIoYcy1iluOElhu9u8dM5VYaKe9cTqbr5/ 0+3tggTbY2vhJIKJpHQFgklsqtSxB+YLbQO9tMgJko76XBmzLy2ah56xuDyx8g7l/JDn 2UkMSmNxfd7dwPo1QuBK+Hc7lJutik8jS3XUTUnVoKGj7fo9RGGkII1V/BKnnFro2FAR c4ng== X-Gm-Message-State: AC+VfDwVGrmqC+TVqTl8Xb2Vq+8Lpq0LG2mUrzBoojiV84I/3CmfIW6v hW+Of94oP5tKy7J69Gj7z9+X1w== X-Google-Smtp-Source: ACHHUZ5/BWwu6sOkYx5RE/rkClGV95eeDtFMUyIDILZdFknNS8QETCM3gAleZueP/DBL7rxmVgR2NQ== X-Received: by 2002:a19:914f:0:b0:4f3:a483:557 with SMTP id y15-20020a19914f000000b004f3a4830557mr4254666lfj.5.1686594283376; Mon, 12 Jun 2023 11:24:43 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:43 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:21 +0200 Subject: [PATCH v3 04/23] clk: qcom: smd-rpm: Move some RPM resources to the common header MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-4-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=2437; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UU7GtjAFC9F3/14Sgtv72aSDwAe2u4JL+0KQToDCmwI=; b=iX5fHRl6tir/I7qMgS6vwBY+LdMrYMhq6DtPXkBDkzFQZbIfwPo0YpBIUEuqs0CTpvFej8BXE 9XtHBB+AKhkA2PRGTSxGEoUTlRk8Yij5oLMWIEe2hJiV66hloeyZbpg X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for handling the bus clocks in the icc driver, carve out some defines and a struct definition to the common rpm header. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 13 ------------- include/linux/soc/qcom/smd-rpm.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index e4de74b68797..937cb1515968 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -18,13 +18,6 @@ #include -#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 -#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 -#define QCOM_RPM_SMD_KEY_RATE 0x007a484b -#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 -#define QCOM_RPM_SMD_KEY_STATE 0x54415453 -#define QCOM_RPM_SCALING_ENABLE_ID 0x2 - #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ type, r_id, key) \ static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ @@ -171,12 +164,6 @@ struct clk_smd_rpm { unsigned long rate; }; -struct clk_smd_rpm_req { - __le32 key; - __le32 nbytes; - __le32 value; -}; - struct rpm_smd_clk_desc { struct clk_smd_rpm **clks; size_t num_clks; diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 99499e4b080e..8190878645f9 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -2,6 +2,8 @@ #ifndef __QCOM_SMD_RPM_H__ #define __QCOM_SMD_RPM_H__ +#include + struct qcom_smd_rpm; #define QCOM_SMD_RPM_ACTIVE_STATE 0 @@ -45,6 +47,19 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_PKA_CLK 0x616b70 #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d +#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773 +#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b +#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45 +#define QCOM_RPM_SMD_KEY_STATE 0x54415453 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2 + +struct clk_smd_rpm_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, u32 resource_type, u32 resource_id, From patchwork Mon Jun 12 18:24:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21BA9C88CB2 for ; Mon, 12 Jun 2023 18:30:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233459AbjFLSav (ORCPT ); Mon, 12 Jun 2023 14:30:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237691AbjFLSYs (ORCPT ); Mon, 12 Jun 2023 14:24:48 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F498E73 for ; Mon, 12 Jun 2023 11:24:46 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f658a17aa4so4648499e87.0 for ; Mon, 12 Jun 2023 11:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594285; x=1689186285; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eCy7STwPQguvSNXF/hCQ4j5BFOyuDUsQ8E/cZCUelP4=; b=G4oYaGxAqeEmVL2CCO3hv38YyrJcIKojCs3Vh+ankfaH8waqiFXAOtsKk9Qn1QXPSk pxBr/2G4q3Wt5UMBSzkCRTagGyg/FSofzHYJP85wasMmMZsz1Vs7Vm2nnaCBjhOsbv5A LIoPw8uOw/AX1VxQ5wtdFQuSIgJ5dscLsWy9kzdqTWAhAGCUSSU1AKmi0ddB+t0wdk8m us4OEwBeD2ze2FHX1zB8S4VeNJ7WDvpMuRlMis9P5DQ4JRJxuxqCj71ZPNnSNiiSuYmA D2yBfXyLM+YAipdUeixMYONA2f0IzYRqNjQ6c9XUPGo21YXtLAY+3oX5vVLI+QAKDGh2 uZgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594285; x=1689186285; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eCy7STwPQguvSNXF/hCQ4j5BFOyuDUsQ8E/cZCUelP4=; b=GXQhjUPCrm8cgVNyG4ygVNqQZXF90tesJWLBWXUn5PjP5dZ9iKxu2sPG7BflgmVCRV u9lrMBJUco8qgShMcFH1uk0XIvbTrdLQKyIjEpOeYwIzFp2lAbArktH8UQmtSCL31EgP VFG610K+Te8/g3kkDabLpLHJfcVrc67M1XYR2nRpMCKAj3c0jcqp7N5EulNa14gGjup6 i/zg57euUvhOFZSjmIVL84xOZGRroT4FF/197cEGXo1Ar/y1ojQcYh6l+SG1jVl3kN0z Sw0cNtER95J3ZEoXxxQB5hNG7WLoDi079fMYDMo2099yUvy06gg0npSMB3nG8p3Wc+6o 3RSQ== X-Gm-Message-State: AC+VfDy5IHnEvfC3HQnfEJEOrbVRWHffy72g68i6x6uUHKrzOvlqLfXg zd1So0WiORaMPhiqA1dd02+VIA== X-Google-Smtp-Source: ACHHUZ58CWP0TUQtOmIAKW02HnTkreLK4yWE3dA8m7XEttkU90zKpYDVPxFVEoeQ7TGKUloBU5imOg== X-Received: by 2002:ac2:51bc:0:b0:4f6:1805:6095 with SMTP id f28-20020ac251bc000000b004f618056095mr5139755lfk.8.1686594284758; Mon, 12 Jun 2023 11:24:44 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:44 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:22 +0200 Subject: [PATCH v3 05/23] soc: qcom: smd-rpm: Move icc_smd_rpm registration to clk-smd-rpm MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-5-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Stephan Gerhold X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=3906; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=5jxwMVCy7bliJJPeYw9tcAw9XDgLw6G87CnBeb6K5TA=; b=pTSpv7jAl37WWUaTl+0qjbAvU7VYkk18U8q9fyvaSeD8hy51vvTFBgtDYt9kqtn4DFF6U90x4 absnOHbqtZ5A2xhhozHZkx9gFRleVQTmtNpXvRSeL5A+xhmew+0lJgn X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Stephan Gerhold icc_smd_rpm will do bus clock votes itself rather than taking the unnecessary detour through the clock subsystem. However, it can only do that after the clocks have been handed off and scaling has been enabled in the RPM in clk-smd-rpm. Move the icc_smd_rpm registration from smd-rpm.c to clk-smd-rpm.c to avoid any possible races. icc_smd_rpm gets the driver data from the smd-rpm device, so still register the platform device on the smd-rpm parent device. Signed-off-by: Stephan Gerhold [Konrad: remove unrelated cleanups] Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 21 +++++++++++++++++++++ drivers/soc/qcom/smd-rpm.c | 17 +---------------- 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 937cb1515968..6e7f0438e8b8 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1289,12 +1289,20 @@ static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); } +static void rpm_smd_unregister_icc(void *data) +{ + struct platform_device *icc_pdev = data; + + platform_device_unregister(icc_pdev); +} + static int rpm_smd_clk_probe(struct platform_device *pdev) { int ret; size_t num_clks, i; struct clk_smd_rpm **rpm_smd_clks; const struct rpm_smd_clk_desc *desc; + struct platform_device *icc_pdev; rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); if (!rpmcc_smd_rpm) { @@ -1344,6 +1352,19 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) if (ret) goto err; + icc_pdev = platform_device_register_data(pdev->dev.parent, + "icc_smd_rpm", -1, NULL, 0); + if (IS_ERR(icc_pdev)) { + dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n", + icc_pdev); + /* No need to unregister clocks because of this */ + } else { + ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc, + icc_pdev); + if (ret) + goto err; + } + return 0; err: dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 0c1aa809cc4e..577f1f25ab10 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -19,7 +19,6 @@ /** * struct qcom_smd_rpm - state of the rpm device driver * @rpm_channel: reference to the smd channel - * @icc: interconnect proxy device * @dev: rpm device * @ack: completion for acks * @lock: mutual exclusion around the send/complete pair @@ -27,7 +26,6 @@ */ struct qcom_smd_rpm { struct rpmsg_endpoint *rpm_channel; - struct platform_device *icc; struct device *dev; struct completion ack; @@ -197,7 +195,6 @@ static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev, static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev) { struct qcom_smd_rpm *rpm; - int ret; rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL); if (!rpm) @@ -210,23 +207,11 @@ static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev) rpm->rpm_channel = rpdev->ept; dev_set_drvdata(&rpdev->dev, rpm); - rpm->icc = platform_device_register_data(&rpdev->dev, "icc_smd_rpm", -1, - NULL, 0); - if (IS_ERR(rpm->icc)) - return PTR_ERR(rpm->icc); - - ret = of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev); - if (ret) - platform_device_unregister(rpm->icc); - - return ret; + return of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev); } static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev) { - struct qcom_smd_rpm *rpm = dev_get_drvdata(&rpdev->dev); - - platform_device_unregister(rpm->icc); of_platform_depopulate(&rpdev->dev); } From patchwork Mon Jun 12 18:24:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 761F5CA9EBC for ; Mon, 12 Jun 2023 18:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234786AbjFLSaw (ORCPT ); Mon, 12 Jun 2023 14:30:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237721AbjFLSYv (ORCPT ); Mon, 12 Jun 2023 14:24:51 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B6CF10CC for ; Mon, 12 Jun 2023 11:24:49 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f642a24568so5516858e87.2 for ; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:47 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:24 +0200 Subject: [PATCH v3 07/23] interconnect: qcom: icc-rpm: Allow negative QoS offset MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-7-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=1945; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=rgTDM+URKWJ36SFNnllBnyQwiFYuxKTtmuTacUJ+85U=; b=7UiBzS0n4xsdfHTqQtldUSL1Fr4X4ozDE1+IvyrfLr7nbeJycdVlDkurmHFJcs6oCBEdTQKJS fsyt6fTKUY8DDiVa5bFEWu8qEZXRBe/GT8V7EuZ9RnxlbiJiTJftXed X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In some very very very very unfortunate cases, the correct offset of the QoS registers will be.. negative. One such case is MSM8998, where The DDR BWMON occupies what-would-be-the-BIMC-base which we usually take into account with the register calculation, making the actual BIMC node start at what-would-be-the-BIMC-base+0x300. In order to keep the calculation code sane, the simplest - however ugly it may be - solution is to allow the offset to be negative. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index d2c04c400cad..ba840a436cc0 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -29,10 +29,10 @@ enum qcom_icc_type { * @num_intf_clks: the total number of intf_clks clk_bulk_data entries * @type: the ICC provider type * @regmap: regmap for QoS registers read/write access - * @qos_offset: offset to QoS registers * @bus_clk_rate: bus clock rate in Hz * @bus_clks: the clk_bulk_data table of bus clocks * @intf_clks: a clk_bulk_data array of interface clocks + * @qos_offset: offset to QoS registers * @keep_alive: whether to always keep a minimum vote on the bus clocks * @is_on: whether the bus is powered on */ @@ -42,7 +42,7 @@ struct qcom_icc_provider { int num_intf_clks; enum qcom_icc_type type; struct regmap *regmap; - unsigned int qos_offset; + int qos_offset; u64 bus_clk_rate[NUM_BUS_CLKS]; struct clk_bulk_data bus_clks[NUM_BUS_CLKS]; struct clk_bulk_data *intf_clks; @@ -108,7 +108,7 @@ struct qcom_icc_desc { bool no_clk_scaling; enum qcom_icc_type type; const struct regmap_config *regmap_cfg; - unsigned int qos_offset; + int qos_offset; }; /* Valid for all bus types */ From patchwork Mon Jun 12 18:24:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80E57C88CB4 for ; Mon, 12 Jun 2023 18:25:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238158AbjFLSZV (ORCPT ); Mon, 12 Jun 2023 14:25:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237772AbjFLSYy (ORCPT ); Mon, 12 Jun 2023 14:24:54 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36D69E7B for ; Mon, 12 Jun 2023 11:24:52 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4f004cc54f4so5580730e87.3 for ; Mon, 12 Jun 2023 11:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594290; x=1689186290; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qoVwErVMHDjHjayDKUron2vfQdiFrlJxkN0o/O5bBtA=; b=qXRITVAtc1dn+CSZ4LgYXqwiWtNcR9mM4H2dFeg2jwOiGmILmjhh9sOyoG9fN5rCmp WLYDkWb5McIecYyfKkI69ZqYiLz5SGzxRpDPGg4lk/5GFXMklr7T2H1jtr8HLvPkTJyt xZAALrjt+tnR+90+QknVaEAGd+A3NQo7TxDQyDzrEGLCT+5l/oqfs5pU3gCpZcBweaXS fsTalvBFG3SQs+djzENhPESI5/lCFktIy0OSAE05yT6V3LxjInpFAMS7uj6tB9VmZ+BU pMxJ+wiD4EJ+qcLUq/xIvhfe+ne+1KP+1WgB4R8+EqNSehSgLOcf5ptXcB842i4PThoV 6kKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594290; x=1689186290; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qoVwErVMHDjHjayDKUron2vfQdiFrlJxkN0o/O5bBtA=; b=PYCvgwkApDmhWVdqfhAqPjfgrGPEjQQUtmHxFslYM2Vohs9dusGCFtTui8lQYJFTSa mRGujIWv5MZi/HdDoS6utfsrzDhkQwg/u1PkPa6LLiaaKH3VfB+A5v0nBQOQnbcKypUc h9iSNfMDSblfmavI9vVsiz/lExdc1cMYBg3qyJTQ+SF1uu61dApEUk0O5tgZhPJ96eS4 R8okhPxdrDsHtsFPmz7NgnYMR8q/2J0QQQjOpgDrcGjQ5UO+Fn0Awcwcz9ApCiMqCiiV 3HJIbvumhCJudPvJ0pmGO9RmCTVXxJAPbIwRXZZKuAv/wfGP5xLaQ/dVEMmSljldEw6P q1UQ== X-Gm-Message-State: AC+VfDyIR8QStVLdngNPrfTD2DEjcm9Hs0HYOb0IC6dWtstBloY2jGmd at2cmWfEjQaUw2CCHA8/FNH+Gw== X-Google-Smtp-Source: ACHHUZ4C95zt4fw031PkmDVq6rh9WnxR9inBA5lq5ZXv7YG33eB8EI6ZIEAIT7A7vCkSZMhjG2FSMw== X-Received: by 2002:ac2:4da7:0:b0:4f6:54c2:35bd with SMTP id h7-20020ac24da7000000b004f654c235bdmr4391451lfe.11.1686594290517; Mon, 12 Jun 2023 11:24:50 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:50 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:26 +0200 Subject: [PATCH v3 09/23] interconnect: qcom: smd-rpm: Add rpmcc handling skeleton code MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-9-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=3554; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CbTTRxJto8qrm6plde8cKMqpaBb1rdIRss/XEaPuhyo=; b=V8ybrcxkJtmQI9Y0OyQAx8gGXhOVsVAWAmYQeFQkAko3KQzznKBDzT0BSCz3JdRdcGbYuLwET JS0y1CmqbY2C6HAx8dSeEQJLyW8lRPvW8sLXe5nSdgeM03lyxl5a3/L X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce qcom_icc_rpm_set_bus_rate() in preparation for handling RPM clock resources within the interconnect framework. This lets us greatly simplify all of the code handling, as setting the rate comes down to: u32 rate_khz = max(clk.sleep_rate, clk.active_rate, clk_a.active_rate) write_to_rpm(clock.description, rate_khz); Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.h | 15 +++++++++++++++ drivers/interconnect/qcom/smd-rpm.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 9b4ea4e39b9f..aec192321411 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -22,6 +22,18 @@ enum qcom_icc_type { QCOM_ICC_QNOC, }; +/** + * struct rpm_clk_resource - RPM bus clock resource + * @resource_type: RPM resource type of the clock resource + * @clock_id: index of the clock resource of a specific resource type + * @branch: whether the resource represents a branch clock +*/ +struct rpm_clk_resource { + u32 resource_type; + u32 clock_id; + bool branch; +}; + #define NUM_BUS_CLKS 2 /** @@ -47,6 +59,7 @@ struct qcom_icc_provider { int qos_offset; u64 bus_clk_rate[NUM_BUS_CLKS]; struct clk_bulk_data bus_clks[NUM_BUS_CLKS]; + const struct rpm_clk_resource *bus_clk_desc; struct clk_bulk_data *intf_clks; bool keep_alive; bool is_on; @@ -104,6 +117,7 @@ struct qcom_icc_desc { struct qcom_icc_node * const *nodes; size_t num_nodes; const char * const *bus_clocks; + const struct rpm_clk_resource *bus_clk_desc; const char * const *intf_clocks; size_t num_intf_clocks; bool keep_alive; @@ -125,5 +139,6 @@ int qnoc_remove(struct platform_device *pdev); bool qcom_icc_rpm_smd_available(void); int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate); #endif diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c index b0183262ba66..433276f1e671 100644 --- a/drivers/interconnect/qcom/smd-rpm.c +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -16,6 +16,7 @@ #include "icc-rpm.h" #define RPM_KEY_BW 0x00007762 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b static struct qcom_smd_rpm *icc_smd_rpm; @@ -44,6 +45,38 @@ int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) } EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send); +int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, u32 active_rate, u32 sleep_rate) +{ + struct clk_smd_rpm_req req = { + .key = cpu_to_le32(QCOM_RPM_SMD_KEY_RATE), + .nbytes = cpu_to_le32(sizeof(u32)), + }; + int ret; + + /* Branch clocks are only on/off */ + if (clk->branch) { + active_rate = !!active_rate; + sleep_rate = !!sleep_rate; + } + + req.value = cpu_to_le32(active_rate); + ret = qcom_rpm_smd_write(icc_smd_rpm, + QCOM_SMD_RPM_ACTIVE_STATE, + clk->resource_type, + clk->clock_id, + &req, sizeof(req)); + if (ret) + return ret; + + req.value = cpu_to_le32(sleep_rate); + return qcom_rpm_smd_write(icc_smd_rpm, + QCOM_SMD_RPM_SLEEP_STATE, + clk->resource_type, + clk->clock_id, + &req, sizeof(req)); +} +EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate); + static int qcom_icc_rpm_smd_remove(struct platform_device *pdev) { icc_smd_rpm = NULL; From patchwork Mon Jun 12 18:24:29 2023 Content-Type: text/plain; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:54 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:29 +0200 Subject: [PATCH v3 12/23] interconnect: qcom: sdm660: Hook up RPM bus clk definitions MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-12-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=1986; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Krc2Kcr5fnOQoU3m0Y+nr01slcqtM3Q1E0UfX4Ye6Q4=; b=2b/6IkjpCVKop7AxhdWXBvUWfBCet//VkgmSPfHfy9/tAb7joqNwWZfuErOaQBTMCHZ4ldl5y 8uuZqPW3SYkARThKexAzyqY3OElO4UfWWvZPrJo9AsdqEXfpaRasoAi X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm660.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 003fc7d110a7..5743ed680e8e 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -1511,6 +1511,7 @@ static const struct qcom_icc_desc sdm660_a2noc = { .type = QCOM_ICC_NOC, .nodes = sdm660_a2noc_nodes, .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes), + .bus_clk_desc = &aggre2_clk, .intf_clocks = a2noc_intf_clocks, .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), .regmap_cfg = &sdm660_a2noc_regmap_config, @@ -1539,6 +1540,7 @@ static const struct qcom_icc_desc sdm660_bimc = { .type = QCOM_ICC_BIMC, .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), + .bus_clk_desc = &bimc_clk, .regmap_cfg = &sdm660_bimc_regmap_config, }; @@ -1593,6 +1595,7 @@ static const struct qcom_icc_desc sdm660_cnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_cnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes), + .bus_clk_desc = &bus_2_clk, .regmap_cfg = &sdm660_cnoc_regmap_config, }; @@ -1655,6 +1658,7 @@ static const struct qcom_icc_desc sdm660_mnoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), + .bus_clk_desc = &mmaxi_0_clk, .intf_clocks = mm_intf_clocks, .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), .regmap_cfg = &sdm660_mnoc_regmap_config, @@ -1692,6 +1696,7 @@ static const struct qcom_icc_desc sdm660_snoc = { .type = QCOM_ICC_NOC, .nodes = sdm660_snoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes), + .bus_clk_desc = &bus_1_clk, .regmap_cfg = &sdm660_snoc_regmap_config, }; From patchwork Mon Jun 12 18:24:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E4ECC88CBC for ; Mon, 12 Jun 2023 18:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238215AbjFLSZ0 (ORCPT ); Mon, 12 Jun 2023 14:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237907AbjFLSZB (ORCPT ); Mon, 12 Jun 2023 14:25:01 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE8BCE7B for ; Mon, 12 Jun 2023 11:24:58 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f655293a38so5191436e87.0 for ; Mon, 12 Jun 2023 11:24:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594297; x=1689186297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oxwAlvsxTG2NJKirdi7L920nJWliszLcfh8qb5HaEiU=; b=KrxKoZAteRQDDN5hHVT10/mvSJUs3GSrKyx9wHMwt4dGs7Ui1g0JYCvH/AvlxeJdM7 8V/eSMvAZh2aSep1ShcofRbjU+7mGzRhNRZ3YUxMYlsGe7EBiukq5F7P/ed1NS1nFTtY mP4l/9Kbc2YK66VTjWhbqirbsoe+Z0uMWjaunbEfD7nFlEVnFJorXOKZ4BZHhD/o/33G OBx4VXQY0ide1PAXexByFEv8RNdkVs9QSIe3MoHEHWZxhK5RVl7ForR/IdwlCHA2bZNH GVlHfTZWzK1I7UAO7G47vuNkn/4RLJ44iN4JoSxWtfVcV/9ypc7yR+nRkB89UNFcZwwR e5rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594297; x=1689186297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oxwAlvsxTG2NJKirdi7L920nJWliszLcfh8qb5HaEiU=; b=dnRCOJuXsH1jnvrFGmC8cuDzSb3x88emWyluGWBOCRHshZRcGDh4svaaprOeSYS7Hz dJWfMg7zf+o9llAVnrbTjNJeoZt9MpQ70e7dBwRHEc62fZjiU4Zj/2zlu4t6/ImnfH6t KrXUX6OPQsz55WNANHp67Fl3sNmN9eTTmKISZpLuYwMh5Z9MZ5nze7OgG4VL4xMPIjvC e59TzdxZRXCPd6S/R9/T7M+CZvBptUTFJo/kz9i5zTcze0v9BohVLbPVKKMmltCWKHJP Ns6zXGwPACfZkbhTvE/6I8Tbmx+UEwPKwIJw85gREpCi7rAgCiEr0Xgn1SGVnCQ413ep V76w== X-Gm-Message-State: AC+VfDyY0tfyVMopYA3R7FXWriuUv2K0ZpJ1/b4CO7o92ERmJbf9YvFi Nbar9C9DjdEByYeAzCUl0GINNQ== X-Google-Smtp-Source: ACHHUZ6Fre2H7uk+cngqm56F9E8xnzgp77wCVevAsYlSJzkkkoEn2t6P4PgjJc+hqE9J/1xdYC3k1A== X-Received: by 2002:a19:f205:0:b0:4dd:ce0b:7692 with SMTP id q5-20020a19f205000000b004ddce0b7692mr4500967lfh.46.1686594297148; Mon, 12 Jun 2023 11:24:57 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:56 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:31 +0200 Subject: [PATCH v3 14/23] interconnect: qcom: qcs404: Hook up RPM bus clk definitions MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-14-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=1291; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=NibH4RmX92w9jFbYbYmeVzyLtbX9fV3dfXE9S9JnGAI=; b=vYHOmrHPf2khIR+4l0Ku4Kx0v4SMVzTQA+pWwvGePhMzB914Y/Y915j+Ii7EJoq664w3zSQNm MlSw8cNNRLXDgr3saJcF5EuuvFEWnr3IsKGW+wWyoc8Q1xlYuOly/6h X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/qcs404.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 938283ddd0e3..9deb4d81104e 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -984,6 +984,7 @@ static struct qcom_icc_node * const qcs404_bimc_nodes[] = { }; static const struct qcom_icc_desc qcs404_bimc = { + .bus_clk_desc = &bimc_clk, .nodes = qcs404_bimc_nodes, .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes), }; @@ -1038,6 +1039,7 @@ static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = { }; static const struct qcom_icc_desc qcs404_pcnoc = { + .bus_clk_desc = &bus_0_clk, .nodes = qcs404_pcnoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes), }; @@ -1066,6 +1068,7 @@ static struct qcom_icc_node * const qcs404_snoc_nodes[] = { }; static const struct qcom_icc_desc qcs404_snoc = { + .bus_clk_desc = &bus_1_clk, .nodes = qcs404_snoc_nodes, .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes), }; From patchwork Mon Jun 12 18:24:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83E38C88CBD for ; Mon, 12 Jun 2023 18:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238220AbjFLSZ0 (ORCPT ); Mon, 12 Jun 2023 14:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237936AbjFLSZC (ORCPT ); Mon, 12 Jun 2023 14:25:02 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DABDE7D for ; Mon, 12 Jun 2023 11:25:00 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f62d93f38aso5648628e87.0 for ; Mon, 12 Jun 2023 11:25:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594298; x=1689186298; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eHA+43B3syu0x2pUChrYAxljP6/us7hNfim2x8e+Qms=; b=NfKrzpunMVdpWMjPG9voSJeMucexL04h+BduTpiCgT1+Zullm2/uL1Mb4m+46lZhtn 6XMX4qXMA8KA5dgrnMfi0zOMX7WcnKbF8/fuu2g8VcHcCo4H+I2trCAjaDD0JA9/bMJa 35u5/qMcIMyb5xYuEJAWJpT0lG5J605IusXXlBcaTFYVWIrrxdA2nugMgShaXj4hCW51 27ZDUtuP3mfgpWTmpz0YsGU+iSNFqhJxX28pjWzWXAD1wPHrwjFrmygwMTCSqkzz4YrS GWT3Ink//XdE/yVMdjG7EGPQ6sjFNVTqF1yEU2+pywwQuwD64EHmqvf/6E+Gv0ZTYAMe kNvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594298; x=1689186298; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eHA+43B3syu0x2pUChrYAxljP6/us7hNfim2x8e+Qms=; b=cqqyl8XPGwLaYhJRn10g01fYtESaXVXdnuNUFrYiym3f/nfEIp/RZVapYQbhdXlUlB Wsbhl4H4RMlOdc+N++HTUjNTrmHkdQcHB1uFWXyxXDWUwkLVcZdhtIc+qvBCcCPjyGyx H0dy6L+TlxwZaSRqvIePFfpcYI4tUMqVErC4znC0zKR8UynSlh5g6HaqYrWRHMSRPybB euF83R7PZKlfhoPBUhUQf9oDdO2d1Ks1DdwLFvYjv0Pr3sgtBvx7yBAPlHVvpVv1a/Lh ZZHxJTxkyzPPVMG5/Hlt4K3VzMTDw0NJLASm9K8Hctfh+2uZWv/ziqQkmt9kEvpnYwR6 NU0A== X-Gm-Message-State: AC+VfDyzXGbxlqebklqQuPYWg/LOD7Ssrdnj04yBlO4csGcBaMfgW3lk KJfafrdzpN4SdvkBRqypM6SkiA== X-Google-Smtp-Source: ACHHUZ7fw+vOLrzZksInuc1Lvn05bR2q5rVrbRuUQWMPbtMGOaDnF3P4qacIZVu2bvgnUx1b4IZtFw== X-Received: by 2002:a19:ab01:0:b0:4f3:aa09:5566 with SMTP id u1-20020a19ab01000000b004f3aa095566mr4439806lfe.65.1686594298549; Mon, 12 Jun 2023 11:24:58 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.24.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:24:58 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:32 +0200 Subject: [PATCH v3 15/23] interconnect: qcom: msm8939: Hook up RPM bus clk definitions MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-15-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov , Stephan Gerhold X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=1734; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1B8WtVx3wEojfY5dydOVxe8YjeFJXTMa40iYBVHPUpQ=; b=9IILqMRi23Bstk6wlqfTWuZtWda1m9Lj1xzdDTC/WaKfvRaX+YgXn4P8vKd97L/pcYu8RoNNw P0uj+LCNi4UBoMn2PMQh2Sun2+1Eq+YjfqIKcvvt1Rz4zDY8kj3k8wU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by: Dmitry Baryshkov Reviewed-by: Stephan Gerhold Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/msm8939.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 639566dce45a..94b11b590a8e 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1284,6 +1284,7 @@ static const struct qcom_icc_desc msm8939_snoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), + .bus_clk_desc = &bus_1_clk, .regmap_cfg = &msm8939_snoc_regmap_config, .qos_offset = 0x7000, }; @@ -1304,6 +1305,7 @@ static const struct qcom_icc_desc msm8939_snoc_mm = { .type = QCOM_ICC_NOC, .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), + .bus_clk_desc = &bus_2_clk, .regmap_cfg = &msm8939_snoc_regmap_config, .qos_offset = 0x7000, }; @@ -1332,6 +1334,7 @@ static const struct qcom_icc_desc msm8939_bimc = { .type = QCOM_ICC_BIMC, .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), + .bus_clk_desc = &bimc_clk, .regmap_cfg = &msm8939_bimc_regmap_config, .qos_offset = 0x8000, }; @@ -1403,6 +1406,7 @@ static const struct qcom_icc_desc msm8939_pcnoc = { .type = QCOM_ICC_NOC, .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), + .bus_clk_desc = &bus_0_clk, .regmap_cfg = &msm8939_pcnoc_regmap_config, .qos_offset = 0x7000, }; From patchwork Mon Jun 12 18:24:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E988CCA9EA5 for ; Mon, 12 Jun 2023 18:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238245AbjFLSZ3 (ORCPT ); Mon, 12 Jun 2023 14:25:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237996AbjFLSZF (ORCPT ); Mon, 12 Jun 2023 14:25:05 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B658E78 for ; Mon, 12 Jun 2023 11:25:03 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4f6195d2b3fso5640353e87.1 for ; Mon, 12 Jun 2023 11:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686594301; x=1689186301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=o0XnmH13ivRPPHGJLER9uxu6PJxvQI4F3jOrAVZw55g=; b=xWUnJglbfMZ3rGAv4MqERD3xkoTFovYVULogIGddo4rqrnYrZ3CQo2pzIvvixci7ZF cvyZiGSZNclBDpIO/6nnnAUkchkfgtAvY0KJMTFCe0FM3HcWR7oiIG+UPE88Ke2y8kdT ZGZAo5ZszB6fr36DHkEQpVhlHuYPXtkGD/ZULQIkKV2WyTix7j17zyOj+uU6jaaN/WH0 f8mK2tNmAVyrJ0o6GdiR0oIVtBjcwC3xqJvOdlXphVDatRLU8W2b/AFyQSIgYlQMfRET dqEMYl6pfRD7W4/Fpm2e4fMNFadl7huGo9CJXqWWix/uGXisUj8PHUUd25awOPEkkynR s5bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686594301; x=1689186301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o0XnmH13ivRPPHGJLER9uxu6PJxvQI4F3jOrAVZw55g=; b=OfVsZo27Y/BFcvxGEjmmXPgJmhhgchfc+f730bWPsnHYCgzfv7lUnndTdr+fMT67cB bsSjW2IRNXqXUvhmtVbzTbia2KOKuTXoyPJ33GP9rABsO9sdKSEAewwFQ715j21xA1lo b/nrcyoD+TJwjuExb4z1pWswP0ioc8ciG+0wsEchyP69lTu/sqK4AvMHkgY9JBBu1SoH 4plqgXqVU/b+TVleS4rRk3eLL0wIYGeaboiRnzRx49YfgyfEYnYZlmymeuwQeYdDb6o2 VbBiAP318KUwE95SZ2meRcICTNI0XCcCkluwKTnmbvUg3NvgoT08CC/w0QRSk5bj+/g3 IWDQ== X-Gm-Message-State: AC+VfDxTTXfYscJC69MoNadBf/iSRWI0HUjtmIokDvuUXVgpFwgWDvC8 vf6Hk5I4H5oepWmQsrSys7Lbhg== X-Google-Smtp-Source: ACHHUZ5YGWB1Pz0JWAq0pXlivYyEghhPm8aOujYRyTmM+uFNGWbgmOp2Lw7l6BMUqAeWy944BNJl/g== X-Received: by 2002:a19:671a:0:b0:4f1:458c:c4c with SMTP id b26-20020a19671a000000b004f1458c0c4cmr4275294lfc.43.1686594301435; Mon, 12 Jun 2023 11:25:01 -0700 (PDT) Received: from [192.168.1.101] (abyj190.neoplus.adsl.tpnet.pl. [83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:25:01 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:34 +0200 Subject: [PATCH v3 17/23] interconnect: qcom: qcm2290: Hook up RPM bus clk definitions MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-17-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=2388; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tSBMAPt7cmsb0YEEInMBYypPFAnegUdevAoSi5GlaYA=; b=j3W8fpt5zJJ9oVdPgFxRoSq13t7pBvjjzWlle1WJxmfiI9hlpvAlSXDXLRgCqdSPcavaI0zec lmxSOhAtaxsB82oAZy8+HDTap9uMpOfS7mykGamlmTqy1qjtzGM0Edv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Assign the necessary definitions to migrate to the new bus clock handling mechanism. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/qcm2290.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index cb636e67a5a4..2c7a76fab83c 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -1196,6 +1196,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { .type = QCOM_ICC_BIMC, .nodes = qcm2290_bimc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), + .bus_clk_desc = &bimc_clk, .regmap_cfg = &qcm2290_bimc_regmap_config, /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ .qos_offset = 0x8000, @@ -1251,6 +1252,7 @@ static const struct qcom_icc_desc qcm2290_cnoc = { .type = QCOM_ICC_NOC, .nodes = qcm2290_cnoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), + .bus_clk_desc = &bus_1_clk, .regmap_cfg = &qcm2290_cnoc_regmap_config, }; @@ -1292,6 +1294,7 @@ static const struct qcom_icc_desc qcm2290_snoc = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_snoc_nodes, .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), + .bus_clk_desc = &bus_2_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ .qos_offset = 0x15000, @@ -1306,6 +1309,7 @@ static const struct qcom_icc_desc qcm2290_qup_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_qup_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), + .bus_clk_desc = &qup_clk, }; static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { @@ -1319,6 +1323,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmnrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), + .bus_clk_desc = &mmaxi_0_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, .qos_offset = 0x15000, }; @@ -1333,6 +1338,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = { .type = QCOM_ICC_QNOC, .nodes = qcm2290_mmrt_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), + .bus_clk_desc = &mmaxi_1_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, .qos_offset = 0x15000, }; From patchwork Mon Jun 12 18:24:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F9D4C88CBB for ; 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:25:04 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:36 +0200 Subject: [PATCH v3 19/23] clk: qcom: smd-rpm: Separate out interconnect bus clocks MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-19-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=26677; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=b1fcpW1FguL43YfbPVvUZKbf1hq8/EEzu+HzcWkLj0U=; b=XR/Suq+cy2c280/f1YdpB6CIcwZ6vuAXnyQ3R8oVNxjjUgn8kzmrLkk9GBXVYaKXHM/tJaVdE DO4Rl4PfOoUDxqGWl+OBgEAic67bEYznS5PqL3bpi0t6xyTn6ky2DTK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The interconnect bus clocks are now handled within the ICC framework. They still however need to get a kickstart *before* we call clk_smd_rpm_enable_scaling(), or RPM will assume that they should all be running at 0 kHz and the system will inevitably die. Separate them out to ensure such a kickstart can still take place. As a happy accident, the file got smaller: Total: Before=41951, After=41555, chg -0.94% Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-smd-rpm.c | 278 +++++++++++++++++------------------------ 1 file changed, 115 insertions(+), 163 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 6e7f0438e8b8..0d1d97659d59 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -167,6 +167,14 @@ struct clk_smd_rpm { struct rpm_smd_clk_desc { struct clk_smd_rpm **clks; size_t num_clks; + + /* + * Interconnect clocks are managed by the icc framework, this driver + * only kickstarts them so that they don't get gated between + * clk_smd_rpm_enable_scaling() and interconnect driver initialization. + */ + struct clk_smd_rpm **icc_clks; + size_t num_icc_clks; bool scaling_before_handover; }; @@ -498,13 +506,69 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); +static struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, +}; + +static struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, +}; + +static struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_sysmmnoc_clk, +}; + +static struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_ocmemgx_clk, +}; + +static struct clk_smd_rpm *msm8996_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_branch_aggre1_noc_clk, + &clk_smd_rpm_branch_aggre2_noc_clk, + &clk_smd_rpm_bus_0_pcnoc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static struct clk_smd_rpm *msm8998_icc_clks[] = { + &clk_smd_rpm_aggre1_noc_clk, + &clk_smd_rpm_aggre2_noc_clk, + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static struct clk_smd_rpm *sdm660_icc_clks[] = { + &clk_smd_rpm_aggre2_noc_clk, + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_snoc_clk, + &clk_smd_rpm_bus_2_cnoc_clk, + &clk_smd_rpm_mmssnoc_axi_rpm_clk, +}; + +static struct clk_smd_rpm *sm_qnoc_icc_clks[] = { + &clk_smd_rpm_bimc_clk, + &clk_smd_rpm_bus_1_cnoc_clk, + &clk_smd_rpm_mmnrt_clk, + &clk_smd_rpm_mmrt_clk, + &clk_smd_rpm_qup_clk, + &clk_smd_rpm_bus_2_snoc_clk, +}; + static struct clk_smd_rpm *msm8909_clks[] = { - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, @@ -530,15 +594,11 @@ static struct clk_smd_rpm *msm8909_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { .clks = msm8909_clks, .num_clks = ARRAY_SIZE(msm8909_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -562,21 +622,15 @@ static struct clk_smd_rpm *msm8916_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { .clks = msm8916_clks, .num_clks = ARRAY_SIZE(msm8916_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8917_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -596,19 +650,13 @@ static struct clk_smd_rpm *msm8917_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { .clks = msm8917_clks, .num_clks = ARRAY_SIZE(msm8917_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8936_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -632,25 +680,17 @@ static struct clk_smd_rpm *msm8936_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { .clks = msm8936_clks, .num_clks = ARRAY_SIZE(msm8936_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8974_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, @@ -684,20 +724,14 @@ static struct clk_smd_rpm *msm8974_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .clks = msm8974_clks, .num_clks = ARRAY_SIZE(msm8974_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), .scaling_before_handover = true, }; static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -718,24 +752,15 @@ static struct clk_smd_rpm *msm8976_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { .clks = msm8976_clks, - .num_clks = ARRAY_SIZE(msm8976_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, @@ -777,23 +802,15 @@ static struct clk_smd_rpm *msm8992_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { .clks = msm8992_clks, .num_clks = ARRAY_SIZE(msm8992_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), }; static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, @@ -837,29 +854,17 @@ static struct clk_smd_rpm *msm8994_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { .clks = msm8994_clks, .num_clks = ARRAY_SIZE(msm8994_clks), + .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), }; static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -891,6 +896,8 @@ static struct clk_smd_rpm *msm8996_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .clks = msm8996_clks, .num_clks = ARRAY_SIZE(msm8996_clks), + .icc_clks = msm8996_icc_clks, + .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks), }; static struct clk_smd_rpm *qcs404_clks[] = { @@ -919,19 +926,15 @@ static struct clk_smd_rpm *qcs404_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .clks = qcs404_clks, .num_clks = ARRAY_SIZE(qcs404_clks), + .icc_clks = bimc_pcnoc_snoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), }; static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, @@ -954,12 +957,6 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, - [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, @@ -979,27 +976,19 @@ static struct clk_smd_rpm *msm8998_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .clks = msm8998_clks, .num_clks = ARRAY_SIZE(msm8998_clks), + .icc_clks = msm8998_icc_clks, + .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks), }; static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, - [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, @@ -1025,15 +1014,13 @@ static struct clk_smd_rpm *sdm660_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { .clks = sdm660_clks, .num_clks = ARRAY_SIZE(sdm660_clks), + .icc_clks = sdm660_icc_clks, + .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks), }; static struct clk_smd_rpm *mdm9607_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, @@ -1047,21 +1034,15 @@ static struct clk_smd_rpm *mdm9607_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { .clks = mdm9607_clks, .num_clks = ARRAY_SIZE(mdm9607_clks), + .icc_clks = bimc_pcnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks), }; static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, @@ -1083,23 +1064,19 @@ static struct clk_smd_rpm *msm8953_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { .clks = msm8953_clks, .num_clks = ARRAY_SIZE(msm8953_clks), + .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), }; static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, @@ -1110,12 +1087,6 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1125,34 +1096,24 @@ static struct clk_smd_rpm *sm6125_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { .clks = sm6125_clks, .num_clks = ARRAY_SIZE(sm6125_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; /* SM6115 */ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1166,27 +1127,17 @@ static struct clk_smd_rpm *sm6115_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { .clks = sm6115_clks, .num_clks = ARRAY_SIZE(sm6115_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1203,31 +1154,21 @@ static struct clk_smd_rpm *sm6375_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { .clks = sm6375_clks, .num_clks = ARRAY_SIZE(sm6375_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, - [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, - [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, @@ -1249,6 +1190,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { .clks = qcm2290_clks, .num_clks = ARRAY_SIZE(qcm2290_clks), + .icc_clks = sm_qnoc_icc_clks, + .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) }; static const struct of_device_id rpm_smd_clk_match_table[] = { @@ -1332,6 +1275,15 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) goto err; } + for (i = 0; i < desc->num_icc_clks; i++) { + if (!desc->icc_clks[i]) + continue; + + ret = clk_smd_rpm_handoff(desc->icc_clks[i]); + if (ret) + goto err; + } + if (!desc->scaling_before_handover) { ret = clk_smd_rpm_enable_scaling(); if (ret) From patchwork Mon Jun 12 18:24:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 692299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36FA1CA9EAD for ; Mon, 12 Jun 2023 18:25:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237807AbjFLSZe (ORCPT ); Mon, 12 Jun 2023 14:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238104AbjFLSZM (ORCPT ); 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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id v24-20020ac25938000000b004f64073a252sm1502035lfi.96.2023.06.12.11.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 11:25:07 -0700 (PDT) From: Konrad Dybcio Date: Mon, 12 Jun 2023 20:24:39 +0200 Subject: [PATCH v3 22/23] interconnect: qcom: icc-rpm: Set correct bandwidth through RPM bw req MIME-Version: 1.0 Message-Id: <20230526-topic-smd_icc-v3-22-5fb7d39b874f@linaro.org> References: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> In-Reply-To: <20230526-topic-smd_icc-v3-0-5fb7d39b874f@linaro.org> To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Georgi Djakov , Leo Yan , Evan Green , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Stephan Gerhold X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686594276; l=1241; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9Ldf/1D6mnr+DmG72PIWvhQfT7N7aniAjBwqWygdML0=; b=0neN5UyCnSYJ6t+VeLO5GgXbU3AUqIZD2454T+xAoOEeEiGAVAdpNgAN0RwtWuRNKN9szCHIX 9lbs9imkG0tCHqVb43vFt1CdPrB8oSoriJlVZs0xB6n1AYksNjN2kjY X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently, we're setting the aggregated-on-provider bandwidth on each node, individually. That is of course incorrect and results in far too high votes. Use the correct values to ensure we're not wasting power. Fixes: 30c8fa3ec61a ("interconnect: qcom: Add MSM8916 interconnect provider driver") Reported-by: Stephan Gerhold Reviewed-by: Stephan Gerhold Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 8e4eb0b90905..989b8a1de6d1 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -355,12 +355,12 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg); - ret = qcom_icc_rpm_set(src_qn, agg_avg); + ret = qcom_icc_rpm_set(src_qn, src_qn->sum_avg); if (ret) return ret; if (dst_qn) { - ret = qcom_icc_rpm_set(dst_qn, agg_avg); + ret = qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg); if (ret) return ret; }