From patchwork Sat Jun 17 16:15:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 693717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B5FBC001B1 for ; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345932AbjFQQ1E (ORCPT ); Sat, 17 Jun 2023 12:27:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238423AbjFQQ1D (ORCPT ); Sat, 17 Jun 2023 12:27:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77E1F1724; Sat, 17 Jun 2023 09:27:01 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1379F60F76; Sat, 17 Jun 2023 16:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 285D1C433C8; Sat, 17 Jun 2023 16:26:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019220; bh=nfDyGgMqm33myHuNfUx4jziWq1pWWDUYYnNP4dchYlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K0tit8FlvBgNCxLsvZuqNmqrvwKesXFZMHSlgwmFsmGn0CIkrJhOtZ7kDEaM7ktS8 X+JXUbiHFeQsp8XDtM4JEg4RHYUzVx7JuEUHYamsOgkhB87wGrXZHszOv896jkef5y 1vxbmr/fXwWffEflkV4glb6HRsNFNq0FpKISjD10N2BvFH6jUi6o/FNOYAZuLLGSir Rda56EcnXg+nX45s4OKpHtOf5tHhUMkcSdsv6oezjPfdyb/oMYrcv/zaqOilmwcox2 qFgqWjSlIRBydT5+BoVww9Sil5V+ZTOzpK4bEGTKnypTgIf7mDR7SyN6KboJeCEjG3 +TBXVAT8oDgow== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Date: Sun, 18 Jun 2023 00:15:23 +0800 Message-Id: <20230617161529.2092-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible string for the T-HEAD TH1520 clint. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1..388d3385d7eb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 From patchwork Sat Jun 17 16:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 693716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7B8BEB64DB for ; Sat, 17 Jun 2023 16:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345949AbjFQQ1O (ORCPT ); Sat, 17 Jun 2023 12:27:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345967AbjFQQ1L (ORCPT ); Sat, 17 Jun 2023 12:27:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6222D173B; Sat, 17 Jun 2023 09:27:09 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E9A5D60F71; Sat, 17 Jun 2023 16:27:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AE5C433CD; Sat, 17 Jun 2023 16:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019228; bh=9TcP0pheewMFNteE2MjQt4eyImwOKciOqR8+Aqc04aI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPnAUsh93U3aeHBUKqzv4wIHLB3IOdV2/E6/coVGuZyPoQ34uckzFBlxTg2W2TApd ElOmw92e7gpvrpqZCj0LR+ePdZPnWiSteQwpULo5lNfTQOo09E1ViF2YbdCqlblh/w rzqy68lX5qbuPf2pI6lR8Y7gEFVwSOAqtFHoZ3wGgQ6jaHe+WzG98kZ4LEQE6z0fKW pnWBbX5XYpiKkX1QOk5psdB1DfcRGUF/Upf+63t+59b5/xuyi7BoIfzBeMFFpNvY2/ weom9JS1O9tQqeAkZv0pDRso9V9TXdymiQr0zAHnAzWjSoMzWxbbgCoVnYl+E2ywLP EphWZrBIzsKew== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Date: Sun, 18 Jun 2023 00:15:25 +0800 Message-Id: <20230617161529.2092-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT From patchwork Sat Jun 17 16:15:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 693715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79921EB64D9 for ; Sat, 17 Jun 2023 16:27:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346318AbjFQQ1e (ORCPT ); Sat, 17 Jun 2023 12:27:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346322AbjFQQ11 (ORCPT ); Sat, 17 Jun 2023 12:27:27 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E84C2700; Sat, 17 Jun 2023 09:27:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C70D160F71; Sat, 17 Jun 2023 16:27:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5DAF8C433C0; Sat, 17 Jun 2023 16:27:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019236; bh=SPhHXPcnyMrXjaiP7DOxwbB5VjmdUJq9U0kUEmDjQ0w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=psdbYLjaspvqgMtuNSkr/BszIFTR4pISYrWxkLOPmv8bPWSIkxY0AgQSBtF3YXC2Y +jGPnMEvDbvFIa/9sxjQT/UAYeFa+wwReHYVw57aqO+sjWmRwpM2ZDVjN97UZopvzS FIi+hi9aTmhcJp+AN75Xq9S1K2vYHuErHTI48uzdX8Ve6NAKmJLF+c2MBShRNbHHib zEy5tjmAC5C1IW29yYSdYBZnGWKzkPPBssM3UJOz3TVk6+/Z9+B4Mjv/u1AGI5NutE /643+We1nvOFlB0LnbYkOhVLfxUALGc+3HOqD3jTjwzjkHt+e6Q+TcOVjMkkRD5LzJ hkTog+p8XmsLQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Sun, 18 Jun 2023 00:15:27 +0800 Message-Id: <20230617161529.2092-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y += allwinner subdir-y += sifive subdir-y += starfive +subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..4b0249ac710f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..a1248b2ee3a3 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Sat Jun 17 16:15:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 693714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24C4DEB64D9 for ; Sat, 17 Jun 2023 16:28:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234005AbjFQQ17 (ORCPT ); Sat, 17 Jun 2023 12:27:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232486AbjFQQ16 (ORCPT ); Sat, 17 Jun 2023 12:27:58 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F9026AA; Sat, 17 Jun 2023 09:27:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 41F2960F76; Sat, 17 Jun 2023 16:27:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 334E4C433C0; Sat, 17 Jun 2023 16:27:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1687019244; bh=15h31Gq485ARLyon5H9bm78eqGG5GpNtnkp3TJY8+4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bUcCSHlXWz8OFVrESwROBhwI5K2nR0kk3xQ1Y0ggV+4bN2ztD8fjNnx+lOC9QoLja 2EcFpI6AFbr8WK290wnO6rYD+tNSbFhScpf39CJQGF1J9X5ZScD/wVutAcsFtIq1bg GDIxqZ4cKpbgNQVFI0mkTXZUZKWi1gIO9Ih2YTI4IY+052KxIN5gr+6FJdz06DUkt7 o3oVmfhkIXPpBYp9jlc6PWHIGqZkx4Pu7dlrRg0lQxKEK094ViP98LUeeM888vAlnQ r0x3Gw/XwFtfMQs2YwjH6voAy9g/mTY999c+5mUScETLEt5jVm9c+uYQGr4uosMr9a WJSPTCjEMg4IQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley , Palmer Dabbelt Subject: [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Date: Sun, 18 Jun 2023 00:15:29 +0800 Message-Id: <20230617161529.2092-9-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org> References: <20230617161529.2092-1-jszhang@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Guo Ren --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..109e4b5b003c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_THEAD=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y