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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v3 01/28] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Date: Sun, 2 Jul 2023 20:42:19 +0300 Message-Id: <20230702174246.121656-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the previous generation of Qualcomm CPUs, 32-bit Krait-based platforms. It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for the Krait-specific 'operating-points-v2-krait-cpu' compatibility string and the relevant opp-microvolt subclasses properties. The listed opp-supported-hw values are applicable only to msm8996 / msm8996pro platforms. Remove the enum as other platforms will use other bit values. It makes little sense to list all possible values for all the platforms here. Acked-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index bbbad31ae4ca..4e84d06d5ff9 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -26,7 +26,9 @@ description: | properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu nvmem-cells: description: | @@ -63,14 +65,16 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x9, 0xd, 0xe, 0xf, - 0x10, 0x20, 0x30, 0x70] + + Other platforms use bits directly corresponding to speedbin index. clock-latency-ns: true required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + required: - opp-hz From patchwork Sun Jul 2 17:42:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 281EEC10F1A for ; Sun, 2 Jul 2023 17:43:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229937AbjGBRnU (ORCPT ); Sun, 2 Jul 2023 13:43:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229914AbjGBRm4 (ORCPT ); Sun, 2 Jul 2023 13:42:56 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBFFCE67 for ; Sun, 2 Jul 2023 10:42:51 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b6985de215so58131441fa.2 for ; Sun, 02 Jul 2023 10:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319770; x=1690911770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=UnZ2EeIOMor8MF3RgMKQhgfr88ixPLYRFeEQTc3XlNSbIHNKbh5KbtUjhqCaT4H0ZH HD72Voo78r0CFislftQQbNDJWBhh/HSosy4FxDdThlZAHBGixrhImAoVDcxTSysyDgGr ENs5LbhIphdi4VfL2JKvWqBx7Q8qgrIYBPwvRI68tXY39XNnmokzKUXlxh1VWjr5yWJe 2KkO48ZbpFckwjzfH/r/bIxkiJSllaUaEuKKBW2Ti7sDehExQzfHP7KiZjqY4hnADTbA RwOTbepXYmIkzrwBoyirdlStqHAGgQgMxLVcxFZ3S40s3WRQdv3QBOkk5H0Pf4G99WSo L9Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319770; x=1690911770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=CuQgszWPiszY0BQou971V0rGdwsMq4jrOzWcycNQED1dj3evZ5wavzyEKAosBgVOIh ly0/y2sEKf3mSg3uqzBSWrxXrQ9zko4DfPmzubTXWSeV1k3+5aDmnVIxSxUp1ZgdlaTO DylL29MFm7lWqhMiGCthmUApxxb9cePg7oEUFplHPk8muJahfSc0KUusiSRTUvEg14Oz KBKYsFgdEAfYK13lKEToML7lRNkHWZJ1HdmBGbaH/3+2T82sXuk7iAHPwHxm4EoSPD57 ELLr6Y3bGuyL0mNG80wuAhuj0/+hpSJA53Tiakwbtob/LHxZLmbUknf8KawgYU+opSdX Hadg== X-Gm-Message-State: ABy/qLbSm22/aA/OVq4xB5MiS0kw154zEIO7RIVTB++vh/wppSZ23/Nu gJT9CMKI1TX900sfV5wZNpu8FQ== X-Google-Smtp-Source: APBJJlFDH1vJEF+OsK08052b2O0TS+CJMxpqf88xFXqijxVs/38/p8oT4vlayEUUDFHpNgDPiaZVGw== X-Received: by 2002:a2e:91ce:0:b0:2af:25cf:92ae with SMTP id u14-20020a2e91ce000000b002af25cf92aemr6098681ljg.22.1688319770010; Sun, 02 Jul 2023 10:42:50 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v3 02/28] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Date: Sun, 2 Jul 2023 20:42:20 +0300 Message-Id: <20230702174246.121656-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. The regulator property is retained as is. It will be changed in the later patches. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++-- 2 files changed, 20 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 64% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..84b3f01d590c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,25 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: @@ -34,8 +41,15 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + type: boolean + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible From patchwork Sun Jul 2 17:42:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E92C0502B for ; Sun, 2 Jul 2023 17:43:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229707AbjGBRnS (ORCPT ); Sun, 2 Jul 2023 13:43:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229901AbjGBRmy (ORCPT ); Sun, 2 Jul 2023 13:42:54 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B86FBE6B for ; Sun, 2 Jul 2023 10:42:52 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b6b98ac328so54316041fa.0 for ; Sun, 02 Jul 2023 10:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319771; x=1690911771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=DPMhhKcZnrCduJPLNWHXheMbw7Qk2BfD0Mvx5n4qijgodlZFH85ezf1bROG6mH1wtf +JHLyWt3bKfN+I7tNR8bXCzAbileB0OoYtqC7BsDb1oPlHfW3gcgu5v0PajvfQEtsBRG P7NnagoCNXmvYRlmgXowc+V2hu6Rt3pGyHxWljqrziuxfv5IHsQQRC1I+onZVN2/FXyk vcmLLmoQ849XjqvLKfLF6JR7GGeltkEGJTEg8wub3V3BDy+zcVUdkIbfDjsPDEpaIgBb YuX6P/kIz5SpXfqvJev+KJMZ8SmPnyqhufhHb52gVA+gfCkJ2OqQmMKYLKUuUqI0y8DO G9Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319771; x=1690911771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=JXzKm24uGBhScp91qfKP78blPOSwypM9ertttQ3YqabkgGEUpQG/m0hzQAHKAcxtsv EU1dq0j/m3XIF7hyTMIDecs0MOQyWczWVHCNo928PAlSMF+4pYPa/se2F+1rCQf3P+ND +KgdR2Wac1deihhq2uKvoeNbr+BHZIUUSJ/yxwtsB4JII8uYm1Nat4PwwfvA9+vMv0Lf wPmbgJ628zsriikHGzc5wRtHabtoAjLAnDZF586rhTQnWYvNrp5PSj126hiodAJGWm6p SD2sGtTbBQbXi8z2KQoy/pwhKTdlr0ao0VkaUbL2v5RswTZHkEKgATi9rO9I3urFlGiu TL6g== X-Gm-Message-State: ABy/qLbSAvxsdRNemWws05ORVG6ww4LLz0r47SHQ9VKeSnFT2zwB3Pr7 cHjE7DY4oxHzSExKGdaa7qHbMw== X-Google-Smtp-Source: APBJJlGPpV/Nu2PasXCj/Q9XCsLgZPwbLMR/bJ2WY4I57bygugelB6693qEcO8IQs5TtREEuiX7Kow== X-Received: by 2002:a2e:9d03:0:b0:2b6:e623:7b57 with SMTP id t3-20020a2e9d03000000b002b6e6237b57mr897118lji.25.1688319770837; Sun, 02 Jul 2023 10:42:50 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:50 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v3 03/28] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Sun, 2 Jul 2023 20:42:21 +0300 Message-Id: <20230702174246.121656-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..a2d871ba8c45 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,7 +47,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -96,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v3 04/28] dt-bindings: clock: qcom, krait-cc: Krait core clock controller Date: Sun, 2 Jul 2023 20:42:22 +0300 Message-Id: <20230702174246.121656-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define bindings for the Qualcomm Krait CPU and L2 clock controller. This device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is represented as the interconnect to facilitate L2 frequency scaling together with scaling the CPU frequencies. Acked-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- include/dt-bindings/clock/qcom,krait-cc.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h new file mode 100644 index 000000000000..9d181873c414 --- /dev/null +++ b/include/dt-bindings/clock/qcom,krait-cc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H + +#define KRAIT_CPU_0 0 +#define KRAIT_CPU_1 1 +#define KRAIT_CPU_2 2 +#define KRAIT_CPU_3 3 +#define KRAIT_L2 4 + +#endif From patchwork Sun Jul 2 17:42:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0A70C05053 for ; Sun, 2 Jul 2023 17:43:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229928AbjGBRnT (ORCPT ); Sun, 2 Jul 2023 13:43:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229937AbjGBRm5 (ORCPT ); Sun, 2 Jul 2023 13:42:57 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 642EAE69 for ; Sun, 2 Jul 2023 10:42:54 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b6a0d91e80so58080661fa.3 for ; Sun, 02 Jul 2023 10:42:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319772; x=1690911772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P6IQl2jydqEVzMHgyvXGKi5dP1nmhqYFToeW0usGn04=; b=t3krUNGgPtG8KhJZgAOluB5qNbULkHrsggCGWOE3+9WkK/Nke8uZExATygIMC5eQr8 51lm7CQ7oTP88c2nBhVE6Pennr1wfbTKKtrgJxEGkiWlBm3k5J0hMWXS45LfdiZZgz/B cZHfzR8C5KdvJe7ja0DU0HzrY+XlI0Y612i9PLs+dwqoDLoCd8vcKdC7TnYdjsEn38H9 GN4lG7GZYZxMIkjnFMZvW3izmfoPD0NrWBM3CQMOm5G3TBnVjemcVFdugkxwSrq+LZsh q57FEDVUgzpdBuKrBCyyU2+J2Co7wLq+7/mTTcyCRBF0Duz6Un2tiHoA876jZpkD0jNM en0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319772; x=1690911772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P6IQl2jydqEVzMHgyvXGKi5dP1nmhqYFToeW0usGn04=; b=kW052qRhYkSw0i3Y0s86zRq8LkBp9GYFz+jlLYt2clhSVWN2QCRiDfKxrtszcvdexJ +IdSHRqp/rBOuPH5Wlnlgc8dp/DfWBBEpF712J36r1UUC+CEQiGgzoyRNAvu40jV3ZFo 5GjP5joSra0GIOrJWGW6QcvCRUUK2zpJCOT+jXNiJkZgA4vVS9P6LoFLwAm4/Qwun2Jo OsfWFDAUse5UjUd2rTINPxueoSuIgUHcV25vmE0zkTi29rALPnXW4S0xyP9q/NKm08Q3 ex3h61GyB9Urfhb+Ns1lqFB5ebzGf6A+pDJOELbbIsDcHpfIajJ+/vL24VuQ7wInrWOq Wmxg== X-Gm-Message-State: ABy/qLbapynfCQthMlrWai4vm3UlckdYTvb/Dkdo1U2LroUPEBMvoRnl ATAWMyNWcCMWf6quaEpindcTzQ== X-Google-Smtp-Source: APBJJlFS99hCzi3mAHUe1l02+2XjqYaJe00YvrgpaEEhLTYEwQtg5DIyyxbRohMVrZXBCGGoRP94GQ== X-Received: by 2002:a05:651c:105a:b0:2b6:d8d4:15b with SMTP id x26-20020a05651c105a00b002b6d8d4015bmr2924331ljm.26.1688319772599; Sun, 02 Jul 2023 10:42:52 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:52 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 05/28] dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms Date: Sun, 2 Jul 2023 20:42:23 +0300 Message-Id: <20230702174246.121656-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The L2 cache device on Qualcomm Krait platforms controls the supplying voltages and the cache frequency. Add corresponding bindings for this device. Signed-off-by: Dmitry Baryshkov --- .../bindings/cache/qcom,krait-l2-cache.yaml | 75 +++++++++++++++++++ include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++ 2 files changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h diff --git a/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml new file mode 100644 index 000000000000..1dcf8165135b --- /dev/null +++ b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait L2 Cache + +maintainers: + - Bjorn Andersson + +description: + L2 cache on Qualcomm Krait platforms is shared between all CPU cores. L2 + cache frequency and voltages should be scaled according to the needs of the + cores. + +allOf: + - $ref: ../cache-controller.yaml# + +properties: + compatible: + items: + - const: qcom,krait-l2-cache + - const: cache + + clocks: + maxItems: 1 + + '#interconnect-cells': + const: 1 + + vdd-mem-supply: + description: suppling regulator for the memory cells of the cache + + vdd-dig-supply: + description: suppling regulator for the digital logic of the cache + + operating-points-v2: true + opp-table-l2: true + +required: + - compatible + - cache-level + - cache-unified + - clocks + - '#interconnect-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + l2-cache { + compatible = "qcom,krait-l2-cache", "cache"; + cache-level = <2>; + cache-unified; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + clocks = <&kraitcc 4>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table-l2 { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + }; + }; +... + diff --git a/include/dt-bindings/soc/qcom,krait-l2-cache.h b/include/dt-bindings/soc/qcom,krait-l2-cache.h new file mode 100644 index 000000000000..c9a38d368111 --- /dev/null +++ b/include/dt-bindings/soc/qcom,krait-l2-cache.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H +#define __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H + +#define MASTER_KRAIT_L2 0 +#define SLAVE_KRAIT_L2 1 + +#endif From patchwork Sun Jul 2 17:42:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C568C0015E for ; Sun, 2 Jul 2023 17:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229947AbjGBRnV (ORCPT ); Sun, 2 Jul 2023 13:43:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229950AbjGBRm6 (ORCPT ); Sun, 2 Jul 2023 13:42:58 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AFB8E6C for ; Sun, 2 Jul 2023 10:42:55 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b5c231f842so54007441fa.2 for ; Sun, 02 Jul 2023 10:42:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319773; x=1690911773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=39CekJt2bg+dTnou8ZXeVeRak2YiAVNMpxW8X6GTBtU=; b=SYaLI0sRwYzEXv1YOqBHrHz5jHOXzvMDYIVWjpHumY8xNxwg0rESkWXjs+1bpBsm5w MFWPKjo8CIPTQKu9SvQWOHi7Kn9tAbgyoZGU84T/BnlSV3Ya1s+QlJ1pVXS+LzYQPNwC 0YoXdi/P+8ry5sxfcmSJyv8LjPrRUIwp3m3ztRWCm7dl/jWS3Ql1SQfxxw+QFnXeV4tX hTDtELrxeP005G1EX3Owk4nJlswwruLGXGFGbtkyRUOqJT2QXKX/Op+kMQGT9OJr5alE KOJounmL+Kbo89ffdRzP6sksOEHTMRwjYoTnkVoprhqwU+h255kvWI4Qmurl+j6okOX7 A15w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319773; x=1690911773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=39CekJt2bg+dTnou8ZXeVeRak2YiAVNMpxW8X6GTBtU=; b=dDNbj9uARVmnFsrtAjqAB4FtJgmGDfummUDMxoNHh2/PC0iMNcNXoHKiCiuczU9BZE y8HTq2spOwf9OOvBgQpTUhd+iHbNIm7Dwjq62ZGSiKVG8JpJygfqlHfFnPoV+L4bwjQB aMdvDuSYNxqu8va6zq9nXW2VzZoVdsJyXAl2V7VGqDgHrJOARThMo33t5ftB14qT4yER u5GHNkhqj8ua4ZSxHzgRpbfSpjct7hDzheh5BXCo+mK/2PNI0ZJ6kNux0xcrG3pp1IZf IfLfAixhWPMJij2PFIYwHrPnPpQXJpQLOpRAuu/S0JonrBpY8fpzAo4YNtb31dtT3OJw RS/g== X-Gm-Message-State: ABy/qLbXA5HvwbhEg/seDcKJSCN4Bu73xk6uVl9Qj7ZYGmo/U3A+dknJ K0NlNmlb+eQ3Gas3FeOlDhbSwg== X-Google-Smtp-Source: APBJJlFns2ZlWmvV1ijFsjEvZawVgLE8JsepTypFQwk9MsQcbGqyIUh1LeVAE9vplaO3AyKKCEcGlA== X-Received: by 2002:a2e:800b:0:b0:2b4:7380:230 with SMTP id j11-20020a2e800b000000b002b473800230mr5268977ljg.13.1688319773490; Sun, 02 Jul 2023 10:42:53 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:52 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 06/28] interconnect: icc-clk: add support for scaling using OPP Date: Sun, 2 Jul 2023 20:42:24 +0300 Message-Id: <20230702174246.121656-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Sometimes it might be required to scale the clock using the OPP framework (e.g. to scale regulators following the required clock rate). Extend the interconnec-clk framework to handle OPP case in addition to scaling the clock. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/icc-clk.c | 13 +++++++++++-- include/linux/interconnect-clk.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index 4d43ebff4257..c7962acdcee7 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -7,10 +7,13 @@ #include #include #include +#include struct icc_clk_node { + struct device *dev; struct clk *clk; bool enabled; + bool opp; }; struct icc_clk_provider { @@ -25,12 +28,16 @@ struct icc_clk_provider { static int icc_clk_set(struct icc_node *src, struct icc_node *dst) { struct icc_clk_node *qn = src->data; + unsigned long rate = icc_units_to_bps(src->peak_bw); int ret; if (!qn || !qn->clk) return 0; - if (!src->peak_bw) { + if (qn->opp) + return dev_pm_opp_set_rate(qn->dev, rate); + + if (!rate) { if (qn->enabled) clk_disable_unprepare(qn->clk); qn->enabled = false; @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst) qn->enabled = true; } - return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw)); + return clk_set_rate(qn->clk, rate); } static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak) @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev, icc_provider_init(provider); for (i = 0, j = 0; i < num_clocks; i++) { + qp->clocks[i].dev = dev; qp->clocks[i].clk = data[i].clk; + qp->clocks[i].opp = data[i].opp; node = icc_node_create(first_id + j); if (IS_ERR(node)) { diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h index 0cd80112bea5..c695e5099901 100644 --- a/include/linux/interconnect-clk.h +++ b/include/linux/interconnect-clk.h @@ -11,6 +11,7 @@ struct device; struct icc_clk_data { struct clk *clk; const char *name; + bool opp; }; struct icc_provider *icc_clk_register(struct device *dev, From patchwork Sun Jul 2 17:42:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50F9DC16B13 for ; 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Sun, 02 Jul 2023 10:42:54 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:53 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 07/28] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Date: Sun, 2 Jul 2023 20:42:25 +0300 Message-Id: <20230702174246.121656-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The krait-cc driver still uses struct clk internally. Rewrite it to allocate and register struct clk_hw instead. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/krait-cc.c | 141 ++++++++++++++++-------------------- 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 410ae8390f1c..a37abbd31f50 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -13,17 +13,9 @@ #include #include -#include "clk-krait.h" - -enum { - cpu0_mux = 0, - cpu1_mux, - cpu2_mux, - cpu3_mux, - l2_mux, +#include - clks_max, -}; +#include "clk-krait.h" static unsigned int sec_mux_map[] = { 2, @@ -235,7 +227,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s .parent_data = p_data, .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }; struct clk_hw *clk; char *hfpll_name; @@ -324,19 +316,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux return pri_mux; } -static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -{ - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - - if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return clks[idx] ? : ERR_PTR(-ENODEV); -} - static const struct of_device_id krait_cc_match_table[] = { { .compatible = "qcom,krait-cc-v1", (void *)1UL }, { .compatible = "qcom,krait-cc-v2" }, @@ -344,60 +323,84 @@ static const struct of_device_id krait_cc_match_table[] = { }; MODULE_DEVICE_TABLE(of, krait_cc_match_table); +static int krait_clk_reinit(struct clk_hw *hw, int cpu) +{ + struct clk *clk; + unsigned long cur_rate, aux_rate; + char name[5]; /* CPUn */ + + if (cpu == -1) + strcpy(name, "L2"); + else + snprintf(name, sizeof(name), "CPU%d", cpu); + + clk = clk_hw_get_clk(hw, clk_hw_get_name(hw)); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + aux_rate = 384000000; + + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { + pr_info("%s @ Undefined rate %lu. Forcing new rate.\n", + name, cur_rate / 1000); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); + pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000); + + clk_put(clk); + + return 0; +} + +/* Krait configurations have at most 4 CPUs and one L2 */ +#define KRAIT_NUM_CLOCKS 5 + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; + int cpu, ret; + struct clk_hw *clk; + struct clk_hw_onecell_data *clks; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1); if (IS_ERR(clk)) return PTR_ERR(clk); if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); + clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2); if (IS_ERR(clk)) return PTR_ERR(clk); } - /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL); if (!clks) return -ENOMEM; + clks->num = KRAIT_NUM_CLOCKS; + BUILD_BUG_ON(KRAIT_L2 >= KRAIT_NUM_CLOCKS); + for_each_possible_cpu(cpu) { - mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(mux)) - return PTR_ERR(mux); - clks[cpu] = mux->clk; + clk = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[cpu] = clk; } - l2_pri_mux = krait_add_clks(dev, -1, id->data); - if (IS_ERR(l2_pri_mux)) - return PTR_ERR(l2_pri_mux); - clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init - * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the - * refcount of these clocks. Any cpufreq/hotplug manager can assume - * that the clocks have already been prepared and enabled by the time - * they take over. - */ - for_each_online_cpu(cpu) { - clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } + clk = krait_add_clks(dev, -1, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[KRAIT_L2] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -410,31 +413,13 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { - pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } + krait_clk_reinit(clks->hws[KRAIT_L2], -1); + for_each_possible_cpu(cpu) + krait_clk_reinit(clks->hws[cpu], cpu); - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); + if (ret) + return ret; return 0; } From patchwork Sun Jul 2 17:42:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D043EC0015E for ; Sun, 2 Jul 2023 17:43:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229984AbjGBRnY (ORCPT ); Sun, 2 Jul 2023 13:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbjGBRm7 (ORCPT ); Sun, 2 Jul 2023 13:42:59 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19D31E6A for ; Sun, 2 Jul 2023 10:42:57 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2b6adef5c22so55947121fa.3 for ; Sun, 02 Jul 2023 10:42:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319775; x=1690911775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bK8WPsZQis5KBu/8sVzWIZ3oMBJ8zoaGC76tJyGSV0I=; b=FXHb7zM8rJO/E+7tVzZGPsJMPoCnqfzWIaIl/7yWAOoC3mW/5SLys0l978waAqzF9+ 5xCdRg4RIcc5P6gQMzqc94cGv3je/ZDZuVlcYITCt8UMidS3p/ENarNjqUe4xuMQXiHh /8MUxUMsBtp6i1+M42rlBV4QEdOlNmenk3dQJ7Zv1fpkExzI0GGRonJRdTFqCtSoMX8X IFrYYftXKOQOCdldNvNTzEO8tDKQFqdCy5bZydS1IXKovR4b0Gim3eyR9fbfJjXi/AMG eUj0ACVEJ+B/aLo2/1E4gDWZIqgeSm2U+kjVg4E8PJVDIPStNOKUvIq7HqkkH9qOeEET NohQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319775; x=1690911775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bK8WPsZQis5KBu/8sVzWIZ3oMBJ8zoaGC76tJyGSV0I=; b=KnHojwm63HTmlLvXyZl0rXWSQZOWnBAEIfGy+pc0wuiYfmXt8JRox2Zgf091OTHGfT Ww71Ln6bDw1sVBdpMAvDj96A1TOjOt+WItMxmvWRijJXp0PLz4kt/8oWyOfrm6WxFYBQ LfGJh+DV4rkVGnk7gJNREPZYuMd/RKwlhOLPY5/FjYsgdqoJP0GLv/lOS4qw+9o2cpOs d536UuL53S8EHudZduV24CWNgVuVysb0gk+OR8ucUDbZ4SasCi2OR6Y/4BUHTPbQlCjT 28trlcktvOtcVA5t4pdGDtOHTQafq906yVSL/V2wXFVQaAmX6ezTifUCk75de/u0F71V 70MA== X-Gm-Message-State: ABy/qLb23nSs4XavxNC5xovD3Cd3HU2AicXkzfmScZAFcYS2Mn507BP2 GhOta3ju9lvAwgKoHHddXkElDA== X-Google-Smtp-Source: APBJJlGF/BMevvwYJuT2W41j7gotm6RZd7WYOC74DkFnCURRwnfcN6FK/LjQMwtye33AX64BGuWzwQ== X-Received: by 2002:a2e:9dc8:0:b0:2b6:d603:7667 with SMTP id x8-20020a2e9dc8000000b002b6d6037667mr4662751ljj.8.1688319775317; Sun, 02 Jul 2023 10:42:55 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:54 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 08/28] soc: qcom: spm: add support for voltage regulator Date: Sun, 2 Jul 2023 20:42:26 +0300 Message-Id: <20230702174246.121656-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++- include/soc/qcom/spm.h | 9 ++ 2 files changed, 212 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index a6cbeb40831b..3c16a7e1710c 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -9,19 +9,31 @@ #include #include #include +#include +#include #include #include #include #include #include +#include #include #include +#include +#include #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MIN_VLVL (0x3f << 10) +#define SPM_AVS_CTL_MAX_VLVL (0x3f << 17) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -31,10 +43,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vlevel = drv->volt_sel; + unsigned int vctl, data0, data1, avs_ctl, sts; + bool avs_enabled; + + vlevel |= 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, 0xff, vlevel); + data0 = FIELD_SET(data0, 0xff, vlevel); + data1 = FIELD_SET(data1, 0x3f, vlevel); + data1 = FIELD_SET(data1, 0x3f << 16, vlevel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = vlevel & 0x3f; + unsigned int min_avs = max(max_avs, 4U) - 4; + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, tie it to CPU0 */ + + return 0; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + drv->reg_cpu = spm_get_cpu(dev); + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..9859ebe42003 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -30,11 +30,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; void spm_set_low_power_mode(struct spm_driver_data *drv, From patchwork Sun Jul 2 17:42:27 2023 Content-Type: text/plain; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 09/28] cpufreq: qcom-nvmem: create L2 cache device Date: Sun, 2 Jul 2023 20:42:27 +0300 Message-Id: <20230702174246.121656-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Scaling the frequencies on some of Qualcomm Krait platforms (e.g. APQ8064) also requires scaling of the L2 cache frequency. As the l2-cache device node is places under /cpus/ path, it is not created by default by the OF code. Create corresponding device here. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a88b6fe5db50..ab78ef1531d0 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -380,6 +380,7 @@ static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; + unsigned int cpu; int ret; if (!np) @@ -390,6 +391,25 @@ static int __init qcom_cpufreq_init(void) if (!match) return -ENODEV; + for_each_possible_cpu(cpu) { + struct device *dev = get_cpu_device(cpu); + struct device_node *cache; + struct platform_device *pdev; + + cache = of_find_next_cache_node(dev->of_node); + if (!cache) + continue; + + if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) { + pdev = of_platform_device_create(cache, NULL, NULL); + if (IS_ERR(pdev)) + pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev); + /* the error is not fatal */ + } + + of_node_put(cache); + } + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; From patchwork Sun Jul 2 17:42:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44FE3C00528 for ; Sun, 2 Jul 2023 17:43:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230011AbjGBRn0 (ORCPT ); Sun, 2 Jul 2023 13:43:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230016AbjGBRnA (ORCPT ); Sun, 2 Jul 2023 13:43:00 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08D44E6B for ; Sun, 2 Jul 2023 10:42:59 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4fba03becc6so3933529e87.0 for ; Sun, 02 Jul 2023 10:42:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319777; x=1690911777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dGUrC2pl70yT5xQt6wVBykOBcOL77JFwxDC19zavIJE=; b=SbMKmAN6L3laP/Q+yqMD9pDXoUK0I9x3KGVs7YaDx95yNQWJYsHovMxRdkCJ0q84Ak Lt504z0PNaogYQcD7+wiCRU+rmJJL24JrILUGxduTRnucFW2eIShGBI+weK6mgRe5hEO FjwfAjyOmmKgog6lRxnRPjR1g+7MeKPs956FMLLNRKbm18HaSGr6xnEnwY6aSo9rpzbk o1noJfZK/x7Hait5MStEEmyh8fk0hH0ySO6R9EHeTeIIifR/DrFEzWLX9eRLPS/FEv+b d3Vp+Xw57tK/Q+XjVlI+xS2zl67Mt8ZcBI/PMdfmfGWiZd9dGYLuB8XJpxDyVdkBz4xQ zeAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319777; x=1690911777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dGUrC2pl70yT5xQt6wVBykOBcOL77JFwxDC19zavIJE=; b=dj3ZSt4z5T9FpDWS9kdmJ1ofx3lRwzk4rqZyPabyfTCnUVVgqzzijc6u+mEadQt4oI 4lyX4CjmaEIXUae7dvslAqDRvmOdiogCzL9QKn9b98KYabqErU7IGh3Zp50LPaKTbwPG rQgkaNNRlJ37d3IuK752V+IZf7iovGcC8Ayo4pmWYkfa0MuniGpM8S4h5NacBZoo0YU1 okK3ucLlvWcoicM5GnfouYNCFOPg9vGox99wGVOwezuXPnnL3bLMe9CVjIaSZ9mSSqjO 9njdopkUJk0zYX2Okx37NVyr32JL3yjJhsk4EXjLcWwdInrCfRCgVd6m1TOPtyxsWIB5 jkYg== X-Gm-Message-State: AC+VfDwR9WJpQnpkxrmqji11uo6Gt0bYnZwODdHvjkPAc7MKtBUzLfMl HYaIeOTrkFrV/x2FoR70IwbQcA== X-Google-Smtp-Source: ACHHUZ4+y/HVTKombqOaLWkQitZBYp37GDvg0uFWAUBBRf/wR6jT3yGk2FBESSJq9VA/W8klWwTx7w== X-Received: by 2002:a05:6512:110a:b0:4f6:2cf9:f57d with SMTP id l10-20020a056512110a00b004f62cf9f57dmr3569702lfg.2.1688319777193; Sun, 02 Jul 2023 10:42:57 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:56 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 10/28] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Date: Sun, 2 Jul 2023 20:42:28 +0300 Message-Id: <20230702174246.121656-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo (newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for 'operating-points-v2-krait-cpu' compatibility string. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index ab78ef1531d0..3bb552f498da 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || + of_device_is_compatible(np, "operating-points-v2-krait-cpu"); if (!ret) { of_node_put(np); return -ENOENT; From patchwork Sun Jul 2 17:42:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2752FC001DF for ; Sun, 2 Jul 2023 17:43:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229649AbjGBRnZ (ORCPT ); Sun, 2 Jul 2023 13:43:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230018AbjGBRnB (ORCPT ); Sun, 2 Jul 2023 13:43:01 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6B1BE48 for ; Sun, 2 Jul 2023 10:42:59 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2b6985de215so58132211fa.2 for ; Sun, 02 Jul 2023 10:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319778; x=1690911778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WXVJ11On9toxIViZ54BypO57RSh7CGGU2NLYyrjlwHQ=; b=fz/wveKBifo3+3GcZUIZ1YmZ/tcJ+q8r5HLocLOc3E7z62aBjswi12CIexGASWBBhV G8O0aeiriCNfJBSM+XJ1HI8BQ2wb9Vq7s/EWxmrkARoRM018w3FjZRwnA1HuYPPW16TE OOPXtrHMtVbjDX+5SywrGrpsOxEYm+jDySTYdhNN1D5dIPNvu+dze1MVwiT3pOCuF7sC qxT82stCasTbi9lDwmP9KgTesZId66Oxg2hLtNo4QJK40vKmVo8AHsKxInGNrKFbXH6/ j+bEnDHS/QlgCFEv5SLkqxQxPNK0oYuYU3rTPy5Ajhz1QIeoh6HTz+0ShS0OBeCV4jyW /9aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319778; x=1690911778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WXVJ11On9toxIViZ54BypO57RSh7CGGU2NLYyrjlwHQ=; b=juMccZj9BVpUQpg2Mro4waZNTJBHDSLH0wAhDAltzMKEDAFJFLqnSfHVaEjB9Exd3m UWylc49yyysqZPr8R56jY5H2EIl6Ab8TPDJ71B1USOLRE1TXIKOXQPrbS6vBwK2uxO3+ 5CPdvlJhtkyJ3iSYKfrKbWA8AOpDLyVOFFadqO67XDHxUBa+csqNiBa6XY45Dc4SNVJT 5rkjTs7RX4SL3rQUGsZUDgJmHa1A/bnq4EhPvIWOjJqVQYxDx0qKsqIr38lmZSKcZGXJ +kp1ZqggKIheQLaYFzXQN/HN0KV0sMv16tCyBKMugIkoLOj8/a8VMTWNF+JvGQcOO8S1 Lmmg== X-Gm-Message-State: ABy/qLbRnNKUdqEdaEZoLbNX+/wn9huXtQ6etcB+212lmRXd9OKCvAAG Ks0uDaFIqQY7o2pKxMBd08ySCA== X-Google-Smtp-Source: APBJJlEJR3sBwvgTvB3ooLaltJOA0PLAuNXu+Bdgl44EHC37hVods1INTAbmkVn/7UYBi/l/7/hwuw== X-Received: by 2002:a2e:7803:0:b0:2b6:b85d:b48c with SMTP id t3-20020a2e7803000000b002b6b85db48cmr5251352ljc.28.1688319778028; Sun, 02 Jul 2023 10:42:58 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:57 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 11/28] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Date: Sun, 2 Jul 2023 20:42:29 +0300 Message-Id: <20230702174246.121656-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The fuses used on msm8960 / apq8064 / ipq806x families of devices do not have the pvs version. Drop this argument from parsing function. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 3bb552f498da..792423590279 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -50,7 +50,7 @@ struct qcom_cpufreq_drv { static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; static void get_krait_bin_format_a(struct device *cpu_dev, - int *speed, int *pvs, int *pvs_ver, + int *speed, int *pvs, u8 *buf) { u32 pte_efuse; @@ -181,8 +181,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, switch (len) { case 4: - get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, - speedbin); + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); break; case 8: get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver, From patchwork Sun Jul 2 17:42:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1273C04FE0 for ; Sun, 2 Jul 2023 17:43:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230020AbjGBRn1 (ORCPT ); Sun, 2 Jul 2023 13:43:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230028AbjGBRnC (ORCPT ); Sun, 2 Jul 2023 13:43:02 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5799183 for ; Sun, 2 Jul 2023 10:43:00 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2b5e7dba43cso57630771fa.1 for ; Sun, 02 Jul 2023 10:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319779; x=1690911779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9qDJV6KZlD2L8q+lvpBd+sQYG0dJyxpwpj9hrg9x4FU=; b=rmSskxAcWgN+iuIoaiuFI53lzHsrFV/8b05dxisx7ZACO/jsJGaGXHolhRkaePtOne 90opSZSPUvFSufJPb/q3siXavwC7hV/UnU18+vrV4Daj0uiEehLddqqrxMDzTu6KNLrn 23SD+V2fdtXCqr0mTEOBCVo+UaWEi0FVRoS8kWZH7bXKpy2pfGIw68PPN7bQi6dpp+OO PkPEXoZ4AnmQhNKAE9f4JUlwYE4GShZENw06nLHeGviSlJzw/uhM6HFAiWEYHrmVDghN hhvBU6IlS8O90/3mudQbMRdsCgVkyyv7TCBeWtc+GLNJmDCSiIg85olFq0WjqAdh2RXT uEPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319779; x=1690911779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9qDJV6KZlD2L8q+lvpBd+sQYG0dJyxpwpj9hrg9x4FU=; b=cxTjg4ZNWGvDLR1b8VzBlknbur2Y5rLe6aSuVdw/BUyaovZSaYFE89cHsm9KkqL0Pl edWn3EwPghflwqmdaYBC4hgATSpYABsVzpA/83Rf8j8MpaaoKBzWPHlqsgs8iqLH15B9 ANH15nGk9kKUestWh/eqBAI7urT4K2i5RHfTpWf+nZ9S55ON5zeNKLJTKZmXL8g67BRZ SkYOsd90qrFLzd2QvXmKLx1hF9kiCueAQtwS1ti2c6RXKq9hk5RBV2ATN4WB4LHu94M+ 4a1xQdRcevjAqHGhKxd30Rrvi6IToVQP/vl99wdI4gKQ+hNYuENzyhqsOHL1+baZDsQm hdJA== X-Gm-Message-State: ABy/qLYTmliiA2sgIGg3/VO1LL5Ovg6xv7nrCi9Tg8EsvoPYhBcB3JUc wPQnhpyeHG/gU7oS+55p1KDBtg== X-Google-Smtp-Source: APBJJlFbhE9Z5RbuoyTeBi5mlX2jiYDUTw/+JoDYyCHAkmkcZ87TP5EFx7HAiWcy9J0LWCY7hKLG0g== X-Received: by 2002:a2e:9d44:0:b0:2b6:df23:2117 with SMTP id y4-20020a2e9d44000000b002b6df232117mr2098665ljj.43.1688319779060; Sun, 02 Jul 2023 10:42:59 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:58 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 12/28] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Date: Sun, 2 Jul 2023 20:42:30 +0300 Message-Id: <20230702174246.121656-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APQ8064 can scale core voltage according to the frequency needs. Rather than reusing the A/B format multiplexer, use a simple fuse parsing function and configure required regulator. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 792423590279..422fd8ca8a00 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { char **pvs_name, struct qcom_cpufreq_drv *drv); const char **genpd_names; + const char * const *regulator_names; }; struct qcom_cpufreq_drv { @@ -203,6 +205,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + u8 *speedbin; + size_t len; + int ret = 0; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) + return -EINVAL; + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + drv->versions = (1 << speed); + + kfree(speedbin); + return ret; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -217,6 +247,16 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const char * apq8064_regulator_names[] = { + "vdd-core", + NULL +}; + +static const struct qcom_cpufreq_match_data match_data_apq8064 = { + .get_version = qcom_cpufreq_apq8064_name_version, + .regulator_names = apq8064_regulator_names, +}; + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -304,7 +344,12 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) config.virt_devs = NULL; } - if (config.supported_hw || config.genpd_names) { + if (drv->data->regulator_names) + config.regulator_names = drv->data->regulator_names; + + if (config.supported_hw || + config.genpd_names || + config.regulator_names) { drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); if (drv->opp_tokens[cpu] < 0) { ret = drv->opp_tokens[cpu]; @@ -363,7 +408,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, {}, From patchwork Sun Jul 2 17:42:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0360EB64D9 for ; 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Sun, 02 Jul 2023 10:42:59 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:42:59 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 13/28] soc: qcom: Add driver for Qualcomm Krait L2 cache scaling Date: Sun, 2 Jul 2023 20:42:31 +0300 Message-Id: <20230702174246.121656-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a simple driver that handles scaling of L2 frequency and voltages. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/Kconfig | 9 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/krait-l2-cache.c | 167 ++++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 drivers/soc/qcom/krait-l2-cache.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e597799e8121..01090b7a3c06 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,6 +70,15 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_KRAIT_L2_CACHE + tristate "Qualcomm Krait L2 cache scaling" + depends on ARCH_QCOM && ARM || COMPILE_TEST + select INTERCONNECT + select INTERCONNECT_CLK + default ARM_QCOM_CPUFREQ_NVMEM + help + The driver for scaling the L2 cache frequency on Qualcomm Krait platforms. + config QCOM_KRYO_L2_ACCESSORS bool depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 99114c71092b..cdd1cc96e9f9 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o +obj-$(CONFIG_QCOM_KRAIT_L2_CACHE) += krait-l2-cache.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o diff --git a/drivers/soc/qcom/krait-l2-cache.c b/drivers/soc/qcom/krait-l2-cache.c new file mode 100644 index 000000000000..c493da50ab65 --- /dev/null +++ b/drivers/soc/qcom/krait-l2-cache.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Random ID that doesn't clash with main qnoc and OSM */ +#define L2_MASTER_NODE 2000 + +static int krait_l2_set_one_supply(struct device *dev, + struct regulator *reg, + struct dev_pm_opp_supply *supply) +{ + int ret; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + return ret; + } + + return 0; +} + +/* vdd-mem and vdd-dig */ +#define NUM_SUPPLIES 2 +static int krait_l2_config_regulators(struct device *dev, + struct dev_pm_opp *old_opp, + struct dev_pm_opp *new_opp, + struct regulator **regulators, + unsigned int count) +{ + struct dev_pm_opp_supply supplies[NUM_SUPPLIES]; + unsigned long old_freq, freq; + unsigned int i; + int ret; + + if (WARN_ON_ONCE(count != NUM_SUPPLIES)) + return -EINVAL; + + ret = dev_pm_opp_get_supplies(new_opp, supplies); + if (WARN_ON(ret)) + return ret; + + old_freq = dev_pm_opp_get_freq(old_opp); + freq = dev_pm_opp_get_freq(new_opp); + + WARN_ON(!old_freq || !freq); + if (freq > old_freq) { + for (i = 0; i < count; i++) { + ret = krait_l2_set_one_supply(dev, regulators[i], &supplies[i]); + if (ret) + goto restore_backwards; + } + } else { + for (i = count; i > 0; i--) { + ret = krait_l2_set_one_supply(dev, regulators[i - 1], &supplies[i - 1]); + if (ret) + goto restore_forward; + } + } + + return 0; + +restore_backwards: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for (; i > 0; i--) + krait_l2_set_one_supply(dev, regulators[i - 1], &supplies[i - 1]); + + return ret; + +restore_forward: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for ( ; i < count; i++) + krait_l2_set_one_supply(dev, regulators[i], &supplies[i]); + + return ret; +} + +static int krait_l2_probe(struct platform_device *pdev) +{ + struct dev_pm_opp_config krait_l2_cfg = { + .clk_names = (const char * const[]) { NULL, NULL }, + .config_regulators = krait_l2_config_regulators, + .regulator_names = (const char * const[]) { "vdd-mem", "vdd-dig", NULL }, + }; + struct icc_clk_data data[] = { + { .name = "l2", .opp = true}, + }; + + struct device *dev = &pdev->dev; + struct icc_provider *provider; + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = devm_pm_opp_set_config(dev, &krait_l2_cfg); + if (ret) + return ret; + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return ret; + + data[0].clk = clk; + provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + platform_set_drvdata(pdev, provider); + + return 0; +} + +static int krait_l2_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_clk_unregister(provider); + + return 0; +} + +static const struct of_device_id krait_l2_match_table[] = { + { .compatible = "qcom,krait-l2-cache" }, + {} +}; +MODULE_DEVICE_TABLE(of, krait_l2_match_table); + +static struct platform_driver krait_l2_driver = { + .probe = krait_l2_probe, + .remove = krait_l2_remove, + .driver = { + .name = "qcom-krait-l2", + .of_match_table = krait_l2_match_table, + .sync_state = icc_sync_state, + }, +}; + +module_platform_driver(krait_l2_driver); + +MODULE_DESCRIPTION("Qualcomm Krait L2 scaling driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Jul 2 17:42:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45BEBC05052 for ; Sun, 2 Jul 2023 17:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230028AbjGBRn3 (ORCPT ); Sun, 2 Jul 2023 13:43:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230052AbjGBRnE (ORCPT ); Sun, 2 Jul 2023 13:43:04 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 908D1E6A for ; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 14/28] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Date: Sun, 2 Jul 2023 20:42:32 +0300 Message-Id: <20230702174246.121656-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index 1caa73e20bc9..1d6fb840dc60 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -213,9 +213,9 @@ pm8921_s1: s1 { bias-pull-down; }; - /* msm otg HSUSB_VDDCX */ + /* msm otg HSUSB_VDDCX and VDD_DIG */ pm8921_s3: s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -299,6 +299,12 @@ pm8921_l23: l23 { bias-pull-down; }; + /* VDD_MEM */ + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + /* * tabla2x-slim-CDC_VDDA_A_1P2V * tabla2x-slim-VDDD_CDC_D @@ -327,8 +333,12 @@ pm8921_lvs6: lvs6 { /* * mipi_dsi.1-dsi1_vddio * pil_riva-pll_vdd + * HFPLL regulator */ pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; }; From patchwork Sun Jul 2 17:42:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E1C4C25B4F for ; Sun, 2 Jul 2023 17:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230236AbjGBRnb (ORCPT ); Sun, 2 Jul 2023 13:43:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230064AbjGBRnE (ORCPT ); Sun, 2 Jul 2023 13:43:04 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A5B1E67 for ; Sun, 2 Jul 2023 10:43:03 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4fbb281eec6so339533e87.1 for ; Sun, 02 Jul 2023 10:43:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319781; x=1690911781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p35WnKMBrcXjWofFp1qaZzVTDzePQvr7csu2aCOqwqs=; b=Ex6Qty5NQA+OMe426tTOlQi9DdfvarRAeo3rNIPrebH+QWHcfuQ3akHy9RJ7IUAGWV PmGEt/22Xl4I/ypJ40OEW51nDANL2ceEFbTEohuXI8RwjzNjbNmgC0AGOYbL8vF4td05 h8g4If8E1+bkzQdn0majiXcMimpVixMAqeAeOJyet+QuR/xyyl9TA9eq30G5aJB0zClQ +pvgCJQ0l9kHtcAEay9JN0k0YNOBK6kgqA8euuI9LkGEaA5JjF8v+1FiBLVhzW7gjAUa aXj8pM/dObad9YJpyRPz6Oqry33mtLD52r/uuihhnRI4OaaZxMHlCo1p7ulk1azm3psT VuDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319781; x=1690911781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p35WnKMBrcXjWofFp1qaZzVTDzePQvr7csu2aCOqwqs=; b=bn8XHB0ZsDbRWPQhDE+u2R8D3T40aGlXg/5gMk7CYoLSjFit8TVyfbjMkcfvGe+zld n4YEslwJ5pQtrA3YHXgogpRgM/jqHqK/EHkkg7MuLkezpDzfvplG50xrEffgTO55M+hN zy5IqvQ+UCmarNHRM7uyWzUcNbIUf0tFd4BMejao7qFxNHQvT6FRtscnLh8KrmyFjYaA tJB9yJ1mhBtQmH6YtEqrtoj3/u5n+vZOcHwVN5gyIFdkWv8vwOEzfmOQb09cflN15inM KKZu2/upNB6zqGlIhSKirty+9RO9lPpj1bLrT2YEXXxGwLMQy1vOpfiY6tOzL9l/Yr4O CHtA== X-Gm-Message-State: ABy/qLYO1wnzPMmdxfvcaOmxKeNEVGJkg5tiTI5o1HgBAF19vvmT/Zke OObcJtjm8s6hBOb5e7sUhuvPoA== X-Google-Smtp-Source: APBJJlHfIYKPLytohmPzXYxo2iOKjkOvmbWAbnFRn3JksRlWN++KHH9xEYp3mxEfx8pweMNo1KS20Q== X-Received: by 2002:ac2:5e68:0:b0:4fb:8939:d95c with SMTP id a8-20020ac25e68000000b004fb8939d95cmr4930570lfr.30.1688319781653; Sun, 02 Jul 2023 10:43:01 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:01 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 15/28] ARM: dts: qcom: apq8064-cm-qs600: constraint cpufreq regulators Date: Sun, 2 Jul 2023 20:42:33 +0300 Message-Id: <20230702174246.121656-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts index 6472277d1c6d..ee0090e03fb3 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -106,8 +106,8 @@ pm8921_s1: s1 { }; pm8921_s3: s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -147,9 +147,23 @@ pm8921_l23: l23 { bias-pull-down; }; + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + pm8921_lvs6: lvs6 { bias-pull-down; }; + + /* HFPLL regulator */ + pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; }; From patchwork Sun Jul 2 17:42:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BBD7C25B5E for ; Sun, 2 Jul 2023 17:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230064AbjGBRnc (ORCPT ); Sun, 2 Jul 2023 13:43:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230082AbjGBRnG (ORCPT ); Sun, 2 Jul 2023 13:43:06 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FA3DE60 for ; Sun, 2 Jul 2023 10:43:04 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2b69923a715so56069421fa.0 for ; Sun, 02 Jul 2023 10:43:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319782; x=1690911782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aVBy+fu/oMsx5XODIGCyweQZPFV4UABvq1rgp87MeiY=; b=RX+rH5G1WUZGaR//tuDlRX+FJFXbMh3m6Ujuj4l8tGX8/3smocSEdl8ht0CbEneNaT A0bLIuEO3/TjdOJrCeQeMnCJtN0udUECQJ+mZYQ3TpkmnVgi4c0s3k78oYGnUrjp3fn8 Z2kYIUfzlG74abgGLWZAiyTAfdSR+QBE4tsBs/Y9g/NB44xiETCZILFsG0uJfUWj7btC TNagVopqCeWUhdloVhAWF2YoG//fPLKCOJYYD5ybQ4VFovSkBiHCtr1R3JYGX2SEqSMU 0qaMNus/col76aMdtjg/7E3ANbbysC/uTHRcoemkH/O9A43AbWDWOZ1YNt0idCTRfLyt rgvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319782; x=1690911782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aVBy+fu/oMsx5XODIGCyweQZPFV4UABvq1rgp87MeiY=; b=AmKD5pSLG+rAjCxSakd+8cf+VMScvRXiFjlPucrJZ8TU5SF6zzJw663lBsVEAaVFgZ +MaiiIBCf2/bUdE2wsMLnHUEZUigG0ogJGmsedptGs0Tdba14hrCWXxJRu99chbazjMy ZZ1WIaxbAxLnN80JQwzpXog5E7b8djEqAnFV2MuKcp7Lc/T8FHa0W4KM7mw9FlucGmt/ yI7YPXCDuB1N/V4T/CSG4/jZpMvSC0ha4vVwBScGXFb37Z34zHc5j7cE4HVZSnXVR0w3 0Nt4D+ghxpyqOd14lcYRfITKlugtYT5RJ6f3M377+os/5uuBn5C0LT5SrIucke/MDEFd q1Ow== X-Gm-Message-State: ABy/qLZMQcC0X/GXt3hmBY7VRzsNpYxfBVZiH6LIjrlCL35cH1ayPkDO pEwLmXiikoTSj9Nr9Idecc6tMw== X-Google-Smtp-Source: APBJJlFtVful/ALsf6VAFSukSaZBm0XeTZWD+E1XAmbrhkfCvDwrVQvb0aLBlqSvslgg/gfnMcbgRw== X-Received: by 2002:a05:651c:1055:b0:2b6:db9b:aadc with SMTP id x21-20020a05651c105500b002b6db9baadcmr2544246ljm.32.1688319782635; Sun, 02 Jul 2023 10:43:02 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:02 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 16/28] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators Date: Sun, 2 Jul 2023 20:42:34 +0300 Message-Id: <20230702174246.121656-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index 39c44fae9d14..ddb092710275 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -217,8 +217,8 @@ pm8921_s1: s1 { }; pm8921_s3: s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -264,6 +264,12 @@ pm8921_l23: l23 { bias-pull-down; }; + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + pm8921_lvs1: lvs1 { bias-pull-down; }; @@ -272,6 +278,14 @@ pm8921_lvs6: lvs6 { bias-pull-down; }; + /* HFPLL regulator */ + pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + pm8921_hdmi_switch: hdmi-switch { bias-pull-down; }; From patchwork Sun Jul 2 17:42:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADF24C25B74 for ; Sun, 2 Jul 2023 17:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjGBRnd (ORCPT ); Sun, 2 Jul 2023 13:43:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbjGBRnH (ORCPT ); Sun, 2 Jul 2023 13:43:07 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 269CFE5F for ; Sun, 2 Jul 2023 10:43:05 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2b699284ff4so58775691fa.2 for ; Sun, 02 Jul 2023 10:43:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319783; x=1690911783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HSVXLsNAShBJHVR9vMtlXCAILUdGmBkWDTfqBXPK0KY=; b=ZmcJGF6jZZmFSCd8ycbmcaHOGMQyab9woSgJuP6kPofFGLkUbCpH2iJL4ZnOluRXOT yRG0PX1JwRwroLdh943/EkXEnCdJ6Oj7l3MMIorqIw52bx6A8uDuX8Pr9AyMQGRXas6F 5yvbfYBACeY/JLtRMpckROrDBO2ZihYecW75gRb1B86ELPptNzjNH06fmaFFL7XgAklO Xdn8i/UjPaJjt7mYPOrlz6f8swIk1kMZxglJkhvPPqOSXwindOCtTsGKmX/vIJNuCwsU uAeCdW+oDMRSP47mM7fBHrJQ6QFrrAImB/qgqAuHA//xt/Rcxu1vd0xvOOV7/aV8cS9M 4o0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319783; x=1690911783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HSVXLsNAShBJHVR9vMtlXCAILUdGmBkWDTfqBXPK0KY=; b=OUf/xdPqqHjOgnNtfUYdJKWrDPvvBny0TFJF4YN6IKBWLxbd6doq5OHMBVecqjgRbZ 1sqArr4XoAtAsqyrAD/ur/4ZfB8HbIg3TcZhQ2y/x4qxK7PpYm7OA1hDUyAXf5jnKmX+ IlKe5R6aUev9AIn5VXcQqA7uCt/FHjanczTc9vhnPQ2QZx0aGkcjfM2qnrcvgSSJZvDn ejGJ8/aqp7Cj5U9hoN8NT6+k0r3c/g6lbnJE7H47LSrjVxHjMs5GV/DEbDmrhcIRU18r Q85wAYPzFjV3cZj6MfF8XZfRygPVV+RA4/ftxuXBH0fqLWBVinP/awJEwufHQFAmHZlZ kYPA== X-Gm-Message-State: ABy/qLYVrJXDAoGWqnSkx4YKgfgMtjbYGdLKx9y/O1s4AJBwdL2ikuk4 PSjt5Gs1HLNn+ZECSRXMg94mgA== X-Google-Smtp-Source: APBJJlGfQ5YkJLM5BRaVIDUTJf0Ihg0ey3efv6IrZlrqxbR3TVF8Kn/hf/0Ururks7UbAt0Uq3H7PQ== X-Received: by 2002:a2e:8182:0:b0:2b6:cfec:69f7 with SMTP id e2-20020a2e8182000000b002b6cfec69f7mr4573764ljg.1.1688319783483; Sun, 02 Jul 2023 10:43:03 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:03 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 17/28] ARM: dts: qcom: apq8064-sony-xperia-lagan-yuga: constraint cpufreq regulators Date: Sun, 2 Jul 2023 20:42:35 +0300 Message-Id: <20230702174246.121656-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- .../boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 6988bd212924..26f1e81e2bf5 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -130,7 +130,7 @@ pm8921_s2: s2 { }; pm8921_s3: s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; bias-pull-down; @@ -281,7 +281,7 @@ pm8921_l23: l23 { }; pm8921_l24: l24 { - regulator-min-microvolt = <750000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1150000>; bias-pull-down; }; @@ -335,7 +335,11 @@ pm8921_lvs6: lvs6 { bias-pull-down; }; + /* HFPLL regulator */ pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; From patchwork Sun Jul 2 17:42:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02FA4C25B77 for ; Sun, 2 Jul 2023 17:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230093AbjGBRne (ORCPT ); Sun, 2 Jul 2023 13:43:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbjGBRnH (ORCPT ); Sun, 2 Jul 2023 13:43:07 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24C05E69 for ; Sun, 2 Jul 2023 10:43:06 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2b6c3921c8bso58017081fa.3 for ; Sun, 02 Jul 2023 10:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319784; x=1690911784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zh4EuEIUK+3K7ESuiSNxZvDgHB1SyNbbFuyE3lj3Cyc=; b=Mt4Q5nEyplEfo1GCziqSb/i7K9j/633W5HEgyukOwrQ/jXaTi5ltlm2WEm6oamSW01 sdGX5Y+B5zxsOLhFkg+PxG/sC/haSq8rqfN8Tcs7DhWjSs4eBnl5ijufEVej/Bu9Lrfo puwU37PpWaMOdYjr0HQANXHvSrl694NBLgejNaBWtnd6hM2hl2Wf42gJKyAMmi9zEEM3 oEhPCd8HctqAt94cYdLg3ZLh5SxFn5P+WBVpBM3DaQqP0EqxC6Hkdig3OanA4Hhpe25z 0h7F1o7CDmV69SsdCR03ausaNYZ5n7vOmoboAP+qpEEllwwTiclwwQvb4VMb8jzOSRPF MWSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319784; x=1690911784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zh4EuEIUK+3K7ESuiSNxZvDgHB1SyNbbFuyE3lj3Cyc=; b=VJk2P8E4TJYKwpyJzdWaUwNyfa397v6P2N+T1TMZeStBj8RuXSiY1tyVkpN/6Y7X3r M2mcH59ZasGKFo7E+5xwkf476cmWMAn6a8oGnGNufyHfsc2oLhkm0aOQcU0pZUcD5xuf GoHYxpu5QIond365+DLAcT+1DaKEYccraImmLP/jLPJOI297AE4KreEkijMu6ccaEDv4 mGcRo/92Or9EEkR+rCkMjhZIzF6H2MGcyQA7ZZF1EU6tZgBRLWT3vrV3t2Eu7ux84w6J jn1TrNpVs/fNBryi2/hZVhSQP/O2OZZcrmfMHnKqebB5rZ+5FyGeVGx4u8YC7IqNO32t HKFw== X-Gm-Message-State: ABy/qLYykBBfpExgYW7WEFxAn7us8FvjUzoRVV6rtj1/E7+27rlRi7DR svtovhSUbhi303X8c3J6DWBgGg== X-Google-Smtp-Source: APBJJlEaifIO01HX4C2bZp/g6HKHe/Pv9mTaf6Q2TPfVcgRJpkmlktX6+8eyyUt02nQyqMASM5Y2Ig== X-Received: by 2002:a2e:8893:0:b0:2b6:ccd6:3eae with SMTP id k19-20020a2e8893000000b002b6ccd63eaemr4678698lji.17.1688319784521; Sun, 02 Jul 2023 10:43:04 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:03 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 18/28] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Sun, 2 Jul 2023 20:42:36 +0300 Message-Id: <20230702174246.121656-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 36c68ee5be65..5a85359d61e5 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -405,25 +405,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Sun Jul 2 17:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1182EC25B7A for ; Sun, 2 Jul 2023 17:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbjGBRnf (ORCPT ); Sun, 2 Jul 2023 13:43:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230120AbjGBRnI (ORCPT ); Sun, 2 Jul 2023 13:43:08 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AEE5E60 for ; Sun, 2 Jul 2023 10:43:07 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2b69ea3b29fso57503861fa.3 for ; Sun, 02 Jul 2023 10:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319785; x=1690911785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Spy/Rz/cAzxXKn/s1kOsEtZbTl790jBubt05JLTnLbc=; b=xKVARl3+UEavVSKgEWAuZsemmhzlBXiFkYs+0+a2XvrnOYn+6kKi3bSiCv5xIQw1tH 4Rde/UGHJm+jLcm3GeOjdUs+4MGDzdDhAT7ftX17teNQ9upYzmBFMgaUq42DAPMgFd6H uyms78+EI6eoPcCzjmRyIII9hr/uvxaqwNPJDpIZ2FrRxJzL6kOIEQ/30Gs1J/dPVse8 Woa/SGMa2A+7MFpeEaulOkFYgkdrm5TrJiKmLsEWZwXipJqZC192llmi6jTsje8z/kwm gaIeEPTEBbn2BLwWoviRnJA7Dj5PD0gbg0adsKj9mwqeJBQMjnCPWx+6cwiTAECEOpN1 UjPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319785; x=1690911785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Spy/Rz/cAzxXKn/s1kOsEtZbTl790jBubt05JLTnLbc=; b=XB1JswOIj/vOmeMUhucQZAOJmR+Sk9PhsYia40/hZ7Jm+/3qZW1OCrftc9NyDxrl7B OXIwjirgvxoqQBF3SI+wRSyjrJFwYKzWt6m82wGjEyTX1wAGaZXMIpkVblCayb/YwQT9 dMLw4KkPYV3HiI0UMs8yRN/BvKQKako5XY+tjp8lLs++teifIp9CPrC2GaGImu6XEK7N jkIBX9CKe6shX33MtbVQ8hYy4KwAu8R0Czt6nimuOTVTZ5DdbBGm3eGWOhhSrkEJVF66 uTXJKnFHo5sfCfrW2IT9AZFUC0Ff5RTgd3P6lUbtfDS6mMRztIDuLWxsBJha1zfYzGY6 5MdA== X-Gm-Message-State: ABy/qLZYflZqf2iQQpYosckoWNYh4vxxe8WdbfGy8pvbe6wtcu1W4kzI kDXaRSl2oku1b/hDfXNTWSi6Ag== X-Google-Smtp-Source: APBJJlG6YkIBJol9D4H5EYF2JEsDZOPDID8nIXGAv1Q5LpjlHVZZ9535mZzz5sKuyxPv/7oF6o4Yig== X-Received: by 2002:a2e:8757:0:b0:2b6:cd71:6235 with SMTP id q23-20020a2e8757000000b002b6cd716235mr5413316ljj.42.1688319785438; Sun, 02 Jul 2023 10:43:05 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:04 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 19/28] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Sun, 2 Jul 2023 20:42:37 +0300 Message-Id: <20230702174246.121656-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5a85359d61e5..ab4b8f8270bb 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -408,25 +408,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Sun Jul 2 17:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8A67C001DF for ; Sun, 2 Jul 2023 17:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230151AbjGBRni (ORCPT ); Sun, 2 Jul 2023 13:43:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbjGBRnJ (ORCPT ); Sun, 2 Jul 2023 13:43:09 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 005B0E67 for ; Sun, 2 Jul 2023 10:43:07 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b6a0e36d42so44609581fa.0 for ; Sun, 02 Jul 2023 10:43:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319786; x=1690911786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PiQD8NPXoK/nu21wRjz7swL+/90HK35SEq9eEZ5XXuE=; b=szb37ojCIrWyIbH7RQecSCJP/XyeHyNqmmaBh9onDYcDKLD+FIPvzBnDlqIGY+WFcw QSD33xfVIt+XDzwzzbL+FjtjY4tFTUbGMGhLhC2jGAk9pRDEDs5N2y8VIYFEMCvarAJm os4V8LiXrKwQddITdbdGB9vAqS5ygbeMTnnjgrWVmuTTjYdLn+FqO0dgWAC+10UiH3G8 cos0esosbF4r75PFBny36CIY2jBj8EGcfi/C9kEcQCD6RPt9v+915NdZ2Ets+OhY6lCb 773d9W5fipsjUR+o4HJ4WfKgXcr5rqPuWDKDjIY3vU57uNwXjiS0W1qBs58+XuljIjTy ldeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319786; x=1690911786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PiQD8NPXoK/nu21wRjz7swL+/90HK35SEq9eEZ5XXuE=; b=BuU0R1mOq/VrQ9tF92niOT5ZVJznpgitsnmrQtIFUSsB9bPmWS1eCf68kokvBcP3Q9 PgV7a+jOLEoH/q8kW8ZtnMUtLkYxKULrHA4XlCdG4WYx6ozIBwDAOFg4tC5mOxp9IBcS OIBGPatUdsJvoOU/PsD55LC9ss7QtAwotPxcWTgjNfvkh6djdnHfzxmCq56h7I6elNQJ kKIPi7qxAUzJoceB6lbenRCJtCSP/KLsBsxapH7ichmyUz//Vecaon+aWf3zeLnluCZz UHYJjamji5863gPKhrNoyUu38oe818utXorKgIsLgH+ye0Fk8duFHscn2TYEjJmfE0tH uUOQ== X-Gm-Message-State: ABy/qLYT5NNnaYEko8eZh1gSLobo4N0X3UCQmMVBUYO0XwQAkXvQIvyf 0tbNzX7B22C6rxW01L+MSpiPfQ== X-Google-Smtp-Source: APBJJlEHhMCDwDgf/6aVjCgaLcezDzbyqLrvjHOiuS5k6VoPxU2fW7+YSfalxB9Qt1FFfIok6q1SPw== X-Received: by 2002:a2e:8697:0:b0:2b6:bd20:c4be with SMTP id l23-20020a2e8697000000b002b6bd20c4bemr2409804lji.20.1688319786343; Sun, 02 Jul 2023 10:43:06 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:05 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 20/28] ARM: dts: qcom: apq8064: add Krait clock controller Date: Sun, 2 Jul 2023 20:42:38 +0300 Message-Id: <20230702174246.121656-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device node for the clock controller for the CPU cores and L2 clocks. It will be further used by the L2 and by the CPUfreq nodes. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ab4b8f8270bb..c212215800d0 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, /* hfpll0 */ + <&gcc PLL10>, /* hfpll1 */ + <&gcc PLL16>, /* hfpll2 */ + <&gcc PLL17>, /* hfpll3 */ + <&gcc PLL12>, /* hfpll_l2 */ + <&acc0>, + <&acc1>, + <&acc2>, + <&acc3>, + <&l2cc>; + clock-names = "hfpll0", + "hfpll1", + "hfpll2", + "hfpll3", + "hfpll_l2", + "acpu0_aux", + "acpu1_aux", + "acpu2_aux", + "acpu3_aux", + "acpu_l2_aux"; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_wrapper_mutex 0x604 0x4>; From patchwork Sun Jul 2 17:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C91ECC001B1 for ; Sun, 2 Jul 2023 17:43:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230142AbjGBRnh (ORCPT ); Sun, 2 Jul 2023 13:43:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230141AbjGBRnK (ORCPT ); Sun, 2 Jul 2023 13:43:10 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D45D0E5E for ; Sun, 2 Jul 2023 10:43:08 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b6a662b9adso53815841fa.2 for ; Sun, 02 Jul 2023 10:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319787; x=1690911787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OZsRJjn/U6tZT4/5EPkI8glRuIiduAZK+U1re19Ckmc=; b=zo2DumS4TLYmSnM0EO/CSQQ5FvpnW5jnGmpWpedfh1I+zmpUZrznJ3282O4IWgPKqS H74sQ5HM5BuQifM3IXb8/6TH1mfAILfFlIBnXDyuBVeG5Uytwy12emLSxdtn794TWf9P SqNPRDAKP/B8DOoH8oep79NLwFi7JSaLI3jeLvV+Bsb0HzFvhMQDZ2LMmU0KrBRGdcoi rQXqjOY3OD7xPGe6h5RN/Y2Uw9i2xkpUkast1Au64kKF8IWerfNi1ZgGrNQvxDynmap5 0atfGyovx8eq3cdb/Z00FMtyGpSb3Dy2KxyGlCdwNayMDgjDIIdm6YBEZRa/5isIN62J tVWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319787; x=1690911787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OZsRJjn/U6tZT4/5EPkI8glRuIiduAZK+U1re19Ckmc=; b=Zn6xuGi7ReXRPD4G+rSZCPy/aJIE59y2A63leG8gxv/Gmmp4RKs4IY4AgfWsXrCMkP NAb72tG7H2965vaBjDMXNURC9xh/ayzla2k60U/YlbzOVWxYccsvwE0aZiCVgaNag8GT YfSEBQTZfcTw4qsI7frSIfRCUq+a4Dz7G1XgXZixAZD5Ld0Fqa9fagQXUhEvCI5ke1zw YDohEPAOKAOqtZdXiirxtrNNq74bhgDalTcLWhFBPIueCL1rAhOVOeMjgIwH5XN45lK3 RmRWSRTruNqFa7X6qeSroTdgz9fNCGa+GAMmMhnw2idEm+C5/SkxT2LFPx621esKmSKK n3PQ== X-Gm-Message-State: ABy/qLbQ08ZertpkCTAZDEpmufTAPhsaFvEBkGnPeT2QRBjdfw1KD4Se QUCf79+hjbUxYou/y5wtxHa4CQ== X-Google-Smtp-Source: APBJJlGjbvR754lTt7F5r4F/RM/CN6QroT5zPLhCLAcvwy6eNTKgAwI+AcMRayhBNYF/nvbPGxdC3A== X-Received: by 2002:a2e:9dd3:0:b0:2b6:dbc5:5ca4 with SMTP id x19-20020a2e9dd3000000b002b6dbc55ca4mr2100083ljj.16.1688319787169; Sun, 02 Jul 2023 10:43:07 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:06 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 21/28] ARM: dts: qcom: apq8064: add L2 cache scaling Date: Sun, 2 Jul 2023 20:42:39 +0300 Message-Id: <20230702174246.121656-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Populate L2 cache node with clock, supplies and OPP information to facilitate scaling L2 frequency. Signed-off-by: Dmitry Baryshkov --- .../dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 5 + .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 5 + .../boot/dts/qcom/qcom-apq8064-ifc6410.dts | 5 + .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 5 + arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 100 +++++++++++++++++- 5 files changed, 119 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index 1d6fb840dc60..30c2ece74ffb 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -78,6 +78,11 @@ reboot-mode { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &dsi0 { vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ vdd-supply = <&pm8921_l8>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts index ee0090e03fb3..7452097e6c6b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -35,6 +35,11 @@ v3p3_fixed: regulator-v3p3 { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi1 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index ddb092710275..80ef3dac6983 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -69,6 +69,11 @@ ext_3p3v: regulator-ext-3p3v { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi1 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 26f1e81e2bf5..748a65c0ece3 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -57,6 +57,11 @@ key-volume-up { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi5 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index c212215800d0..860f8981e8db 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include #include #include @@ -81,9 +82,106 @@ CPU3: cpu@3 { }; L2: l2-cache { - compatible = "cache"; + compatible = "qcom,krait-l2-cache", "cache"; cache-level = <2>; cache-unified; + clocks = <&kraitcc KRAIT_L2>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table-l2 { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-756000000 { + opp-hz = /bits/ 64 <756000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-972000000 { + opp-hz = /bits/ 64 <972000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + }; }; idle-states { From patchwork Sun Jul 2 17:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADF89C27C50 for ; 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Sun, 02 Jul 2023 10:43:08 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:07 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 22/28] ARM: dts: qcom: apq8064: add simple CPUFreq support Date: Sun, 2 Jul 2023 20:42:40 +0300 Message-Id: <20230702174246.121656-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Declare CPU frequency-scaling properties. Each CPU has its own clock, how all CPUs have the same OPP table. Voltage scaling is not (yet) enabled with this patch. It will be enabled later. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 482 +++++++++++++++++++++++ 1 file changed, 482 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 860f8981e8db..5c9daa997e72 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include / { @@ -46,6 +47,13 @@ CPU0: cpu@0 { qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_0>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw0_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -57,6 +65,13 @@ CPU1: cpu@1 { qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_1>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw1_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -68,6 +83,13 @@ CPU2: cpu@2 { qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_2>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw2_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -79,6 +101,13 @@ CPU3: cpu@3 { qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_3>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw3_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -195,6 +224,456 @@ CPU_SPC: spc { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <384000>; + opp-microvolt-speed0-pvs0 = <950000 950000 975000>; + opp-microvolt-speed0-pvs1 = <925000 900000 950000>; + opp-microvolt-speed0-pvs3 = <875000 850000 900000>; + opp-microvolt-speed0-pvs4 = <875000 850000 900000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + /* + * higher latency as it requires switching between + * clock sources + */ + clock-latency-ns = <244144>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed0-pvs1 = <950000 925000 975000>; + opp-microvolt-speed0-pvs3 = <900000 875000 925000>; + opp-microvolt-speed0-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <875000 875000 875000>; + opp-supported-hw = <0x4007>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed0-pvs3 = <925000 900000 950000>; + opp-microvolt-speed0-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs3 = <950000 925000 975000>; + opp-microvolt-speed0-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs0 = <962500 962500 987500>; + opp-microvolt-speed1-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <962500 962500 987500>; + opp-microvolt-speed14-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed1-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs2 = <962500 937500 987500>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <912500 887500 937500>; + opp-microvolt-speed1-pvs5 = <912500 887500 937500>; + opp-microvolt-speed1-pvs6 = <912500 887500 937500>; + opp-microvolt-speed2-pvs0 = <962500 962500 987500>; + opp-microvolt-speed2-pvs1 = <937500 937500 937500>; + opp-microvolt-speed2-pvs2 = <937500 912500 962500>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <912500 887500 937500>; + opp-microvolt-speed2-pvs5 = <912500 887500 937500>; + opp-microvolt-speed2-pvs6 = <912500 887500 937500>; + opp-microvolt-speed14-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed14-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs2 = <962500 937500 987500>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <912500 887500 937500>; + opp-microvolt-speed14-pvs5 = <887500 887500 887500>; + opp-microvolt-speed14-pvs6 = <912500 887500 937500>; + opp-supported-hw = <0x4007>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed0-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed1-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs3 = <950000 925000 975000>; + opp-microvolt-speed1-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs5 = <925000 900000 950000>; + opp-microvolt-speed1-pvs6 = <925000 900000 950000>; + opp-microvolt-speed2-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed2-pvs1 = <950000 950000 950000>; + opp-microvolt-speed2-pvs2 = <950000 925000 975000>; + opp-microvolt-speed2-pvs3 = <937500 912500 962500>; + opp-microvolt-speed2-pvs4 = <925000 900000 950000>; + opp-microvolt-speed2-pvs5 = <925000 900000 950000>; + opp-microvolt-speed2-pvs6 = <925000 900000 950000>; + opp-microvolt-speed14-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed14-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs3 = <950000 925000 975000>; + opp-microvolt-speed14-pvs4 = <925000 900000 950000>; + opp-microvolt-speed14-pvs5 = <900000 900000 900000>; + opp-microvolt-speed14-pvs6 = <925000 900000 950000>; + opp-supported-hw = <0x4007>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed1-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs5 = <950000 925000 975000>; + opp-microvolt-speed1-pvs6 = <950000 925000 975000>; + opp-microvolt-speed2-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed2-pvs1 = <975000 975000 975000>; + opp-microvolt-speed2-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs3 = <962500 937500 987500>; + opp-microvolt-speed2-pvs4 = <950000 925000 975000>; + opp-microvolt-speed2-pvs5 = <950000 925000 975000>; + opp-microvolt-speed2-pvs6 = <950000 925000 975000>; + opp-microvolt-speed14-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed14-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs4 = <950000 925000 975000>; + opp-microvolt-speed14-pvs5 = <925000 925000 925000>; + opp-microvolt-speed14-pvs6 = <950000 925000 975000>; + opp-supported-hw = <0x4007>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs4 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed1-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs5 = <962500 937500 987500>; + opp-microvolt-speed1-pvs6 = <962500 937500 987500>; + opp-microvolt-speed2-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed2-pvs1 = <1000000 1000000 1000000>; + opp-microvolt-speed2-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs3 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs5 = <962500 937500 987500>; + opp-microvolt-speed2-pvs6 = <962500 937500 987500>; + opp-microvolt-speed14-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed14-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs5 = <937500 937500 937500>; + opp-microvolt-speed14-pvs6 = <962500 937500 987500>; + opp-supported-hw = <0x4007>; + }; + + opp-1242000000 { + opp-hz = /bits/ 64 <1242000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1200000 1200000 1225000>; + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed0-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed1-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed2-pvs1 = <1012500 1012500 1012500>; + opp-microvolt-speed2-pvs2 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed14-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed14-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs5 = <950000 950000 950000>; + opp-microvolt-speed14-pvs6 = <975000 950000 1000000>; + opp-supported-hw = <0x4007>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>; + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed1-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed1-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs0 = <1062500 1062500 1087500>; + opp-microvolt-speed2-pvs1 = <1037500 1037500 1037500>; + opp-microvolt-speed2-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed14-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs5 = <962500 962500 962500>; + opp-microvolt-speed14-pvs6 = <987500 962500 1012500>; + opp-supported-hw = <0x4007>; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1237500 1237500 1262500>; + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed0-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed1-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed2-pvs1 = <1075000 1075000 1075000>; + opp-microvolt-speed2-pvs2 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed14-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed14-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed14-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs5 = <987500 987500 987500>; + opp-microvolt-speed14-pvs6 = <1000000 975000 1025000>; + opp-supported-hw = <0x4007>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs4 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs0 = <1162500 1162500 1187500>; + opp-microvolt-speed14-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs2 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs4 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs5 = <1000000 1000000 1000000>; + opp-microvolt-speed14-pvs6 = <1012500 987500 1037500>; + opp-supported-hw = <0x4001>; + }; + + opp-1566000000 { + opp-hz = /bits/ 64 <1566000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed1-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed1-pvs2 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs3 = <1087500 1062500 1112500>; + opp-microvolt-speed1-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs6 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed2-pvs1 = <1100000 1100000 1100000>; + opp-microvolt-speed2-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed2-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs6 = <1025000 1000000 1050000>; + opp-supported-hw = <0x06>; + }; + + opp-1674000000 { + opp-hz = /bits/ 64 <1674000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed1-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed1-pvs2 = <1162500 1137500 1187500>; + opp-microvolt-speed1-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs6 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed2-pvs1 = <1137500 1137500 1137500>; + opp-microvolt-speed2-pvs2 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs3 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs6 = <1050000 1025000 1075000>; + opp-supported-hw = <0x06>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed1-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed1-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed1-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed1-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs5 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs6 = <1075000 1050000 1100000>; + opp-supported-hw = <0x02>; + }; + + opp-1782000000 { + opp-hz = /bits/ 64 <1782000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed2-pvs1 = <1187500 1187500 1187500>; + opp-microvolt-speed2-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed2-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed2-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs5 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs6 = <1087500 1062500 1112500>; + opp-supported-hw = <0x04>; + }; + + opp-1890000000 { + opp-hz = /bits/ 64 <1890000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1287500 1287500 1312500>; + opp-microvolt-speed2-pvs1 = <1250000 1250000 1250000>; + opp-microvolt-speed2-pvs2 = <1237500 1212500 1262500>; + opp-microvolt-speed2-pvs3 = <1200000 1175000 1225000>; + opp-microvolt-speed2-pvs4 = <1175000 1150000 1200000>; + opp-microvolt-speed2-pvs5 = <1150000 1125000 1175000>; + opp-microvolt-speed2-pvs6 = <1125000 1100000 1150000>; + opp-supported-hw = <0x04>; + }; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0>; @@ -834,6 +1313,9 @@ qfprom: qfprom@700000 { #address-cells = <1>; #size-cells = <1>; ranges; + speedbin_efuse: speedbin@c0 { + reg = <0x0c0 0x4>; + }; tsens_calib: calib@404 { reg = <0x404 0x10>; }; From patchwork Sun Jul 2 17:42:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0808C27C42 for ; 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Sun, 02 Jul 2023 10:43:09 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:08 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 23/28] ARM: dts: qcom: apq8064: enable passive CPU cooling Date: Sun, 2 Jul 2023 20:42:41 +0300 Message-Id: <20230702174246.121656-24-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Wire up CPUs and thermal trip points to save the SoC from overheating by lowering the CPU frequency. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5c9daa997e72..cc23adc13444 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -699,6 +700,13 @@ cpu_crit0: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -720,6 +728,13 @@ cpu_crit1: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -741,6 +756,13 @@ cpu_crit2: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -762,6 +784,13 @@ cpu_crit3: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From patchwork Sun Jul 2 17:42:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 482D6C27C54 for ; Sun, 2 Jul 2023 17:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230174AbjGBRnk (ORCPT ); Sun, 2 Jul 2023 13:43:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230157AbjGBRnN (ORCPT ); Sun, 2 Jul 2023 13:43:13 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C50FBE67 for ; Sun, 2 Jul 2023 10:43:11 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2b69dcf45faso58392591fa.0 for ; Sun, 02 Jul 2023 10:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319790; x=1690911790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F6xlLRk1fYN/CIBfPLrvf0p37P9WFmKE4yFn7ZJ/dKo=; b=pTQafm5Oj7ccSGVOVbnjW9wwbqZXwPWtKv+vOeoB++pPbZefHB8IsGDXyMg1CYdi/q vjcQea/na+3n/UGnRiFmQaoAYWLDBQyegWnQBfwS00p9U4DphA870o7mQNLlT5d8Xrd4 01VNVw0xrl7LokKnrPyr+T6Fzl4rcqmu8m8EcO1lFHdykqzTx7eXgPe6w5VrcxhAJ+3g 2bzeMtckFppvLadCuPr9RzJ6wnXEhTpCMFWO9R+S0/gUcukdgCNll7ZL4JbSO6hgusvK prtBaSPMMEwVidneD162uUMzt8ITDMcZb+yH5zGo4pCKoi44nUcxE0+Meu90KVAcZwIc r5pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319790; x=1690911790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F6xlLRk1fYN/CIBfPLrvf0p37P9WFmKE4yFn7ZJ/dKo=; b=SSTFw+i2trsAv2BUmhteJT89HyB47HOk5HeF+Ygv4rDw+X+ZnhMMnvmV4evhNFP2Ke wiTGJ/cOf8YaAXe3JYuUw6DWcBp0XbDQ3zWLgIQ8ueVfW9+UAXJBnGhp5WUmKcCHYVIG mo3ICBXLA3K3Pb7sZoM6mpUFhfItypZWoElFMCgIAbXqLqdFr+dSPxYtettCuzQEGXJ6 nNH/KZpqimB1HO8lcrMNy5SXUHBzrSECqbnfz4pDj+Njcc9lpTuSRGghdpjjHAV8ZZZv pwpgxC8YRNnpoLSMU567i2Z8usSyew622tehaIAs3+jRUF3Tx44Tyomua/BF3fvNA93J rRwQ== X-Gm-Message-State: ABy/qLZgNhUOvJXB6zjxKq3ZP1+039kqrFozOmbEcLzb0bWjOO9zogPr tPfIob04Zbr5fuKmC/pIvd/Qqg== X-Google-Smtp-Source: APBJJlGzUSqA8cgtTpQxgCces82GHZbYjOw4Td6m506DLn9qHglWl/yrBewQzk0QEhjY8H/aWqaiYg== X-Received: by 2002:a2e:3a09:0:b0:2b5:8a21:5627 with SMTP id h9-20020a2e3a09000000b002b58a215627mr5172699lja.51.1688319790072; Sun, 02 Jul 2023 10:43:10 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:09 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 24/28] ARM: dts: qcom: msm8960: declare SAW2 regulators Date: Sun, 2 Jul 2023 20:42:42 +0300 Message-Id: <20230702174246.121656-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index b25cd58003e2..ba82b6ab899e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -223,13 +223,21 @@ acc1: clock-controller@2098000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Sun Jul 2 17:42:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85EDAC27C65 for ; Sun, 2 Jul 2023 17:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbjGBRnl (ORCPT ); Sun, 2 Jul 2023 13:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230176AbjGBRnO (ORCPT ); Sun, 2 Jul 2023 13:43:14 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E053E6E for ; Sun, 2 Jul 2023 10:43:12 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2b6a662b9adso53816171fa.2 for ; Sun, 02 Jul 2023 10:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319791; x=1690911791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ok9P9IpAQTcPv0Tlft8NotdgEZSuFIkwvtwYagpVMWE=; b=hU2u4lruLLK/+LV27c2moyQ9G1WO52cbfcHrN98FdIE14mmzSeSFniW4Zz5l/wm//M dFR61fG/NE1TiYv/42Np0q7NiJgRYEttBvQSvQEJxwtSriS3ZrA4zV8SzJ2k1elAlr3w losoEpzkcskMxQ2JOo+RYFZsR79d6b0caJaUn3rGM0n0KLwatwVC0egwwwsDNJTxKc6W z9lPjVPEDT8k+NObH3PSoz3eG/gWDKU8kDW4ke1avRPvDIPpgYr/2ZAEBrhAosMqAcp4 0pnAbB3rKKo7Vce4EBAPs/DvCQcXEpb2TNAp/EEEMLQUfnKUIhr9JGqzB/s8YncxEPWd ZMpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319791; x=1690911791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ok9P9IpAQTcPv0Tlft8NotdgEZSuFIkwvtwYagpVMWE=; b=Q9CB/g3o7BcwotYPRIIhqHUv+vhvzsaFhOPMnCQ2k+DWIQREoHN/YlXbd/k9WlhiAG q6IzNZ7FOG9nNtetOYtSaRuBph1qjOITVR8nKKPi6mApfDCcS9jLAXx120STjwogbpZz EzRWa7WD726OBPYBdTPv54Y4o5qETAdOH3Nd3PnAEU1/j7vz1GmLUniYJaLLvT1ajQo5 bDW2XT0D5izNeRDcf7sIZy+tsCh7bknAX7AEwdJuStEosWCqUbLmHm57y9N4qp1qkLVb jSy4x/xKdWFjFeggy+7JPvd6wA5Mfaaq3090VbohfX/R7fD/t1xqE6LqmN5G3eNQuuiq TPvA== X-Gm-Message-State: ABy/qLbtriX/GT1Yj+6W5HPaX/N6lpGqHE4q/H7iq7NTEF6fpaX5faeP 7LYwczFnluAN/CQB1vnkfqZohg== X-Google-Smtp-Source: APBJJlGrwOZUDJObS9p4hbTu2Q7j7tqTM3w0NsR7pT0qKaTIsfP3sSBaw8ZXbOkisLykRKHjXM1l2A== X-Received: by 2002:a2e:7c0f:0:b0:2b6:d7a0:c27d with SMTP id x15-20020a2e7c0f000000b002b6d7a0c27dmr3136344ljc.37.1688319790947; Sun, 02 Jul 2023 10:43:10 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:10 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 25/28] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device Date: Sun, 2 Jul 2023 20:42:43 +0300 Message-Id: <20230702174246.121656-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8f178bc87e1d..6a2ff30a2f3c 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Jul 2 17:42:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3DB7C00528 for ; Sun, 2 Jul 2023 17:43:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbjGBRnk (ORCPT ); Sun, 2 Jul 2023 13:43:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230192AbjGBRnO (ORCPT ); Sun, 2 Jul 2023 13:43:14 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA73B183 for ; Sun, 2 Jul 2023 10:43:13 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2b6a662b9adso53816251fa.2 for ; Sun, 02 Jul 2023 10:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319792; x=1690911792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m3iVCt7nS+euIxpXidw/3v385QWRNdeTuls6EQqgHh0=; b=FWVdcPcQM0oDX7YXc1hgasumud57y5IH/tcRSF+Z8YRQjkfIHq6ewN5IGjP4MyUJZX kiiKmNoV8ixbCH/qLyvBrtczqfa9NWfTzrlMki7OLrjNXy/FPPQhAWMjfJW1hJcGRKJC 820KeUqROhpKxwX3TpOongGe20QdY4njeT+ZtxgKaW3fWwylcZKK1DAzTF4Lmi4RCcqG 2wrsC+usDOyWUHu0uCo5Y0LPQ+0IEPF92Ltjq9brtjwnxpCE+bDFiZF8s/fnySRut9fd Lkpzspw/0Jc6qbL96bkSolVK1QxUIR7QuAv7hbXWh3iP6D99p72md0DW3MVKwVtg/nhJ mmdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319792; x=1690911792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m3iVCt7nS+euIxpXidw/3v385QWRNdeTuls6EQqgHh0=; b=P84wYrbvNs0dO5Q9LOG7T9z5/06kThslqAsYpq8weFirXOYtb2aQULm5f/qj496o8f BNms1WBwNRP4A1SgCtRKJv5CEzDYMS/8BGTQ7xqVaxWTiTunFZIZZ19Ar6BHgNyll7mi mAM5vfzPPKPinL7qV7pm1Td9vNVgOgklfSO+qvaWR1LJYvs7931oPQhBlyfzrmcnzfv9 rus4JZTmQKW1O+2lDMkV6wBBH4zSUWdI3XxTtMst1GMVcN5BM6Crmub1l1tGvNzBEoV4 LCoSTaEJNfBOINece9bq9acgDfUVSkhNP0WibV1UBRxBJm4Qr8SoGDKqtT04NLWbj1lW jQ2Q== X-Gm-Message-State: ABy/qLaNHhqiiIl2XW/ZaWjnGJibGcvaO3nYa69i9vog+W6doR3e0niM UDIYvDUt1eUKRe2vhoxcbo8PNg== X-Google-Smtp-Source: APBJJlGUFIcXD9GA76VfUeHACSqBSmGW1Heb75yKtmzwl7EWw9fDwWQbsPOmnA68jFGPBWfJSlXLtw== X-Received: by 2002:a2e:8257:0:b0:2b6:d084:e589 with SMTP id j23-20020a2e8257000000b002b6d084e589mr4307228ljh.47.1688319791965; Sun, 02 Jul 2023 10:43:11 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:11 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 26/28] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Date: Sun, 2 Jul 2023 20:42:44 +0300 Message-Id: <20230702174246.121656-27-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index a4ff1fe63903..bb4f08d40ca4 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -416,7 +416,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Jul 2 17:42:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 699788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B582AC27C79 for ; Sun, 2 Jul 2023 17:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbjGBRnm (ORCPT ); Sun, 2 Jul 2023 13:43:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230200AbjGBRnQ (ORCPT ); Sun, 2 Jul 2023 13:43:16 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D80AE60 for ; Sun, 2 Jul 2023 10:43:14 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b6a084a34cso53921581fa.1 for ; Sun, 02 Jul 2023 10:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319792; x=1690911792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=opGMkE+RmDE5zkyZAa1LQgTvHH68ZBwvMhZI5dpXRoc=; b=WMVRoFPOH0oYuKrpEfqVgY7AixffovubRFVREzpvwkeL3p1FFB/78nSebso2Q6y10X y0L1rTbstwJr+sZbiRUliDK6PFSQ8p0CXevpodFxywVBN8s4jHU9OUBeVNik6G1gnqe/ Gp3eYoH4dZa6DH3T1uClg13yiXKsjOLhm30sVuVZz5RYWQlChQFzFcmIBwdgg1zvtqlf xJNH5wECAVPQhEaJT+kX8aWsjSSYkmy67MmOcm91FWFglT8uPIhdCZBpMccqOhyFS6Pc g8nNNF/A3Lt7eyXAIop7m4CSE9V4Fe0i5pu02nvc/o/Daj3aoUHJFLiFTDFUiWuSFl0U L+jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319792; x=1690911792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=opGMkE+RmDE5zkyZAa1LQgTvHH68ZBwvMhZI5dpXRoc=; b=efPibq27Is9zOdtz75rIjcZBSXnkHYrmtzrKuEsVPLVeXHN6NR/cNy/6vriiW24En4 zKXMQ+AhtdjIiwK9IavGoDm1SLFVGYi9kjARjTi6+MBXMi4f15JT0L2JzqWU5Y/p1rcY namKaetGLMUA2PtD2r/LgHc4OB64ve/jLrois5Rlby/EWgmGb8ciF4C9siINej7r84tf F7bl2ULK2u+X2P/LWjTwzEMYljqgBDM2YhBwAvyEP/1E8PeIGAuGl0asMjTdDXeGphMU U4AZiSti9LfL0SAzYoGUzk9BC32JefuliuEy/j6lyL/HfSFOduZ8kpScpQsasJC8wYze 9DhA== X-Gm-Message-State: ABy/qLb3gOeF2VR+JsFS8230ZxAL2aChZ/wQJ5UarXP1QkSLWLrPwdJJ 4VYBs7Wt4bTLvW8uUodov/qC1a2XNEg1fG9WYCo= X-Google-Smtp-Source: APBJJlFEVtDlhA4Fop6XZKOVXJZ2gSWDSS2y34nlny7yuuVdgDbyQzPDFwBypd2gHJ6Lq2aU5U//RA== X-Received: by 2002:a2e:9785:0:b0:2b6:d536:1bba with SMTP id y5-20020a2e9785000000b002b6d5361bbamr4061940lji.18.1688319792802; Sun, 02 Jul 2023 10:43:12 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:12 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 27/28] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices Date: Sun, 2 Jul 2023 20:42:45 +0300 Message-Id: <20230702174246.121656-28-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f0ef86fadc9d..ad3c922843c7 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -350,31 +350,26 @@ acc3: power-manager@b0b8000 { saw0: regulator@b089000 { compatible = "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw1: regulator@b099000 { compatible = "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw2: regulator@b0a9000 { compatible = "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw3: regulator@b0b9000 { compatible = "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw_l2: regulator@b012000 { compatible = "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { From patchwork Sun Jul 2 17:42:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 698480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42635C27C6F for ; Sun, 2 Jul 2023 17:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjGBRnm (ORCPT ); Sun, 2 Jul 2023 13:43:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230206AbjGBRnQ (ORCPT ); Sun, 2 Jul 2023 13:43:16 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BD58E59 for ; Sun, 2 Jul 2023 10:43:15 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b5c231f842so54009311fa.2 for ; Sun, 02 Jul 2023 10:43:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688319793; x=1690911793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7SRMw2832DQB4senqNrBO6nhVQ4RvkIxirBPWKvUG+w=; b=WYcGYHYQSTykDSVs/CC+hPWYKiefIFjasm6fBAXi7bBXdeowIypy3eU1E6xjtBLAwD z0F4Ri8LsJtQMK4x9gDLbuR7fngKyj5tACmEvBIPAP/BJSpY5dTJgUDGV2pkpcKuIWMc NtHvyRmmh9iUmpdyRXA7woz/IaErGtg1fFKcDTyX5lhbuBfLaJbn6/CF2St2rlH+Y1oi T8xVY0sRVDzMmV/qEnNv4WeGqA6JGAMlfD0/XjtZDj1iutnYwkzZzs6fE7LYis1ccs4W fjnsTJ2u0pYGB2aEcgQ80L6V8hlmj/rYzNMNJwmTbDXlyH14HzpW0xpLLZaZstC4m8DS mo9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688319793; x=1690911793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7SRMw2832DQB4senqNrBO6nhVQ4RvkIxirBPWKvUG+w=; b=DZlQijopOUW2Pdna7/hS4uOSsVGgAeZ8ketRVYZIY+cEWHDncCMlfLKQXAU9ASWBqx eaGpQQrAMhyp7YEPoWN05vuajdmzKMOdoIvhvFJcExVJFmruuef1RnuDeYwFvpWT8oQx uTtV222pqk6/HR6zofxomIsWqTGndhAdpkM1YUbRILV56k9Ss22N1e9l347K+7xrfw5m yQ5T7l8NZindYZcE4Qd1YMEv3p/eGp75iarbfuLrXerJnz/rLfL4iAe3vgMmzLm7TdZU wnYawSDZPhH7kktFrbvXc8Vi7k59pWDkVbfbr9LqksYO8STF3e5c31z3n/XOvNudu5tV piLQ== X-Gm-Message-State: ABy/qLb0V/Vdt0NWD9S0SaxCJR+QYH3ati4f/DRILhD8hzyP3lKdwLVo E28bPHbS0Ics8HV2owhuKM06VQ== X-Google-Smtp-Source: APBJJlHcTkVDz57v9uEaWfG/MgSJY5N/hkVOJefQpd3rwFselpcTuYqdhD6ecBmFMV1lnrdGZrv9Wg== X-Received: by 2002:a05:651c:22f:b0:2b6:ba66:8b4 with SMTP id z15-20020a05651c022f00b002b6ba6608b4mr5414161ljn.8.1688319793640; Sun, 02 Jul 2023 10:43:13 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id v23-20020a2e9917000000b002b6daa3fa2csm1372550lji.69.2023.07.02.10.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 10:43:13 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v3 28/28] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices Date: Sun, 2 Jul 2023 20:42:46 +0300 Message-Id: <20230702174246.121656-29-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> References: <20230702174246.121656-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6198f42f6a9c..ecb99e104de0 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 { saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 {