From patchwork Wed Jul 19 07:20:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 704450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88358C001DC for ; Wed, 19 Jul 2023 07:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230100AbjGSHVO (ORCPT ); Wed, 19 Jul 2023 03:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbjGSHVA (ORCPT ); Wed, 19 Jul 2023 03:21:00 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E030B210B; Wed, 19 Jul 2023 00:20:43 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36J7G9oC032355; Wed, 19 Jul 2023 07:20:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=X8U7m6oeXAUjm/N5kYm0WAl5wvbpfFgciZSimFM50A8=; b=G0dEsCpqrJY9vH8e3Kil2NAt8GTB9Boy2ZCQP2GyJ0IA8KGMlvYwJWhAsqxcG/M1oKPt c1DFSDgCeIr2BJG18MCSxkP1yhpCsHQf4PV5GfmLfqd+bTVghtgtXAMY2TIWOWfhUrip NThmO3sLfZ9EMnljsSKTtvIJm22p+3dczhmGdulSA+/Spd3VAfse4P2L3vgAJ7l7EsGl SOnpIXJv1qPYSiNKAhHKUjh+aqOcIZAda4fQr/tJ3BAo2x4aKfHtopvVHEkJJsLOE3wm Xpt7sV1jqScnVZQF4jmo/zNEtQFiE4V+0in3Y2ItVOANs6LxYznEK9FMW7NQUdmnrUa9 Ow== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rx8sk087t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKSo022626; Wed, 19 Jul 2023 07:20:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v72-1; Wed, 19 Jul 2023 07:20:20 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKI9022612; Wed, 19 Jul 2023 07:20:20 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKre022582; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D5D014B07; Wed, 19 Jul 2023 12:50:19 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v10 1/4] dt-bindings: PCI: qcom: ep: Add interconnects path Date: Wed, 19 Jul 2023 12:50:15 +0530 Message-Id: <1689751218-24492-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: j5RE-AyD1ly7aUPmN4MrNP51q2U9nhI_ X-Proofpoint-ORIG-GUID: j5RE-AyD1ly7aUPmN4MrNP51q2U9nhI_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms may not boot if a device driver doesn't initialize the interconnect path. Mostly it is handled by the bootloader but we have starting to see cases where bootloader simply ignores them. Add the "pcie-mem" & "cpu-pcie" interconnect path as a required property to the bindings. Signed-off-by: Krishna chaitanya chundru Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8111122..e553341 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -71,6 +71,14 @@ properties: description: GPIO used as WAKE# output signal maxItems: 1 + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + resets: maxItems: 1 @@ -98,6 +106,8 @@ required: - interrupts - interrupt-names - reset-gpios + - interconnects + - interconnect-names - resets - reset-names - power-domains @@ -167,7 +177,9 @@ examples: - | #include #include + #include #include + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, @@ -194,6 +206,9 @@ examples: interrupts = , ; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; From patchwork Wed Jul 19 07:20:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 704451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E83CBC001DC for ; Wed, 19 Jul 2023 07:21:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbjGSHVJ (ORCPT ); Wed, 19 Jul 2023 03:21:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjGSHUy (ORCPT ); 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Wed, 19 Jul 2023 07:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36J7KLiV022655; Wed, 19 Jul 2023 07:20:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v78-1; Wed, 19 Jul 2023 07:20:21 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKXI022632; Wed, 19 Jul 2023 07:20:21 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKnU022618; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 126244B0A; Wed, 19 Jul 2023 12:50:20 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v10 2/4] arm: dts: qcom: sdx65: Add PCIe EP interconnect path Date: Wed, 19 Jul 2023 12:50:16 +0530 Message-Id: <1689751218-24492-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> References: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xRkYrMUJhXv7dZpmi_v6Dp2S7zvgYDkr X-Proofpoint-ORIG-GUID: xRkYrMUJhXv7dZpmi_v6Dp2S7zvgYDkr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 priorityscore=1501 mlxlogscore=869 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 1a35830..69fe7e5 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -332,6 +332,10 @@ ; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core";