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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id y9-20020a2e9789000000b002b9ae051ea1sm1438688lji.113.2023.07.29.04.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Jul 2023 04:04:57 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Thomas Bogendoerfer Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Sergio Paracuellos , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH] mips: dts: ralink: reorder MT7621 clocks in Ethernet block Date: Sat, 29 Jul 2023 13:04:49 +0200 Message-Id: <20230729110449.1357-1-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Rafał Miłecki Use order as specified in the binding (first "ethif" then "fe"). This fixes: arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@1e100000: clock-names:0: 'ethif' was expected From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml arch/mips/boot/dts/ralink/mt7621-tplink-hc220-g5-v1.dtb: ethernet@1e100000: clock-names:1: 'fe' was expected From schema: Documentation/devicetree/bindings/net/mediatek,net.yaml Fixes: 7a6ee0bbab25 ("mips: dts: ralink: add MT7621 SoC") Signed-off-by: Rafał Miłecki Acked-by: Sergio Paracuellos --- arch/mips/boot/dts/ralink/mt7621.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi index 7caed0d14f11..73035d4f4cc1 100644 --- a/arch/mips/boot/dts/ralink/mt7621.dtsi +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi @@ -300,9 +300,9 @@ ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; - clocks = <&sysc MT7621_CLK_FE>, - <&sysc MT7621_CLK_ETH>; - clock-names = "fe", "ethif"; + clocks = <&sysc MT7621_CLK_ETH>, + <&sysc MT7621_CLK_FE>; + clock-names = "ethif", "fe"; #address-cells = <1>; #size-cells = <0>;