From patchwork Sun Aug 27 11:50:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C686FC83F1F for ; Sun, 27 Aug 2023 11:51:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229835AbjH0LvL (ORCPT ); Sun, 27 Aug 2023 07:51:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbjH0Lum (ORCPT ); Sun, 27 Aug 2023 07:50:42 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6882519B for ; Sun, 27 Aug 2023 04:50:37 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-500b0f06136so1410848e87.0 for ; Sun, 27 Aug 2023 04:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137035; x=1693741835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=T3P5AiTSCX5RpK2R7xLe4ZbH1tME377lor7YXPNjC37fGtWJ42KlLewwjr3UR8eOe3 vaOulIUgywNvYz+S2wDShhlr9zuwHf3YX67eS53ANzPaLtLZw3JpPWCiGkOxSsSdUYL8 DH3xgHHbkOpN/aGTBLkWYhBJjbe/OSFfAGqXrVmgyoCWCoCTZ0dQ6njvMAcTVAHnaoIh 1cMuuWyZ71ljeJpS7cGHAwImSaj234j1zg1sAoGkG5GEbv4ejifkSaGvExs6Tc45Mryy iuaqZM5JKS3yEAXGAWUTi+kp7LLqPuRkX3nCeGXExGHysPGrXqdlbuj6mra5ZPdWWsoi B8Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137035; x=1693741835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=AJjWf3bay0/sbX4PL0BAw9kb1qF9QQQcQt7DyzWx8iL45iu7RDxcDSgqQyHNVyXHy2 Kmkq9/hJQh9G+ywoBMX9RjsoxRaGizInounAsXHgR8OlVWSrKg6sGcxn/IxbPWPsrQyl hjV1YH320JsbRtS3zbmQmQaKJgSQonnl2Mp86HAD0okBOatOrW1pAf/cBH1I2XvVlVbT nziZbsojHK/ZKOEfDqWiqVvX9ldTNLindDMjGowvxBpGH7ylq3skLTWATtZHhqFspYUi MjKphsGzc1TK6014namHaFYuOrDaod8YwI1RdE+yb+tKus/5Vs3LQ6mzpcZc6RpsBawX 0mCw== X-Gm-Message-State: AOJu0Yzh9gpu3eYIvMYwQJ863DVDK8AXkYvfaxabRcHPSRDEIuZXZdri 5RV7Y8nyUPoflqclK9loRmKDBg== X-Google-Smtp-Source: AGHT+IGl5MduPxL5W7j/gTGahht78xN2EIeyQS3zhPxoOY8LmpHwOTWvx0qvJjWqBjoJyWAzfxkDFw== X-Received: by 2002:ac2:4a6e:0:b0:4fb:9e1a:e592 with SMTP id q14-20020ac24a6e000000b004fb9e1ae592mr14393826lfp.4.1693137035473; Sun, 27 Aug 2023 04:50:35 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:34 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v4 01/23] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Date: Sun, 27 Aug 2023 14:50:11 +0300 Message-Id: <20230827115033.935089-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. The regulator property is retained as is. It will be changed in the later patches. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++-- 2 files changed, 20 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 64% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..84b3f01d590c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,25 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: @@ -34,8 +41,15 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + type: boolean + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible From patchwork Sun Aug 27 11:50:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A92E3C83F01 for ; Sun, 27 Aug 2023 11:51:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229800AbjH0LvL (ORCPT ); Sun, 27 Aug 2023 07:51:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229882AbjH0Lum (ORCPT ); Sun, 27 Aug 2023 07:50:42 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E3211AA for ; Sun, 27 Aug 2023 04:50:38 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4ff8cf11b90so3658042e87.1 for ; Sun, 27 Aug 2023 04:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137036; x=1693741836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=fDoOejcfzbwe19CsC5cIGnRJDuUADqOk57Xiavi4d1himlAQR99YeRzVY5y99S43Ln dvvS4bUmAgjviEi1KwLy0qXZOE5zvLB1OE6E1vwOPnNGa3+6WuN1GUvLmNGdYatnHiuk aLwRh9GBMRdt1bL4MDJrL82Ketk/yJ9TFJzlJU5qr3oHZwIa6tdvl+4jmf4dckRT+72V 9ndmMJYJqBWyidMqRYesB8qsSzBiNY5h8i/E0AITIfbEJp0IddVCRzCS3j79BnbtPYKv b2lwOUBP6zxFlaBhOrnBEV2pHG/ZFTa3mwVHf2pXqJYfoWHOhVTrGuGksofwfegzLlJc ViVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137036; x=1693741836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=NzzR8qKAeI8lgBguF6Wu1aLUIb7z/oZaP5Ey7SyqyOdM2+uy8msvJQBGIsiiVUxyxe CSJ+D9HrEzhlBZHhuRXjnXz46QzYTYCW6IgU81qhLd+QMYn6jhhaiKDXeL2aMH09fmz1 6I6hqIGeovM70qKawNOu4FhtfU8l37cxvdaYASieeDsJCrK3kyhhEm8SiqGIRoHj3G1u vOFQ7bMXWEyG6tTZ3F4Splvf6LgIpfFEmzw/Xp8qi7lLubODAjvDnFSGK36p1uHf2mqg wDl+/UbYTl8BzCGQDybVT2GEH0fwbQ69rqcX1F28dEW61x6uYTA/JXP6rbjnXiOU/jGx dOMg== X-Gm-Message-State: AOJu0Yw1TAnnBJtG775YaZ1GOKHaDNCiA/OaJkvz/CPjraqBlejQkkOQ C9sv3fn2E9YzV9kDiGawVrJISw== X-Google-Smtp-Source: AGHT+IFyZIPVYeMBLN7zioe1bDA719mHlp3XKfCKpKDpxPRm40Vc0kjyn/3jpYKnN+AZ2sv3SNTXzQ== X-Received: by 2002:a19:520b:0:b0:4f8:71cc:2b6e with SMTP id m11-20020a19520b000000b004f871cc2b6emr14940588lfb.33.1693137036363; Sun, 27 Aug 2023 04:50:36 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:35 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v4 02/23] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Sun, 27 Aug 2023 14:50:12 +0300 Message-Id: <20230827115033.935089-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..a2d871ba8c45 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,7 +47,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -96,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... From patchwork Sun Aug 27 11:50:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83DF0C83F1C for ; Sun, 27 Aug 2023 11:51:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbjH0LvL (ORCPT ); Sun, 27 Aug 2023 07:51:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229907AbjH0Luo (ORCPT ); Sun, 27 Aug 2023 07:50:44 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4351D130 for ; Sun, 27 Aug 2023 04:50:39 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-5007f3d3235so3593765e87.2 for ; Sun, 27 Aug 2023 04:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137037; x=1693741837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ro+frU1rlZBxpMUoLWa0fuKb2nit2Il6DrrgMioSWzE=; b=kVrCWnDlujG4mHtYucB+dfb+lZ8IoCUgXize2o9ICAfAWnp9uyyEB8CUU76ZXGeMY+ fNyOJzNqMAawRUbImkbTI4VZrlzJZHHrnGZSCjbMAfB0GOwu4+khYb37OBIxwBPTEF2n uE4o1Fn9Ib6GdiaKozkNa+jaGiNfnsvmrp3Z+zNlc4JcHEURLr0fWrF3ndQgzz3lxYhS XPn1kR47nv169Wia2E2zfZvTk9zr3W8ZeLLBHCXKKr093UQRei405JlDP50Av85F5cXo 2zgLmy9JuPsuvB+8lhD6MBHjwxxmwMLtevLevtUNSZVA16/4zkVA6gYpFi5C/Oa1boDr G9yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137037; x=1693741837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ro+frU1rlZBxpMUoLWa0fuKb2nit2Il6DrrgMioSWzE=; b=FDckHKZg4sa3yp+r+HjtUyg4DlFULbw43PGbRv8wKes708bFNySjYCiOemHu+3hMdV 7BF3fPmGkpkY9vL/SWbhJwR1xcJ+YsM92kaCOYGhnL2UuXWo7vvFrJAjL1VwERcn+d8U EnMozzRzJ4qeu/wdjZcG8NnrljrzcSztfpZNOK5LNJUICHQ9o6cAgQ7uYgNLCDkzFnVa PA4OezRgOdrhIaJeiIO7eS/+9XWHm76SSVB8RGt1pmklzHdF7wdIcHurR1CR6TNYz/w3 nMUbBHoGawiOunOuGHoJYYKBz8whXDJVs2rOeJLtSFbygQoj2w+bkS23K7WWyTyQEQp5 EnFw== X-Gm-Message-State: AOJu0YzXkLP4yXfqzRnBGFd7V7eq7PakU3kNlRVMky/nIMI21Es9HUhg bA6YegUzNWXgbISL6CxFigKeCg== X-Google-Smtp-Source: AGHT+IGt2xgmWwOY0CUsVtOQyV9nxdtxLsPQavPhWLMXNuZlLE1bY4JF0pl4U12XqJVuGZD0wQUyqQ== X-Received: by 2002:a05:6512:114d:b0:4f8:67f0:7253 with SMTP id m13-20020a056512114d00b004f867f07253mr22826824lfg.49.1693137037268; Sun, 27 Aug 2023 04:50:37 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold , Rob Herring Subject: [PATCH v4 03/23] dt-bindings: clock: qcom, krait-cc: Krait core clock controller Date: Sun, 27 Aug 2023 14:50:13 +0300 Message-Id: <20230827115033.935089-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for the Qualcomm Krait CPU and L2 clock controller. This device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is represented as the interconnect to facilitate L2 frequency scaling together with scaling the CPU frequencies. Acked-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- include/dt-bindings/clock/qcom,krait-cc.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h new file mode 100644 index 000000000000..9d181873c414 --- /dev/null +++ b/include/dt-bindings/clock/qcom,krait-cc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H +#define __DT_BINDINGS_CLOCK_QCOM_KRAIT_CC_H + +#define KRAIT_CPU_0 0 +#define KRAIT_CPU_1 1 +#define KRAIT_CPU_2 2 +#define KRAIT_CPU_3 3 +#define KRAIT_L2 4 + +#endif From patchwork Sun Aug 27 11:50:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08AB0C83F23 for ; Sun, 27 Aug 2023 11:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229868AbjH0LvM (ORCPT ); Sun, 27 Aug 2023 07:51:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229928AbjH0Lup (ORCPT ); Sun, 27 Aug 2023 07:50:45 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B661B8 for ; Sun, 27 Aug 2023 04:50:39 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4ffa6e25ebbso3973296e87.0 for ; Sun, 27 Aug 2023 04:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137038; x=1693741838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1h5yZ1ON0tbidIVRhLbpjEGcgJUDJL2iKVUumFLXMN4=; b=a7muBL9IUjqVns3i7KW6R+6B7wM+KGnCPlxLztBTGwmKd+7z0pZeGLdaSXFwCjJhfX 9Ub944wky508FCfEE8IQHBzo3TJlucAi5N1NkR7K+gAVoqa5iZkw9CddGPC2PS80cqVT HZD51xtrHwKHyC/GFCx+xAL2moQUGk0xmcXgrjtG2grNG4NaKBOH97WPa83SEOCP/CMW jGzVMk176p7kQNitmRfBRVlDQsllaRWQFkBtGkBobzd6rwr5MumkHM49mMYqOrdkXMVV PigGQa4KeXaau44rGImOqs1sReH4OGRItWGNBkknm82QaVKarQcnuYOQkSCNkWGXS4WF iYJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137038; x=1693741838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1h5yZ1ON0tbidIVRhLbpjEGcgJUDJL2iKVUumFLXMN4=; b=CmgwExO8B7yik/+Sbxn0UmBDcqXWgdK2oT8R6JSI+YBqa8Uw9A0pTw/4VLCL/s7Z2L fE0pd6fraqDZUdHOWU1vnGPrvAs5VRGf8L7aQfZ4++NfpvyQ9w9YN9OqB6DYAKihNTLj anrYlMI/1poRSW0gsVpWY2KuqMT0Ehy7geXpvwwIjFQbFRrjqpslg0OuB2e9eSyVzvmi 6rTu27c1oHKSzc+Kirifx8cYowj+WCdiCCBTN9V/hVu8hmQaHkLGuiv7pVAuxfMaN4Gl 1jf9xfuxj/kznnbrcVPRvkY2xy7rOK746BYHi3H0xY0r4sSsBs6wlfjwupvBkUEF0b4y aOPQ== X-Gm-Message-State: AOJu0YyoVMU0jh4mKSQtvIxaJj+/p/Tppd3bGzoGKIqquuiIs8+pI7Ek ElqIPRw5h2xvpBS4bfAEzib3Zg== X-Google-Smtp-Source: AGHT+IGW0g5PxPyHdiA94zEf8AFi046HCvktmj51b88ouBJ1A4lNV4gblc4U8fgDj2Haet1KdvtBvA== X-Received: by 2002:a05:6512:3096:b0:500:a008:a2e8 with SMTP id z22-20020a056512309600b00500a008a2e8mr3090179lfd.12.1693137038048; Sun, 27 Aug 2023 04:50:38 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:37 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 04/23] dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms Date: Sun, 27 Aug 2023 14:50:14 +0300 Message-Id: <20230827115033.935089-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The L2 cache device on Qualcomm Krait platforms controls the supplying voltages and the cache frequency. Add corresponding bindings for this device. Signed-off-by: Dmitry Baryshkov --- .../bindings/cache/qcom,krait-l2-cache.yaml | 86 +++++++++++++++++++ include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h diff --git a/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml new file mode 100644 index 000000000000..59ce11dd0a24 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Krait L2 Cache + +maintainers: + - Bjorn Andersson + +description: + L2 cache on Qualcomm Krait platforms is shared between all CPU cores. L2 + cache frequency and voltages should be scaled according to the needs of the + cores. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + contains: + enum: + - qcom,krait-l2-cache + + required: + - compatible + +properties: + compatible: + items: + - const: qcom,krait-l2-cache + - const: cache + + clocks: + maxItems: 1 + + '#interconnect-cells': + const: 1 + + vdd-mem-supply: + description: suppling regulator for the memory cells of the cache + + vdd-dig-supply: + description: suppling regulator for the digital logic of the cache + + operating-points-v2: true + opp-table: + type: object + +required: + - compatible + - cache-level + - cache-unified + - clocks + - '#interconnect-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + l2-cache { + compatible = "qcom,krait-l2-cache", "cache"; + cache-level = <2>; + cache-unified; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + clocks = <&kraitcc 4>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + }; + }; +... + diff --git a/include/dt-bindings/soc/qcom,krait-l2-cache.h b/include/dt-bindings/soc/qcom,krait-l2-cache.h new file mode 100644 index 000000000000..c9a38d368111 --- /dev/null +++ b/include/dt-bindings/soc/qcom,krait-l2-cache.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H +#define __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H + +#define MASTER_KRAIT_L2 0 +#define SLAVE_KRAIT_L2 1 + +#endif From patchwork Sun Aug 27 11:50:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 200DEC83F14 for ; Sun, 27 Aug 2023 11:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229876AbjH0LvM (ORCPT ); Sun, 27 Aug 2023 07:51:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbjH0Lur (ORCPT ); Sun, 27 Aug 2023 07:50:47 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B62C6194 for ; Sun, 27 Aug 2023 04:50:40 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-5007616b756so3684599e87.3 for ; Sun, 27 Aug 2023 04:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137039; x=1693741839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RE7HOe0pcemwQjf6HadDywbH9N0H3cGYSXkFuYxT2Qk=; b=shSk0f0FHs/9hv48+jI6S+O+GL1A2N0XfyOsF0BKvw2XRUECnHATfhqyxlOGAILHTG TdXxwufhz4wW3drK9QQoccPaM6dt/b4s0H2kUaYGqjlViDg+kPJEN8XHd4JApbPlGHnN bKtWRRL9Hqb/udg2WEB05f0PAmh5o0+DDuW9NgS8hQgNA4t4fEXX3fkwsVlf8ubBkhOg r/L+a3Mr1LIQ+jZL02r/mnaK0q/7Lg/qvg+GxUeTsLmcFliHM267Uk9CgeCdtSrpKn1t q6RTc1uDKEkMBq7oALwzET/rDbDIyWWjAXzLlpWBFphdxLVxvvMei8WtIJjHECp/HZCE k0SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137039; x=1693741839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RE7HOe0pcemwQjf6HadDywbH9N0H3cGYSXkFuYxT2Qk=; b=cs7UHhI9iOJNfrr3zu9dj8wv0RE2jw+9bYOIS8pv1DCulqz30msMjqsfSwqsE0RQyq E9lydWUaAZHY8LIH2+AL9WKsix68VF5aF8FDtVjBaExQbLPqLLuOQzXuCAdr6AWCSX6J 27/aQZDHL1tpKHV1iteDEvzyLSAJ9S2mo7XspltZj3g27RJ+OHaAy7TcApCs9kDzOuSS u9Nu+k4B7TTLN61wkqBgEyiE5Aam+fq1zyeGhKRmRDCpZfHSqRWZQEoJIzJY5+XoVG3p ge0ZgArKJuJETWEDWem6sYtciYvWpxYrZn/3WijXipBm/G2VyYVR7ry9wzOHcSgY4E2a qlvw== X-Gm-Message-State: AOJu0Yxk9cJZSeKdKOmsfZwmcSlq7TDHPrtDwPUp6pFYmHIiDfcNkArh pPp02Yrhpmq5qZN87juAOzIP2g== X-Google-Smtp-Source: AGHT+IEPJHYwp4cS/Ene382b2GGakTS+bBTqFA1XKuPxc0KSNbgoOKH7eGQQvy0xVSJaTV5xSgVjXQ== X-Received: by 2002:a19:7617:0:b0:4fd:fd97:a77b with SMTP id c23-20020a197617000000b004fdfd97a77bmr15120494lff.50.1693137038977; Sun, 27 Aug 2023 04:50:38 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 05/23] interconnect: icc-clk: add support for scaling using OPP Date: Sun, 27 Aug 2023 14:50:15 +0300 Message-Id: <20230827115033.935089-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sometimes it might be required to scale the clock using the OPP framework (e.g. to scale regulators following the required clock rate). Extend the interconnec-clk framework to handle OPP case in addition to scaling the clock. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/icc-clk.c | 13 +++++++++++-- include/linux/interconnect-clk.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index d787f2ea36d9..45ffb068979d 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -7,10 +7,13 @@ #include #include #include +#include struct icc_clk_node { + struct device *dev; struct clk *clk; bool enabled; + bool opp; }; struct icc_clk_provider { @@ -25,12 +28,16 @@ struct icc_clk_provider { static int icc_clk_set(struct icc_node *src, struct icc_node *dst) { struct icc_clk_node *qn = src->data; + unsigned long rate = icc_units_to_bps(src->peak_bw); int ret; if (!qn || !qn->clk) return 0; - if (!src->peak_bw) { + if (qn->opp) + return dev_pm_opp_set_rate(qn->dev, rate); + + if (!rate) { if (qn->enabled) clk_disable_unprepare(qn->clk); qn->enabled = false; @@ -45,7 +52,7 @@ static int icc_clk_set(struct icc_node *src, struct icc_node *dst) qn->enabled = true; } - return clk_set_rate(qn->clk, icc_units_to_bps(src->peak_bw)); + return clk_set_rate(qn->clk, rate); } static int icc_clk_get_bw(struct icc_node *node, u32 *avg, u32 *peak) @@ -106,7 +113,9 @@ struct icc_provider *icc_clk_register(struct device *dev, icc_provider_init(provider); for (i = 0, j = 0; i < num_clocks; i++) { + qp->clocks[i].dev = dev; qp->clocks[i].clk = data[i].clk; + qp->clocks[i].opp = data[i].opp; node = icc_node_create(first_id + j); if (IS_ERR(node)) { diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h index 0cd80112bea5..c695e5099901 100644 --- a/include/linux/interconnect-clk.h +++ b/include/linux/interconnect-clk.h @@ -11,6 +11,7 @@ struct device; struct icc_clk_data { struct clk *clk; const char *name; + bool opp; }; struct icc_provider *icc_clk_register(struct device *dev, From patchwork Sun Aug 27 11:50:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E681C83F25 for ; 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Sun, 27 Aug 2023 04:50:40 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:39 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 06/23] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Date: Sun, 27 Aug 2023 14:50:16 +0300 Message-Id: <20230827115033.935089-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The krait-cc driver still uses struct clk internally. Rewrite it to allocate and register struct clk_hw instead. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/krait-cc.c | 141 ++++++++++++++++-------------------- 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 410ae8390f1c..a37abbd31f50 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -13,17 +13,9 @@ #include #include -#include "clk-krait.h" - -enum { - cpu0_mux = 0, - cpu1_mux, - cpu2_mux, - cpu3_mux, - l2_mux, +#include - clks_max, -}; +#include "clk-krait.h" static unsigned int sec_mux_map[] = { 2, @@ -235,7 +227,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s .parent_data = p_data, .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }; struct clk_hw *clk; char *hfpll_name; @@ -324,19 +316,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux return pri_mux; } -static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -{ - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - - if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return clks[idx] ? : ERR_PTR(-ENODEV); -} - static const struct of_device_id krait_cc_match_table[] = { { .compatible = "qcom,krait-cc-v1", (void *)1UL }, { .compatible = "qcom,krait-cc-v2" }, @@ -344,60 +323,84 @@ static const struct of_device_id krait_cc_match_table[] = { }; MODULE_DEVICE_TABLE(of, krait_cc_match_table); +static int krait_clk_reinit(struct clk_hw *hw, int cpu) +{ + struct clk *clk; + unsigned long cur_rate, aux_rate; + char name[5]; /* CPUn */ + + if (cpu == -1) + strcpy(name, "L2"); + else + snprintf(name, sizeof(name), "CPU%d", cpu); + + clk = clk_hw_get_clk(hw, clk_hw_get_name(hw)); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + aux_rate = 384000000; + + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { + pr_info("%s @ Undefined rate %lu. Forcing new rate.\n", + name, cur_rate / 1000); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); + pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000); + + clk_put(clk); + + return 0; +} + +/* Krait configurations have at most 4 CPUs and one L2 */ +#define KRAIT_NUM_CLOCKS 5 + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; - int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; + int cpu, ret; + struct clk_hw *clk; + struct clk_hw_onecell_data *clks; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1); if (IS_ERR(clk)) return PTR_ERR(clk); if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); + clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2); if (IS_ERR(clk)) return PTR_ERR(clk); } - /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL); if (!clks) return -ENOMEM; + clks->num = KRAIT_NUM_CLOCKS; + BUILD_BUG_ON(KRAIT_L2 >= KRAIT_NUM_CLOCKS); + for_each_possible_cpu(cpu) { - mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(mux)) - return PTR_ERR(mux); - clks[cpu] = mux->clk; + clk = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[cpu] = clk; } - l2_pri_mux = krait_add_clks(dev, -1, id->data); - if (IS_ERR(l2_pri_mux)) - return PTR_ERR(l2_pri_mux); - clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init - * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the - * refcount of these clocks. Any cpufreq/hotplug manager can assume - * that the clocks have already been prepared and enabled by the time - * they take over. - */ - for_each_online_cpu(cpu) { - clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } + clk = krait_add_clks(dev, -1, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[KRAIT_L2] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -410,31 +413,13 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { - pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } + krait_clk_reinit(clks->hws[KRAIT_L2], -1); + for_each_possible_cpu(cpu) + krait_clk_reinit(clks->hws[cpu], cpu); - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } - - of_clk_add_provider(dev->of_node, krait_of_get, clks); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); + if (ret) + return ret; return 0; } From patchwork Sun Aug 27 11:50:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D991C83F2C for ; Sun, 27 Aug 2023 11:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229891AbjH0LvO (ORCPT ); Sun, 27 Aug 2023 07:51:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjH0Luv (ORCPT ); Sun, 27 Aug 2023 07:50:51 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFE1718D for ; Sun, 27 Aug 2023 04:50:42 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2bcc187e0b5so35270201fa.1 for ; Sun, 27 Aug 2023 04:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137041; x=1693741841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yLKGJjqVnU2Wm3Zgin7pA30JtWvao8SZmntEz34aPKQ=; b=hKk3x+Zv5Stkb3C8Elm6a90EI7XMk8yQcRuxikhvRvwchROVpMkm7xFolD8qtVBmDk 6adcp2Yx5D1Y6Yh4Z7ZOZBPIHAg0oOor+qQO9ni01bpQYVrIfpqAglssPtn6/i08vWm8 ork+yMC8gdL9Kus8RSiMNGBU+rVlTfaLI/I8tFm+UGlR29owTQyIcQlP8VM8mk6OC2IC 9pYdggLXqJF/0HTtQV0BeSaEtAxsGQlqOq0NcTsz9ktSL2HiKieIRWQdKxASDAvsmIzk r2g4UtiajpQsb7q2bVCHfUsUK8ot4Rvyfqw0MFyPpOovKa7EhCFC5B5wfkwmxXfymV3o 7SZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137041; x=1693741841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yLKGJjqVnU2Wm3Zgin7pA30JtWvao8SZmntEz34aPKQ=; b=KU1xENTsb6OquwpuFSRI9Ez5MsKEfodHIkzz/ltQBACRJ/y+MCKO9L0yKYtETyDkop n4qqxTPQ8cttpFjJqQ7NiAcpVaZORJpL5UGODF0VqlAdBeYCi/30b90379w7oIH4Wbfw K6cbN4CP8BsA+Aa7z7LvyAQxuFtDklOhkjBXbaCP+JCubryQW3dbc9QFYqNEYp1Nq+Ad ewWy7q29UU6wZIzbl2/EsjBkfUp3Hb65KW4FCBHwL9uIntaulSJyk8KGMpNISun+iI5a mpZtkJJQJSOLGnmGhMnySeofKX1RitbU2LD/RF2UpFyWrrkoCCVpAjNqxZ/l/Ejy/Xiz ALSw== X-Gm-Message-State: AOJu0YzzXTxmVNAWOJehHsMh7sazJCvT0f80h7h+A5cFqN1bokBtbXRX 1xHINVOxvmg9z7cbvq77sPrqgA== X-Google-Smtp-Source: AGHT+IE82B0W59RE5kDcLVQBQzjElyJ+kGQifs7Z6nM3Eb6+cLGR9AHkSdzhRVD0qO0TI75bkp+Yxw== X-Received: by 2002:a05:6512:282c:b0:4ff:8f45:ab86 with SMTP id cf44-20020a056512282c00b004ff8f45ab86mr19674525lfb.25.1693137041071; Sun, 27 Aug 2023 04:50:41 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:40 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 07/23] soc: qcom: spm: add support for voltage regulator Date: Sun, 27 Aug 2023 14:50:17 +0300 Message-Id: <20230827115033.935089-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 221 ++++++++++++++++++++++++++++++++++++++++- include/soc/qcom/spm.h | 9 ++ 2 files changed, 225 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2f0b1bfe7658..595e2afb2141 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -6,20 +6,40 @@ * SAW power controller driver */ -#include +#include +#include #include #include +#include +#include +#include #include -#include #include -#include #include +#include +#include + +#include + #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +/* These registers might be specific to SPM 1.1 */ +#define SPM_VCTL_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0) +#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16) + +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17) +#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -29,10 +49,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -169,6 +191,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -176,7 +202,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -187,6 +218,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -238,6 +273,181 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vctl, data0, data1, avs_ctl, sts; + unsigned int vlevel, volt_sel; + bool avs_enabled; + + volt_sel = drv->volt_sel; + vlevel = volt_sel | 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); + data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = volt_sel; + unsigned int min_avs = max(max_avs, 4U) - 4; + + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, tie it to CPU0 */ + + return 0; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + drv->reg_cpu = spm_get_cpu(dev); + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -288,6 +498,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -315,7 +526,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..9859ebe42003 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -30,11 +30,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; void spm_set_low_power_mode(struct spm_driver_data *drv, From patchwork Sun Aug 27 11:50:18 2023 Content-Type: text/plain; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 08/23] soc: qcom: Add driver for Qualcomm Krait L2 cache scaling Date: Sun, 27 Aug 2023 14:50:18 +0300 Message-Id: <20230827115033.935089-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a simple driver that handles scaling of L2 frequency and voltages. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/Kconfig | 9 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/krait-l2-cache.c | 160 ++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/soc/qcom/krait-l2-cache.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 715348869d04..1f3040ef551d 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -70,6 +70,15 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_KRAIT_L2_CACHE + tristate "Qualcomm Krait L2 cache scaling" + depends on ARCH_QCOM && ARM || COMPILE_TEST + select INTERCONNECT + select INTERCONNECT_CLK + default ARM_QCOM_CPUFREQ_NVMEM + help + The driver for scaling the L2 cache frequency on Qualcomm Krait platforms. + config QCOM_KRYO_L2_ACCESSORS bool depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index bbca2e1e55bb..4d16e5cdd334 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_QCOM_STATS) += qcom_stats.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o +obj-$(CONFIG_QCOM_KRAIT_L2_CACHE) += krait-l2-cache.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o diff --git a/drivers/soc/qcom/krait-l2-cache.c b/drivers/soc/qcom/krait-l2-cache.c new file mode 100644 index 000000000000..fb0ca9f4797c --- /dev/null +++ b/drivers/soc/qcom/krait-l2-cache.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Random ID that doesn't clash with main qnoc and OSM */ +#define L2_MASTER_NODE 2000 + +static int krait_l2_set_one_supply(struct device *dev, + struct regulator *reg, + struct dev_pm_opp_supply *supply) +{ + int ret; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + return ret; + } + + return 0; +} + +/* vdd-mem and vdd-dig */ +#define NUM_SUPPLIES 2 +static int krait_l2_config_regulators(struct device *dev, + struct dev_pm_opp *old_opp, + struct dev_pm_opp *new_opp, + struct regulator **regulators, + unsigned int count) +{ + struct dev_pm_opp_supply supplies[NUM_SUPPLIES]; + unsigned long old_freq, freq; + int ret; + + if (WARN_ON_ONCE(count != NUM_SUPPLIES)) + return -EINVAL; + + ret = dev_pm_opp_get_supplies(new_opp, supplies); + if (WARN_ON(ret)) + return ret; + + old_freq = dev_pm_opp_get_freq(old_opp); + freq = dev_pm_opp_get_freq(new_opp); + + WARN_ON(!old_freq || !freq); + if (freq > old_freq) { + ret = krait_l2_set_one_supply(dev, regulators[0], &supplies[0]); + if (ret) + return ret; + + ret = krait_l2_set_one_supply(dev, regulators[1], &supplies[1]); + if (ret) { + dev_pm_opp_get_supplies(old_opp, supplies); + krait_l2_set_one_supply(dev, regulators[0], &supplies[0]); + + return ret; + } + } else { + ret = krait_l2_set_one_supply(dev, regulators[1], &supplies[1]); + if (ret) + return ret; + + ret = krait_l2_set_one_supply(dev, regulators[0], &supplies[0]); + if (ret) { + dev_pm_opp_get_supplies(old_opp, supplies); + krait_l2_set_one_supply(dev, regulators[1], &supplies[1]); + + return ret; + } + } + + return 0; +} + +static int krait_l2_probe(struct platform_device *pdev) +{ + struct dev_pm_opp_config krait_l2_cfg = { + .clk_names = (const char * const[]) { NULL, NULL }, + .config_regulators = krait_l2_config_regulators, + .regulator_names = (const char * const[]) { "vdd-mem", "vdd-dig", NULL }, + }; + struct icc_clk_data data[] = { + { .name = "l2", .opp = true }, + }; + + struct device *dev = &pdev->dev; + struct icc_provider *provider; + struct clk *clk; + int ret; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + ret = devm_pm_opp_set_config(dev, &krait_l2_cfg); + if (ret) + return ret; + + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return ret; + + data[0].clk = clk; + provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + platform_set_drvdata(pdev, provider); + + return 0; +} + +static int krait_l2_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_clk_unregister(provider); + + return 0; +} + +static const struct of_device_id krait_l2_match_table[] = { + { .compatible = "qcom,krait-l2-cache" }, + {} +}; +MODULE_DEVICE_TABLE(of, krait_l2_match_table); + +static struct platform_driver krait_l2_driver = { + .probe = krait_l2_probe, + .remove = krait_l2_remove, + .driver = { + .name = "qcom-krait-l2", + .of_match_table = krait_l2_match_table, + .sync_state = icc_sync_state, + }, +}; + +module_platform_driver(krait_l2_driver); + +MODULE_DESCRIPTION("Qualcomm Krait L2 scaling driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Aug 27 11:50:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5BA1C83F17 for ; Sun, 27 Aug 2023 11:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbjH0LvO (ORCPT ); Sun, 27 Aug 2023 07:51:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbjH0Lux (ORCPT ); Sun, 27 Aug 2023 07:50:53 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F97C1BB for ; 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Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 09/23] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Date: Sun, 27 Aug 2023 14:50:19 +0300 Message-Id: <20230827115033.935089-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index 329c2546aa0a..b60761290156 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -224,9 +224,9 @@ pm8921_s1: s1 { bias-pull-down; }; - /* msm otg HSUSB_VDDCX */ + /* msm otg HSUSB_VDDCX and VDD_DIG */ pm8921_s3: s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -310,6 +310,12 @@ pm8921_l23: l23 { bias-pull-down; }; + /* VDD_MEM */ + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + /* * tabla2x-slim-CDC_VDDA_A_1P2V * tabla2x-slim-VDDD_CDC_D @@ -338,8 +344,12 @@ pm8921_lvs6: lvs6 { /* * mipi_dsi.1-dsi1_vddio * pil_riva-pll_vdd + * HFPLL regulator */ pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; }; From patchwork Sun Aug 27 11:50:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA6A7C83F1A for ; Sun, 27 Aug 2023 11:51:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbjH0LvQ (ORCPT ); Sun, 27 Aug 2023 07:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjH0Luy (ORCPT ); Sun, 27 Aug 2023 07:50:54 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1650C1A2 for ; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-5009969be25so3703368e87.3 for ; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137043; x=1693741843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8KDBrUFxvk4wsTAEzsTm5KMoDepnn6zKvijV8dmMWVs=; b=eJa3SO1MWfrCt2LNj05Qv9mIV6/g1KqTjVMc9StVLX+7K2UsfVYbvYYPdhjSEC9SEP alDsRDcjK5GAyOf82KiDDT3+eihTCIEQ12wuRf9hxmYtt8ZWrmUyow2BOfyabtieURyS +RBcJF+e+dSWGy6Nyk5/p/rAxvADSvJy1d5G33FFU2PMdNEEq5lccF64BdKWnrd/xEdf Fqz4Wp3g/e2syVC8KfOOLe4tis/g9kYohGasBlah+0RS6aoSSgmIOgbRzpJUc1PcR0ZR 8wyawiHd17tJDZZsB5iH30HuhiE/F177dmCfRv3wsa6uln3wTqRcfH0+zYx0CwjOvWT4 hCpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137043; x=1693741843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8KDBrUFxvk4wsTAEzsTm5KMoDepnn6zKvijV8dmMWVs=; b=hk/2epNCtvrFPh+WdJBczDFbsU2KJDlDp3GUJaiiXT4/QMocC5bgrvel5P1YlFZ+0K nSQRmiKnQX7+vsdLKb1fNbUB4aB94QKoFqqXTKBe1Yaa+1nP1NzB1YKhch2SlGyPhW1T No7+3BqB3iDDl5AD/6hE0gLSGXOuciL2OKXygGDqwBXVFC0WazDXKHNonyaTVabYAihm wh8CuYQsA0FKRpBeKHo8R8oECb09xssOPpPyMb8VZZIII/al3wWLGGGmI0aj6FBx9F6w ov3xpGVGx1j34rjTxO7rNPG9TLoWj1j3dSs1RIKDp9035PkeNs9bPFeD/3ty8cPIQR7A /APw== X-Gm-Message-State: AOJu0YwvwocF1qqQQAPQrcrCwGIKNEUYdzKVr8a8cPeEJ13OLISTX772 zYrBFOk4YQmLoqrnaTKeKjv3LQ== X-Google-Smtp-Source: AGHT+IGxUZBkVrWP6BMePbUZBlujSEAikUvWhsWK+Cf0yxICxoD31Wz1dbr7xzSwVZ0JIHiwR31lcw== X-Received: by 2002:a05:6512:3150:b0:500:9734:545a with SMTP id s16-20020a056512315000b005009734545amr7821055lfi.5.1693137043478; Sun, 27 Aug 2023 04:50:43 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:43 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 10/23] ARM: dts: qcom: apq8064-cm-qs600: constraint cpufreq regulators Date: Sun, 27 Aug 2023 14:50:20 +0300 Message-Id: <20230827115033.935089-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts index 671d58cc2741..ee071aed9b8d 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -116,8 +116,8 @@ pm8921_s1: s1 { }; pm8921_s3: s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -157,9 +157,23 @@ pm8921_l23: l23 { bias-pull-down; }; + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + pm8921_lvs6: lvs6 { bias-pull-down; }; + + /* HFPLL regulator */ + pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; }; From patchwork Sun Aug 27 11:50:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2AAFC83F32 for ; Sun, 27 Aug 2023 11:51:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229937AbjH0LvQ (ORCPT ); Sun, 27 Aug 2023 07:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230023AbjH0Luy (ORCPT ); Sun, 27 Aug 2023 07:50:54 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1681A3 for ; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-5007c8308c3so3625486e87.0 for ; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137044; x=1693741844; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WVZJg+f84R7PJyB3nirGOnHo9z3XpfKQ1Jd83cypp5Q=; b=NJQTBElmk3IK4FkIvFrV4rT9eYc/8Nq9i8SDIPDdGSYQoVp9WVJBR/LwRECek1gfEL jnSTv5hbAszFfK7LIgZ+dAWeLa8bnmbNVGBvEpibohXckdlaJlFX7zrLP3dPxrlVy1CZ b1K5y0Ty60EKc/yk8m7SkqKxATnhHFIyJvR79j2NG980yY7VT226j1Mx6QwptFd6ppeP ojdmmr9wrj34Tc4WR9gshSx8Jdmf+H7bjDrbG7aheiZuJPNpUXXvz+BwBKeMylPMNlf7 V4Hw3Bda9NpFnUkj2wS+a6LzzX3Pm1tBpEM+W+KxPkUBY7vj/xDdBJ13n/Bs6eoa/SfB vQ7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137044; x=1693741844; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WVZJg+f84R7PJyB3nirGOnHo9z3XpfKQ1Jd83cypp5Q=; b=cbZLBBcFWGHoTqpcpRlI68ZqQ2hygMYyW16McCqOPRGl/SM434/ohBWX+v0C43FPgl xgSJVCrfrQV4Kqb529gKN/KJxBXTyU9NLoLwzbVlxzGu04tNzIxXE7+ezIoKItdm1aam dN/WPgYdVRrlbj3di8i7W491pau679hqHKA2K02SiCEviPqZD2zq/fAi+2CC7VsfuJ9g V/P9uWbSMdbm0uAcD/UjPmPcy5viTKb7DrJDQicPWG++T9GXIla5Fkp6PffUyAKUOm9T xXegXqxLVOWmodVFoHMdq5XyeukXe8jIfDNu053acVxUU2aOhM5MkTF83HHIWavXuiTe Y7lw== X-Gm-Message-State: AOJu0Yzc0xRugFyWEnqpGfytfxcEzMuyAeMnM9bJIgJSkq2fjSxdHuCh HAaM1KxogxpeQqczfpiNgbMDDMHXfe+9AnEwq7w= X-Google-Smtp-Source: AGHT+IFXwNmLKwO0eU+BnV6btdlQbqS9/6m3vHIjGJkMwbt3gumalz1+cSPtBK5eKpvAFd0Xbb39pg== X-Received: by 2002:a05:6512:33c1:b0:4ff:a23b:de27 with SMTP id d1-20020a05651233c100b004ffa23bde27mr3461549lfg.50.1693137044233; Sun, 27 Aug 2023 04:50:44 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:43 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 11/23] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators Date: Sun, 27 Aug 2023 14:50:21 +0300 Message-Id: <20230827115033.935089-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index 3078afda37c6..062c9cf4ec77 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -227,8 +227,8 @@ pm8921_s1: s1 { }; pm8921_s3: s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -274,6 +274,12 @@ pm8921_l23: l23 { bias-pull-down; }; + pm8921_l24: l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + pm8921_lvs1: lvs1 { bias-pull-down; }; @@ -282,6 +288,14 @@ pm8921_lvs6: lvs6 { bias-pull-down; }; + /* HFPLL regulator */ + pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + pm8921_hdmi_switch: hdmi-switch { bias-pull-down; }; From patchwork Sun Aug 27 11:50:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BC72C83F39 for ; Sun, 27 Aug 2023 11:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229927AbjH0LvQ (ORCPT ); Sun, 27 Aug 2023 07:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230038AbjH0Luz (ORCPT ); Sun, 27 Aug 2023 07:50:55 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACC8619B for ; Sun, 27 Aug 2023 04:50:46 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-50078e52537so3519074e87.1 for ; Sun, 27 Aug 2023 04:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137045; x=1693741845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZJKq5xqa+IkQt1yiAXdQVIWb4sugXk36NSJJNWDebJk=; b=A0EuRbs7w/GtYN7EPG/qGlkn7jtItAW+oh70XoHfcCvMTiW9LG0/GoJyMKM6ZAupuN 3yhR1kFQaT2qDNzObuUqgK8R+Scnvw6nA/nPC+bYGRTTXQV0ITnt3WxaWqYU3AIa7N5Z FqWILKhXCpKxLaYU9Q8dtDS/SwU2EoouoePf0zCJ7YKIN3MGO6fmQ15unr3hAYx8Q96X VvGBX2uMPN6TgA1u7Ne3zTf4HBAgBMJ8g/BngME292jPqG3Mctq61MDDHNGT3NWTBR6X EGEBQdtj2THKTe1gue+9ByQn4YWcO2uBYutCgN4IMIGZRAJu4gapeuGmo5iKNsgvyqTi e9mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137045; x=1693741845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZJKq5xqa+IkQt1yiAXdQVIWb4sugXk36NSJJNWDebJk=; b=aTmoLMcnDszy8BQwJwqju9SszxEkpR0jhFusE2v+w4pM/Bh5M/hYoPR60zKix6y9Ys XcqY6y89YStP3dDYyd5NL/lDtJl69VOjgRZA78H0qOcDPU9SbijWBYNrxVeEanVNUOPO gMef7JiEF0qCEBocChSwAFpvrgVWaIBw7t78KczTgsNTq1GCLJwiNBEDmLt1ucsj2xhZ fWYrUqXVy3234b0XTJB4EKV9M2peeGibiDpwUQSpcF9HSFK0F33vgbL0hVWJRlXifr73 uGUsidQSWooLHRCMgb2ChnYkARTyyQAhPR5vS4sUW0LDnR4AWE0F+BxzW4jnZw2V1Ey5 zXrw== X-Gm-Message-State: AOJu0YyCe3hZW+DF3hOF5SKj2XQny7mSDl/hD74bOE1oFYgFabwQbcfF wKm80xG8FdMKh9EGsnhY0vgnPw== X-Google-Smtp-Source: AGHT+IH4vwUEa9C4O3F5XVX0DJ4Bmcnok2/i5QVe/7kjqRQk9U1QsVR59T4Dyn6xMcYMfwEuFRfyuA== X-Received: by 2002:a05:6512:32cc:b0:4fb:90c6:c31a with SMTP id f12-20020a05651232cc00b004fb90c6c31amr20255459lfg.14.1693137045037; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:44 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 12/23] ARM: dts: qcom: apq8064-sony-xperia-lagan-yuga: constraint cpufreq regulators Date: Sun, 27 Aug 2023 14:50:22 +0300 Message-Id: <20230827115033.935089-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 2412aa3e3e8d..5b911e5f0b55 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -139,7 +139,7 @@ pm8921_s2: s2 { }; pm8921_s3: s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; bias-pull-down; @@ -290,7 +290,7 @@ pm8921_l23: l23 { }; pm8921_l24: l24 { - regulator-min-microvolt = <750000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1150000>; bias-pull-down; }; @@ -344,7 +344,11 @@ pm8921_lvs6: lvs6 { bias-pull-down; }; + /* HFPLL regulator */ pm8921_lvs7: lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; From patchwork Sun Aug 27 11:50:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E02C3C83F33 for ; Sun, 27 Aug 2023 11:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229941AbjH0LvR (ORCPT ); Sun, 27 Aug 2023 07:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjH0Lu4 (ORCPT ); Sun, 27 Aug 2023 07:50:56 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7568119A for ; Sun, 27 Aug 2023 04:50:47 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-500760b296aso2789879e87.0 for ; Sun, 27 Aug 2023 04:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137046; x=1693741846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6+5JyGg/RVsbvystfdqTjelqQjEsUcHgseGOGd0sd2A=; b=aSTNedRj9jCe9y3t0hQnZaMJKHOiM0JuipUnX25XmiichKI6Tfjv9PE7skbef6vDa+ xWwqvtfP2znXpUE2t5x1T4/rxfpUnayLBxI1+aiKgCrwSTxPGH/8SgXxP5DqLW9F0WkT FrBZJk+sDiO66q1XRPkDEJzrFcwSNW5QsxQBKAy+HLC5if2hmeb/zlst432oX0I20Ioi bKqNGSjXccv/c4lTuC1NfTacWyfd0Ezj/DnvBnl9jSQUDu7IOfcdrNtXlQikfpOdMdju PfJ4p0ddG5blYbqPPXo94o67P+4FoSKjKjRleq2WMP8WPOphB5qAwmeSBCbBNXL3yCfR K5Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137046; x=1693741846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6+5JyGg/RVsbvystfdqTjelqQjEsUcHgseGOGd0sd2A=; b=G7bl+JIgiYj2Ve0kz+/bk6KvBQSReO/VnCLiMMaITfFU3wJuCdmbUPpeUs9dquv88n 4LJE0Gv7lqUpg5vVmEK2oeW4zpqRNQiwe65qArYmi67V+9SeNhfYUtS3D7FUNgZ4EB9W jaPwnhG4AxvRwXfh+jaYDuDoE/YfdvUSYBkJ/raJf/MPQN5Y6NwiUykQzIkLwKwLwuqu rWQk4xDA1NeZp2ACzf6uvDzu2km+2eJzApiV4EHwGdO2Xum52cbsIxymouPcTV56c4U+ oM2ff32GAte3R6uFlXbrpRJQz2XfU2ZfL32sc8/qSSocVgnocv0v/9t7W/x+BljqVK8d OqRw== X-Gm-Message-State: AOJu0YyLMS/s5fhQyitC3Rn5naC2SCJ9N7zvlRIfmgC0W3ouogdCoB69 onbVr8cbdDl0NrYlWO2t4TVSxVuIva2PhtN2Z8I= X-Google-Smtp-Source: AGHT+IERPpheMJF2+A8ACb1ozqTwHyIWBqnIUx7wppUVgi9tjaJj72nweT2g1EdhwLJ0NbJZJNpCOQ== X-Received: by 2002:a05:6512:3d01:b0:500:a6c1:d8e0 with SMTP id d1-20020a0565123d0100b00500a6c1d8e0mr2395379lfv.22.1693137045746; Sun, 27 Aug 2023 04:50:45 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:45 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 13/23] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Sun, 27 Aug 2023 14:50:23 +0300 Message-Id: <20230827115033.935089-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5b7d2c6f0ce9..2f94d26fc792 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -365,25 +365,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Sun Aug 27 11:50:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73230CA1016 for ; Sun, 27 Aug 2023 11:51:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230010AbjH0LvV (ORCPT ); Sun, 27 Aug 2023 07:51:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbjH0LvC (ORCPT ); Sun, 27 Aug 2023 07:51:02 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C483CC0 for ; Sun, 27 Aug 2023 04:50:55 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-50087d47d4dso3700957e87.1 for ; Sun, 27 Aug 2023 04:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137054; x=1693741854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3iFr5ykSW5K/n9AH6BnSCA7flwWQ6QIykUQHsbJGtbs=; b=ef2gEVG/82XfG0mQrkVAAmk+eVc0NES2QamcfKNnCe/G+DSeRCe5NTwjoITMyTJScN L6FfeR4M3K9jC/nwVhPbzg7WVLI9MC8nR4QulC+GhBdfhdIzMT4zfWcMJXl3NpyR9uDf jMPsVMQpnVz1zB2cUffBSMQk67RHAVGOVVppiEToaKqM/BAeCuyjLH4atdY6kEecaeyl jZGE8lgICQrBeBPRZ/5T6TrN0BjGbehi0t8iaMFi44CfbTPvxzKk1GZDZ8v3ShhhfBIN 7p6xiwds5Rjd4WnMbjWBQ0OY8HypUPkinAhrr+mmy+02JRf8WvfMGZTlLL4tG6XlqHjq EgPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137054; x=1693741854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3iFr5ykSW5K/n9AH6BnSCA7flwWQ6QIykUQHsbJGtbs=; b=bZRPMLngRaxcG1eZrNW/lXfSEmdxyId0EllezSnVKWtpOw37X2m73SqLEi+6VVG5ht 0xIFhdaPdXqVC+lnV4YBUHFlXRrMHJrabK+kjgL3s3g9bpQ15dWRS1akG2u2fAle/sOQ LlxZNbMSwoVPrOTkuX0UIdhVU7l1NpL/V2MBN/9/NLACTVbvNVi+Kt3sNV2uouzQ9zWZ netbER7l7bG1pBxCFvBndqSDp7tNvEjOMBH8I4GgVefy/3QH5anAbCNYFTm4Dx/AtDOS 8v25w4R8jt2Ohva0nVxL++hvrkv2hdYgHdAZN0jM2u3eInsX+R+ke0Z5xqspL+OacmV8 jutw== X-Gm-Message-State: AOJu0YzD2AfrfmDIcVX8Ryu4ScWGOOEY6y2fLWxwQxFCky3PqWu9fgY+ dC0W+k+RRQ4MlVPORxDtIfN50w== X-Google-Smtp-Source: AGHT+IFPncuxEc70hypPWOq9OKWCCPeTxvJl6mRRrmle+JQxUrnM6ogihzRMYLvrTliBMvOHP3qLeQ== X-Received: by 2002:a05:6512:470:b0:500:aec8:cac1 with SMTP id x16-20020a056512047000b00500aec8cac1mr3026380lfd.26.1693137046513; Sun, 27 Aug 2023 04:50:46 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:46 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 14/23] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Sun, 27 Aug 2023 14:50:24 +0300 Message-Id: <20230827115033.935089-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 2f94d26fc792..ba7d5ef8de17 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -368,25 +368,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Sun Aug 27 11:50:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1060FC83F3C for ; Sun, 27 Aug 2023 11:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229950AbjH0LvR (ORCPT ); Sun, 27 Aug 2023 07:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230073AbjH0Lu5 (ORCPT ); Sun, 27 Aug 2023 07:50:57 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E423C1AB for ; Sun, 27 Aug 2023 04:50:48 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-5008faf4456so3586271e87.3 for ; Sun, 27 Aug 2023 04:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137047; x=1693741847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lNgy+1kOBvDlpkUgg/7RVOK6q0mi/Y5ybYzwxVC6iZ8=; b=EAErSifRGyNKlv9rORxPH6lTzaPnvhp/VOI47XAjcHpno2huSHvnJ2OOtVGLNBFG1Q jZ0+IjRDgxFxbOS+N+n+1mgZxcSM5AcaXBzE/l3XBuImmOBqaefn/YOmMgQkHk6t5HO2 6Pd08H6BgZZYvmlNbDovUkLlOB5tcD+WMLujqYMgKzuonLkkn0WVYcUw0gTHol2K/VUw FhImzj6B52NFA3MErp/NkX6VJz+18E3Rtff0XHmoEIKR4C949fOxTZi+NdRgVUBXi8lc rlEugGwIhGKBiGwgAC4/1QFg9cG4lP3rJPW9caQE62GVFaCt/7xPUKa2wDpr1yCyNYvk xzWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137047; x=1693741847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lNgy+1kOBvDlpkUgg/7RVOK6q0mi/Y5ybYzwxVC6iZ8=; b=RXLN+davCoqk2Ky/DYMwjEDwSLh6lBTop/5kPGaNHAT2xZY8RVML3L95tg/Z9elbYu piHKwrEMeiu4EA6JljoZVsaceYKIOGrj4b6UaPBoIzKjuHCxw8FE7TcTwWj41feeOE+C oI9z4YQOjnH6PopQJ1JD/moignHDeoX7AdQpwdxNcx8ekRqxp8iHsYQMwuHRqUxhy3AU Cw5Fp56D2DW2NscS0/68a6U0t1CbOGyZFiqF8Gq5I2dAPLgHusXVni49ov4S671CX6GM JIa9xdDrIfUx4DO/5zmmXVQgLVV/m5SSX3p+LoBA5w3rl/dc06WPxoDQOIsIie2Crgxb vZkw== X-Gm-Message-State: AOJu0Yw6FA9MiJTxAAPOpzIXfUeLnxdeqnzn6o5v3eYOX57ODtv+yMiF SkxiDq5x5aOf6RAjFxqY6PEy1A== X-Google-Smtp-Source: AGHT+IFOUuEs2+5V+8gsH1thwMWdka3F0S7ngE1D4jTdGG2M2mHZMZPDCWIMV585xdCa2/n/ri92AQ== X-Received: by 2002:a05:6512:3d8b:b0:4ff:80d4:e12f with SMTP id k11-20020a0565123d8b00b004ff80d4e12fmr18410281lfv.60.1693137047307; Sun, 27 Aug 2023 04:50:47 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:46 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 15/23] ARM: dts: qcom: apq8064: add Krait clock controller Date: Sun, 27 Aug 2023 14:50:25 +0300 Message-Id: <20230827115033.935089-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device node for the clock controller for the CPU cores and L2 clocks. It will be further used by the L2 and by the CPUfreq nodes. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ba7d5ef8de17..a05e64bff07f 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, + <&gcc PLL10>, + <&gcc PLL16>, + <&gcc PLL17>, + <&gcc PLL12>, + <&acc0>, + <&acc1>, + <&acc2>, + <&acc3>, + <&l2cc>; + clock-names = "hfpll0", + "hfpll1", + "hfpll2", + "hfpll3", + "hfpll_l2", + "acpu0_aux", + "acpu1_aux", + "acpu2_aux", + "acpu3_aux", + "acpu_l2_aux"; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_wrapper_mutex 0x604 0x4>; From patchwork Sun Aug 27 11:50:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90609C83F3B for ; Sun, 27 Aug 2023 11:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229956AbjH0LvS (ORCPT ); Sun, 27 Aug 2023 07:51:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbjH0Lu6 (ORCPT ); Sun, 27 Aug 2023 07:50:58 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB91E195 for ; Sun, 27 Aug 2023 04:50:49 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-5008faf4456so3586285e87.3 for ; Sun, 27 Aug 2023 04:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137048; x=1693741848; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jGL0BWRJKPfl8oger7j3JrfqT3+nXc/9EFQqXlrE5Ig=; b=QPgOAQIumn8IWNtnwbrmxegPRxzIXf/bCEdQVjz85Sy8RmLJeNxcrXpIYkQXFt/Yjr +mhFW4s0tsJg2YoTm+2Xqw+AvUufoA1tRhiPshQicm/MpMD5Kw4L1253Tj6c0Wd2w6mD V2acviL0t9rAehVMpRKEyYt+k7ksI95uEIn9VcmJuVpJFJHPidsm9xji8hpfnishrz9S WAYCu5FacM2pGFrIOXg2DsCIehEWBgSpwd+J8OHlY1kslMHyU8OgGXtBVbXuJAHjfJKv d8wOg1XNp1zcUhPkBGiXQ0I51JhYolLOLrqh00xDEHhGBse+s0f4DfIaDPCOTLxbRBja 0dxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137048; x=1693741848; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGL0BWRJKPfl8oger7j3JrfqT3+nXc/9EFQqXlrE5Ig=; b=XA0Z9dsheZiaejV+730+eofRLsJ55bc11mpLHa8PJv4HumChIsePQjmi8NpPGPbS6j +/1RYeLVkN30ifnhcqq0OmLcWx0U4QE6JOd/mHUjVTwCvaZg+Dur3v3dasQwrJ/hy/rZ /UNw+H24e6qOpVgZwr0XnfqUvjl+6vsoslqlKdYdseHRxkXZmSJefql+r9S+5tMzZUdX RmYE/X5eFDbyZKwkeqoctDiTS5XofSH6ZHUgGxxfGkZtzhL2b0cGmXF9DxyHJKARjLyS oEMZfqDYc7W3pLZZ1ITIoCwvYpyAXed6A51AGiWmxtn4SWWb6tChUTic0UlP4q71d6LR OyKA== X-Gm-Message-State: AOJu0Yw+Atj4Tm98q+7n+TdtbOvPSAEpGFykpTkT5LanW8q5WwgEMtbz nrv8cQFNWh9jkUQSwtdU8aiUsQ== X-Google-Smtp-Source: AGHT+IEL2U8FotRdtR+0JKbrKDc/HrSAwGHsKFfKUOe/JBFKtQwwvTjjHXf8Zt+r+f/AzI4NLQifRA== X-Received: by 2002:a05:6512:2256:b0:500:808c:9ee6 with SMTP id i22-20020a056512225600b00500808c9ee6mr15671753lfu.6.1693137048073; Sun, 27 Aug 2023 04:50:48 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:47 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 16/23] ARM: dts: qcom: apq8064: add L2 cache scaling Date: Sun, 27 Aug 2023 14:50:26 +0300 Message-Id: <20230827115033.935089-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Populate L2 cache node with clock, supplies and OPP information to facilitate scaling L2 frequency. Signed-off-by: Dmitry Baryshkov --- .../dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 5 + .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 5 + .../boot/dts/qcom/qcom-apq8064-ifc6410.dts | 5 + .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 5 + arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 100 +++++++++++++++++- 5 files changed, 119 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index b60761290156..a8f826f0479a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -78,6 +78,11 @@ reboot-mode { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &dsi0 { vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ vdd-supply = <&pm8921_l8>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts index ee071aed9b8d..7372f62fa31d 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -35,6 +35,11 @@ v3p3_fixed: regulator-v3p3 { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi1 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index 062c9cf4ec77..ddc69496100a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -69,6 +69,11 @@ ext_3p3v: regulator-ext-3p3v { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi1 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 5b911e5f0b55..8e0c12d406f6 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -57,6 +57,11 @@ key-volume-up { }; }; +&L2 { + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; +}; + &gsbi5 { qcom,mode = ; status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index a05e64bff07f..21990ca5851a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include #include #include @@ -81,9 +82,106 @@ CPU3: cpu@3 { }; L2: l2-cache { - compatible = "cache"; + compatible = "qcom,krait-l2-cache", "cache"; cache-level = <2>; cache-unified; + clocks = <&kraitcc KRAIT_L2>; + #interconnect-cells = <1>; + operating-points-v2 = <&l2_opp_table>; + + l2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <1050000 1050000 1150000>, + <950000 950000 1150000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1050000 1050000 1150000>, + <1050000 1050000 1150000>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-756000000 { + opp-hz = /bits/ 64 <756000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-972000000 { + opp-hz = /bits/ 64 <972000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-microvolt = <1150000 1150000 1150000>, + <1150000 1150000 1150000>; + }; + }; }; idle-states { From patchwork Sun Aug 27 11:50:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0EBEEE49B3 for ; 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Sun, 27 Aug 2023 04:50:48 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:48 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 17/23] ARM: dts: qcom: apq8064: add simple CPUFreq support Date: Sun, 27 Aug 2023 14:50:27 +0300 Message-Id: <20230827115033.935089-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Declare CPU frequency-scaling properties. Each CPU has its own clock, how all CPUs have the same OPP table. Voltage scaling is not (yet) enabled with this patch. It will be enabled later. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 483 +++++++++++++++++++++++ 1 file changed, 483 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 21990ca5851a..f08d87bcc37e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include / { @@ -46,6 +47,13 @@ CPU0: cpu@0 { qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_0>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw0_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -57,6 +65,13 @@ CPU1: cpu@1 { qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_1>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw1_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -68,6 +83,13 @@ CPU2: cpu@2 { qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_2>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw2_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -79,6 +101,13 @@ CPU3: cpu@3 { qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_3>; + clock-names = "cpu"; + clock-latency = <100000>; + vdd-core-supply = <&saw3_vreg>; + interconnects = <&L2 MASTER_KRAIT_L2 &L2 SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -195,6 +224,454 @@ CPU_SPC: spc { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + /* Voltage thresholds are */ + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <384000>; + opp-microvolt-speed0-pvs0 = <950000 950000 975000>; + opp-microvolt-speed0-pvs1 = <925000 900000 950000>; + opp-microvolt-speed0-pvs3 = <875000 850000 900000>; + opp-microvolt-speed0-pvs4 = <875000 850000 900000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + /* + * higher latency as it requires switching between + * clock sources + */ + clock-latency-ns = <244144>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed0-pvs1 = <950000 925000 975000>; + opp-microvolt-speed0-pvs3 = <900000 875000 925000>; + opp-microvolt-speed0-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <875000 875000 875000>; + opp-supported-hw = <0x4007>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed0-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed0-pvs3 = <925000 900000 950000>; + opp-microvolt-speed0-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs0 = <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed0-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs3 = <950000 925000 975000>; + opp-microvolt-speed0-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs0 = <962500 962500 987500>; + opp-microvolt-speed1-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs2 = <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <962500 962500 987500>; + opp-microvolt-speed14-pvs1 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs2 = <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <900000 875000 925000>; + opp-supported-hw = <0x4007>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed0-pvs1 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed0-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed1-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs2 = <962500 937500 987500>; + opp-microvolt-speed1-pvs3 = <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <912500 887500 937500>; + opp-microvolt-speed1-pvs5 = <912500 887500 937500>; + opp-microvolt-speed1-pvs6 = <912500 887500 937500>; + opp-microvolt-speed2-pvs0 = <962500 962500 987500>; + opp-microvolt-speed2-pvs1 = <937500 937500 937500>; + opp-microvolt-speed2-pvs2 = <937500 912500 962500>; + opp-microvolt-speed2-pvs3 = <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <912500 887500 937500>; + opp-microvolt-speed2-pvs5 = <912500 887500 937500>; + opp-microvolt-speed2-pvs6 = <912500 887500 937500>; + opp-microvolt-speed14-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed14-pvs1 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs2 = <962500 937500 987500>; + opp-microvolt-speed14-pvs3 = <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <912500 887500 937500>; + opp-microvolt-speed14-pvs5 = <887500 887500 887500>; + opp-microvolt-speed14-pvs6 = <912500 887500 937500>; + opp-supported-hw = <0x4007>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed0-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed0-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed0-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed1-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs3 = <950000 925000 975000>; + opp-microvolt-speed1-pvs4 = <925000 900000 950000>; + opp-microvolt-speed1-pvs5 = <925000 900000 950000>; + opp-microvolt-speed1-pvs6 = <925000 900000 950000>; + opp-microvolt-speed2-pvs0 = <975000 975000 1000000>; + opp-microvolt-speed2-pvs1 = <950000 950000 950000>; + opp-microvolt-speed2-pvs2 = <950000 925000 975000>; + opp-microvolt-speed2-pvs3 = <937500 912500 962500>; + opp-microvolt-speed2-pvs4 = <925000 900000 950000>; + opp-microvolt-speed2-pvs5 = <925000 900000 950000>; + opp-microvolt-speed2-pvs6 = <925000 900000 950000>; + opp-microvolt-speed14-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed14-pvs1 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs3 = <950000 925000 975000>; + opp-microvolt-speed14-pvs4 = <925000 900000 950000>; + opp-microvolt-speed14-pvs5 = <900000 900000 900000>; + opp-microvolt-speed14-pvs6 = <925000 900000 950000>; + opp-supported-hw = <0x4007>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed0-pvs1 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed1-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs4 = <950000 925000 975000>; + opp-microvolt-speed1-pvs5 = <950000 925000 975000>; + opp-microvolt-speed1-pvs6 = <950000 925000 975000>; + opp-microvolt-speed2-pvs0 = <1000000 1000000 1025000>; + opp-microvolt-speed2-pvs1 = <975000 975000 975000>; + opp-microvolt-speed2-pvs2 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs3 = <962500 937500 987500>; + opp-microvolt-speed2-pvs4 = <950000 925000 975000>; + opp-microvolt-speed2-pvs5 = <950000 925000 975000>; + opp-microvolt-speed2-pvs6 = <950000 925000 975000>; + opp-microvolt-speed14-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed14-pvs1 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs3 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs4 = <950000 925000 975000>; + opp-microvolt-speed14-pvs5 = <925000 925000 925000>; + opp-microvolt-speed14-pvs6 = <950000 925000 975000>; + opp-supported-hw = <0x4007>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed0-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs3 = <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs4 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed1-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs5 = <962500 937500 987500>; + opp-microvolt-speed1-pvs6 = <962500 937500 987500>; + opp-microvolt-speed2-pvs0 = <1025000 1025000 1050000>; + opp-microvolt-speed2-pvs1 = <1000000 1000000 1000000>; + opp-microvolt-speed2-pvs2 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs3 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs5 = <962500 937500 987500>; + opp-microvolt-speed2-pvs6 = <962500 937500 987500>; + opp-microvolt-speed14-pvs0 = <1075000 1075000 1100000>; + opp-microvolt-speed14-pvs1 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs2 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs4 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs5 = <937500 937500 937500>; + opp-microvolt-speed14-pvs6 = <962500 937500 987500>; + opp-supported-hw = <0x4007>; + }; + + opp-1242000000 { + opp-hz = /bits/ 64 <1242000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1200000 1200000 1225000>; + opp-microvolt-speed0-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed0-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed1-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed1-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs0 = <1037500 1037500 1062500>; + opp-microvolt-speed2-pvs1 = <1012500 1012500 1012500>; + opp-microvolt-speed2-pvs2 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs3 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs5 = <975000 950000 1000000>; + opp-microvolt-speed2-pvs6 = <975000 950000 1000000>; + opp-microvolt-speed14-pvs0 = <1087500 1087500 1112500>; + opp-microvolt-speed14-pvs1 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs3 = <1012500 987500 1037500>; + opp-microvolt-speed14-pvs4 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs5 = <950000 950000 950000>; + opp-microvolt-speed14-pvs6 = <975000 950000 1000000>; + opp-supported-hw = <0x4007>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed0-pvs1 = <1200000 1175000 1225000>; + opp-microvolt-speed0-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed1-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed1-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed1-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed1-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs0 = <1062500 1062500 1087500>; + opp-microvolt-speed2-pvs1 = <1037500 1037500 1037500>; + opp-microvolt-speed2-pvs2 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs5 = <987500 962500 1012500>; + opp-microvolt-speed2-pvs6 = <987500 962500 1012500>; + opp-microvolt-speed14-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed14-pvs1 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs2 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs3 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs4 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs5 = <962500 962500 962500>; + opp-microvolt-speed14-pvs6 = <987500 962500 1012500>; + opp-supported-hw = <0x4007>; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1237500 1237500 1262500>; + opp-microvolt-speed0-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed0-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed0-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed1-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed1-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed2-pvs0 = <1100000 1100000 1125000>; + opp-microvolt-speed2-pvs1 = <1075000 1075000 1075000>; + opp-microvolt-speed2-pvs2 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs3 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs5 = <1012500 987500 1037500>; + opp-microvolt-speed2-pvs6 = <1000000 975000 1025000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1175000>; + opp-microvolt-speed14-pvs1 = <1137500 1112500 1162500>; + opp-microvolt-speed14-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed14-pvs3 = <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs4 = <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs5 = <987500 987500 987500>; + opp-microvolt-speed14-pvs6 = <1000000 975000 1025000>; + opp-supported-hw = <0x4007>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed0-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed0-pvs3 = <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs4 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs0 = <1162500 1162500 1187500>; + opp-microvolt-speed14-pvs1 = <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs2 = <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs4 = <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs5 = <1000000 1000000 1000000>; + opp-microvolt-speed14-pvs6 = <1012500 987500 1037500>; + opp-supported-hw = <0x4001>; + }; + + opp-1566000000 { + opp-hz = /bits/ 64 <1566000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed1-pvs1 = <1175000 1150000 1200000>; + opp-microvolt-speed1-pvs2 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs3 = <1087500 1062500 1112500>; + opp-microvolt-speed1-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs6 = <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs0 = <1125000 1125000 1150000>; + opp-microvolt-speed2-pvs1 = <1100000 1100000 1100000>; + opp-microvolt-speed2-pvs2 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs3 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs4 = <1062500 1037500 1087500>; + opp-microvolt-speed2-pvs5 = <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs6 = <1025000 1000000 1050000>; + opp-supported-hw = <0x06>; + }; + + opp-1674000000 { + opp-hz = /bits/ 64 <1674000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed1-pvs1 = <1212500 1187500 1237500>; + opp-microvolt-speed1-pvs2 = <1162500 1137500 1187500>; + opp-microvolt-speed1-pvs3 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs6 = <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs0 = <1175000 1175000 1200000>; + opp-microvolt-speed2-pvs1 = <1137500 1137500 1137500>; + opp-microvolt-speed2-pvs2 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs3 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs4 = <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs5 = <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs6 = <1050000 1025000 1075000>; + opp-supported-hw = <0x06>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1250000 1250000 1275000>; + opp-microvolt-speed1-pvs1 = <1225000 1200000 1250000>; + opp-microvolt-speed1-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed1-pvs3 = <1150000 1125000 1175000>; + opp-microvolt-speed1-pvs4 = <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs5 = <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs6 = <1075000 1050000 1100000>; + opp-supported-hw = <0x02>; + }; + + opp-1782000000 { + opp-hz = /bits/ 64 <1782000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1225000 1225000 1250000>; + opp-microvolt-speed2-pvs1 = <1187500 1187500 1187500>; + opp-microvolt-speed2-pvs2 = <1187500 1162500 1212500>; + opp-microvolt-speed2-pvs3 = <1162500 1137500 1187500>; + opp-microvolt-speed2-pvs4 = <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs5 = <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs6 = <1087500 1062500 1112500>; + opp-supported-hw = <0x04>; + }; + + opp-1890000000 { + opp-hz = /bits/ 64 <1890000000>; + opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1287500 1287500 1312500>; + opp-microvolt-speed2-pvs1 = <1250000 1250000 1250000>; + opp-microvolt-speed2-pvs2 = <1237500 1212500 1262500>; + opp-microvolt-speed2-pvs3 = <1200000 1175000 1225000>; + opp-microvolt-speed2-pvs4 = <1175000 1150000 1200000>; + opp-microvolt-speed2-pvs5 = <1150000 1125000 1175000>; + opp-microvolt-speed2-pvs6 = <1125000 1100000 1150000>; + opp-supported-hw = <0x04>; + }; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0>; @@ -796,9 +1273,15 @@ qfprom: qfprom@700000 { #address-cells = <1>; #size-cells = <1>; ranges; + + speedbin_efuse: speedbin@c0 { + reg = <0x0c0 0x4>; + }; + tsens_calib: calib@404 { reg = <0x404 0x10>; }; + tsens_backup: backup_calib@414 { reg = <0x414 0x10>; }; From patchwork Sun Aug 27 11:50:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28D0FCA1000 for ; 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Sun, 27 Aug 2023 04:50:49 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 18/23] ARM: dts: qcom: apq8064: enable passive CPU cooling Date: Sun, 27 Aug 2023 14:50:28 +0300 Message-Id: <20230827115033.935089-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Wire up CPUs and thermal trip points to save the SoC from overheating by lowering the CPU frequency. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index f08d87bcc37e..638b2201ee0d 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -697,6 +698,13 @@ cpu_crit0: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -718,6 +726,13 @@ cpu_crit1: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -739,6 +754,13 @@ cpu_crit2: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -760,6 +782,13 @@ cpu_crit3: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From patchwork Sun Aug 27 11:50:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E8DFCA1005 for ; Sun, 27 Aug 2023 11:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229999AbjH0LvU (ORCPT ); Sun, 27 Aug 2023 07:51:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbjH0LvA (ORCPT ); Sun, 27 Aug 2023 07:51:00 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30BA01AE for ; Sun, 27 Aug 2023 04:50:52 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-5007abb15e9so3555363e87.0 for ; Sun, 27 Aug 2023 04:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137050; x=1693741850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=RxhZlklBSIEl9RVh6fYQFn+9GAm4251u+yLgcNDva21YfyRVnyg89P1GKiM8r3EsE7 xNHpVp94uj9IE8WsXy1i0PWK/BdWRC/U8Z09YdZ9Jxa1O/QLsmNWX5GC6lDVETD8RH9i wp+7Izvl6znwQZC4zl+b2I4lJXmoBC5LMInw6cuEDY77bgGLnsl/Kea8wwYy/sWXa3sq hNHM/RZpB8ivOwin2pMrht71rA6fAfbGx9VX1ZGNI+CKvrZojpuD0MBwMyKA8WGDYjzm brAcZ7qAh2sXn2tY6yx0Pb7LFHnTeRJoHYjkhwm4J2P74t8fyKDqaxpOzZ7Oii4LoJ2v f30Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137050; x=1693741850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=dF9ac9uHman9IZ4Rf338Y2GCEi+EfCE4yOiglYOT7zqvrh/iACYGKbNQc79Vpvb2xi YuASjziv4X844mqnC6xi8+sPdOthAHUxtvamvlGwC9Q6lZ0R3wFDJ7jetBEuPTMKJCLL MkN45vukthmeLQ191SAFlYMHFRJvurFRIov/u4oTYH01H5XWuyuf8qwls/8aHxfjidiy ZPEjA9JMr+vDHoVmDd/rXvfEHB/HTu8M6leqver+SsEwtLcDeVCtE/nQV6bcWVog14cp eIUUJH7Has5gXkcI6XY1Aq7PB2205RkEAoHun0U6ZoBxR04WSpvm9moqlUoT8Y4KVEIG Fqrg== X-Gm-Message-State: AOJu0Ywvp4DHP7dkoc5RL4z0y+PThC8n92v67rKz8T0b73fHWgQAOGpp IUPkzc30NxF+VsJvpmvHb3cX2g== X-Google-Smtp-Source: AGHT+IGf8NtA1/5vzI9NrBVDAVTtPGY5IUZYE/c+ypMVwosM5x6pFbxaoVYhp6r0hbU8e388T1CiNw== X-Received: by 2002:ac2:5631:0:b0:500:771f:4887 with SMTP id b17-20020ac25631000000b00500771f4887mr14170938lff.55.1693137050416; Sun, 27 Aug 2023 04:50:50 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 19/23] ARM: dts: qcom: msm8960: declare SAW2 regulators Date: Sun, 27 Aug 2023 14:50:29 +0300 Message-Id: <20230827115033.935089-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index f420740e068e..0ab340405784 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -223,13 +223,21 @@ acc1: clock-controller@2098000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Sun Aug 27 11:50:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB2ECA1007 for ; Sun, 27 Aug 2023 11:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjH0LvT (ORCPT ); Sun, 27 Aug 2023 07:51:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbjH0LvB (ORCPT ); Sun, 27 Aug 2023 07:51:01 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEC781B3 for ; Sun, 27 Aug 2023 04:50:52 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-50078e52537so3519114e87.1 for ; Sun, 27 Aug 2023 04:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137051; x=1693741851; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uwm1Y1yKYRC2h+rKhVRBCueR16O0EXSdEm7pH6xao2g=; b=zeDkuL9gLDOtGUp3sxh74K4EK+IzvWipMMDLCvIh7VPsj5D8Wu6woMcZV24JehwQyk abgsKoOz5xJ9ncztZWgoax0uIGcnvl0wVOOaAspWHcy/2KJWoVJWNKFk9Pb2KqLCEGUY SumSLkPaRz23E9XHi2TP4RgNr0vFFXiPuS4FLiJm+WRuVYFHbC+9Xa2kh/o1Mr0BQ1gK awkepLX3yifRJ+02dKJ+0U81yaiOcmR+YVkePME1Q0MksupFx/BFfBqpG0fvVwPcf0rb qT7dYTXd+rGUYdUay10BIK+HRXbduQpqTi5q6HBoG9CYA638dIDzcYGQ5n+cNAJkFZUm iiBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137051; x=1693741851; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uwm1Y1yKYRC2h+rKhVRBCueR16O0EXSdEm7pH6xao2g=; b=lsXymSrq4Q1j2Hu3RpGNJykXcHZCSUQOtxVY3MvlqYWmd99bz1krwmjPsL6+um9BLE u0JKtKIZeNf4BD2po+12sx1q2hURiZx+J5g6IkE4owZduhQdv01tPnTbLNUEgq7Cb639 I3eKeNEm/U2gqfMrCSYvyWSAU4Mch1blxA+RT+cqVyQTDHA0qWBw2m5o9uR17DAq3pzt FYVsIi5/W85OBsdT7v72AsjrDDltVfTCQlWD2dRYQXTeKMMSJJnoNs5YM0dVgj293GNG Kw5bUuVkA+4gjsAE8FXBHIgD40d7QNEY9VYhv9Xu/77nqZQ1S4TRZfzU4LPyf2HnteoG mtyQ== X-Gm-Message-State: AOJu0YwIgVg6ayrGQ27Xq+BoiLxSiegsWa437rxSgs8sQRaSrACQ4Epc Gpq4oOZDLjMArujIiv5nDA7l8w== X-Google-Smtp-Source: AGHT+IGFpGW7MeqAUFh8aVAXu7OTE6U1OKVMAOiRtG4IiJPhDohiehKW0Qi1TrQenA9YoNglJnTxqA== X-Received: by 2002:a05:6512:2203:b0:4fe:2efa:b847 with SMTP id h3-20020a056512220300b004fe2efab847mr21623379lfu.23.1693137051233; Sun, 27 Aug 2023 04:50:51 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:50 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 20/23] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device Date: Sun, 27 Aug 2023 14:50:30 +0300 Message-Id: <20230827115033.935089-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 2b1f9d0fb510..24bc2cbfbd96 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Aug 27 11:50:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C2BEC88CB2 for ; Sun, 27 Aug 2023 11:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbjH0LvT (ORCPT ); Sun, 27 Aug 2023 07:51:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230114AbjH0LvB (ORCPT ); Sun, 27 Aug 2023 07:51:01 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F6BE1A2 for ; Sun, 27 Aug 2023 04:50:53 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4ffa01fc987so3942276e87.1 for ; Sun, 27 Aug 2023 04:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137052; x=1693741852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UjiOOSIFD1BfoYfBPled7JeOTQXrWmcDLuPBL1ifAvE=; b=O+xSE724Xiu5eDk7sYPj5FiudsiSeK1M0DXA9G0H9f6HDa3mqnnaJvzIQJflxwGku/ 3xGS3Pc6fI0E2cCq45t67BeSLq+KzV+RIO+v/nWOCCqq2LVVb9SEKJFrhuG3MPSVMsA3 0h4vwVgsgRDCu5uY6vAeME+fky81ORsygJQZrGQPne9dD/L05rpo0ewfdANLJ9JM969v psxb+n3CccYGt8iXYZASnS8keRmKr7znImqmP237eDDMndUANt2rMSz7eqd8Nv5TRGTe h12lr7IUMalaeAYWLkDDyXYmQyPHkZmZgcL/vN8ZLRwXEPHo4ckAyTo5njq92fu2jlOQ vRjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137052; x=1693741852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UjiOOSIFD1BfoYfBPled7JeOTQXrWmcDLuPBL1ifAvE=; b=aF6uoI5Cm8K2VyDY7aG1GZqYmaJjr75JsCAgwk0DpRfQDD/nQvcj5HVMklvA6EdotB h//AfC989kaLwmtTrO/pB+YIZFWdWC6y5jEUu4n5vNl/DJxNl3SbiPsd/Pf4jEPJUqzn TfBqQQoz7EYhEUNHJdgeBkgR3PBupxRNbog/37WFuMeKcTe9phayJgAx5hx1qg8KLMjo 7XkOKOHKK43DDiRefJ5i1TGqaqG+aAnLhtOHg0RtqHTmTtQGNTYu+K8mnWSk0E8emN84 95aE9OiVwZOtOts5lmtbvPBshzel99BmjlbANOUuBRdgIKeQj0fWk4dlArDM9+U+WuS1 nXEw== X-Gm-Message-State: AOJu0Yxjyxr++rPALlpdhE9BppWG5uikYONQwwFl+sstoJhTPbfZo7r1 KGiHtM+bvC1iNEuKY9EL44hT9g== X-Google-Smtp-Source: AGHT+IEE9Bq1tj1Yh5sCK7VPOaAq3m0fBmoO5Fz+8uN1sbCirrWxtwQeJb1kc4gxaz0nYH6PU1fpBw== X-Received: by 2002:a05:6512:282c:b0:4fe:28cd:b3f with SMTP id cf44-20020a056512282c00b004fe28cd0b3fmr7875063lfb.5.1693137051965; Sun, 27 Aug 2023 04:50:51 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:51 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 21/23] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Date: Sun, 27 Aug 2023 14:50:31 +0300 Message-Id: <20230827115033.935089-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index d54be72fe3b2..7d844236de0f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -416,7 +416,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Sun Aug 27 11:50:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 718019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C690CA100F for ; Sun, 27 Aug 2023 11:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230012AbjH0LvU (ORCPT ); Sun, 27 Aug 2023 07:51:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230122AbjH0LvC (ORCPT ); Sun, 27 Aug 2023 07:51:02 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77BB91A3 for ; Sun, 27 Aug 2023 04:50:54 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-5008faf4456so3586347e87.3 for ; Sun, 27 Aug 2023 04:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137053; x=1693741853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/WTwDERDtHj3CTZ7wFbbvBEJPnjqFeRCht0k5iEHuFc=; b=dmgHm7t8uyEXZ57hn44I83Gair3QmORlR0O1aWePu0Stq+4rPWG3H9HMPg8kei19kd Msf4qYkwFLSyojbc7gRXcSfSffjSLsSRDRYp2GpYp8IlydPoqFBVs+KYQ4KTPuS7A0oi a5zi2M5DPkobnqeTroi6OxB21zmae8dVpuNx4SHu1tNXC4pfZYTHcAsIpjUZRG8cgga9 C2Ukftu5UIp0X5iGpkyoZ/jvDiBjF+B0rbCGFad1wbnGBv0QVfbmzYPCQjsBLZ2SLdhp feH1Ve6cm/k0dlaxpgREAUDIPYd6Ry6RHMOsJmzdLA4MOgAdbaSWEMt2qdLYTeuiW3lg S+4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137053; x=1693741853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/WTwDERDtHj3CTZ7wFbbvBEJPnjqFeRCht0k5iEHuFc=; b=SDU/uZfbn+0hoBXQvjV0s6mlPdIYMoQdrAyRhKfXT2sODI3dJolGp4Wo2aTh5esNQt PHOpWyvryezAv7wh0NQ0nY/+yL6fcdGL0QtWSATfgCwo8USuxQ272OqU5cHpo4xOzebF /eBmNJPIs+fRdpKMI64QrMm2MCLklBEhNasKJNejz+2AST6lrWfrvqADq3u4bveUJtom 6O615ejJ+gY7zWqexQ7xX2F/TOlXFmLraOuxVZkjO4xKxQXEEYTuCI7ur73/Cl6UlWVd ME1ooUk3ya3/eWRYGn85zQuCl3jiZ+zhgmYKjBFrmFPVIMNaMDwQ1UXZcvqEiMYSxkFE dD2w== X-Gm-Message-State: AOJu0Yzd9sN+8AF5/pADWiABc6LM9vKeao77rU27+FaFrpNj1f1UIACx okVCq8vpslMnXJWaPmq0aOOS/A== X-Google-Smtp-Source: AGHT+IH5qtw8JTqvFzTu20TNm7+v/svqIabMj4Jzgr64ksxaY0M+LkPYQIJVW8zSI7CmUYmfTuCYSQ== X-Received: by 2002:a05:6512:3f1a:b0:500:aaea:149d with SMTP id y26-20020a0565123f1a00b00500aaea149dmr4514090lfa.46.1693137052753; Sun, 27 Aug 2023 04:50:52 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:52 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 22/23] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices Date: Sun, 27 Aug 2023 14:50:32 +0300 Message-Id: <20230827115033.935089-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 9844e0b7cff9..d7bd97997ff9 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -353,31 +353,26 @@ acc3: power-manager@b0b8000 { saw0: regulator@b089000 { compatible = "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw1: regulator@b099000 { compatible = "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw2: regulator@b0a9000 { compatible = "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw3: regulator@b0b9000 { compatible = "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw_l2: regulator@b012000 { compatible = "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { From patchwork Sun Aug 27 11:50:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 717530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9747CA1010 for ; Sun, 27 Aug 2023 11:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230005AbjH0LvU (ORCPT ); Sun, 27 Aug 2023 07:51:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbjH0LvC (ORCPT ); Sun, 27 Aug 2023 07:51:02 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 253AA1B8 for ; Sun, 27 Aug 2023 04:50:55 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4ff882397ecso3492688e87.3 for ; Sun, 27 Aug 2023 04:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693137053; x=1693741853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rzx9Bm824S2wRWYFO7S2MdJvHvf/jzSVekqRFumNr7k=; b=VKlq61LG7eiUVDlCu1oOs0TkRJTbsYvQqWvjCRgyDh4261NSRyrk6YloVEyca0sTaF 29YwGLcuj6pb1PlsAaw4qGzLFP67VXskypHQxXeV5Qoj1SFR7jCgT0H+msqeKhdMd9+M cDLwdt2Tdlf2U2bSFAIuRR1nqc/1EjZAQakEXu/Oh1IE526FkyhpBnL4ABWEgIlE3tEy juQNJrBC6Z3ON65rfiELxGYXrzkTeM4cmNs4EPGZF2ySaLVaHDq1d4DjwseGf6g5LVt7 vDfduzDIUESXJZ0rz6Ly9LZtPTVI26zgg16V9AGPwTOn3T+ufczczVmkdEFTqBNf0OlG AkNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693137053; x=1693741853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rzx9Bm824S2wRWYFO7S2MdJvHvf/jzSVekqRFumNr7k=; b=ezWVeudQPmqHGaz6KHPUFzeUkwj8HTY4xhSP4bvFxGaz37KqDGAjIzg3X2ZK1vjF/I 0G7TScOxkjUwvDU2jP5Yp9EliXErTWlUc1F2OSEztumj10eVA+XbAG80WosZYjp2Rj3i 6wVsX5lwNgUoz1Rv6xrNWTIkRoh9Y9nRvM9ipcLTeKoxM4I1KfsUAXHGOaZPj+Vx+r+c IliVFjx6jOKiD7WHTZJShuJW6YdY25abisL08F/5uC4Dzch8SF0c9O/5r1AFxuCPjktu 9/7mrJjZjBHmCpSptDRKTLlr3P+ZdjSHDiktoamPYY5+LpULYLnTmFsAXrh+oXSrnQfT +q1A== X-Gm-Message-State: AOJu0Yza2tLEkB+sTSPpB3vS2EgXfrpw3v1MIvWIeca+4hjO6v2XYsqm kWVnnFU15ppF4NB95rQgaaZs4A== X-Google-Smtp-Source: AGHT+IGqlgoo4wUMXLVlAqHZbEMker1couiI+m+u0qpCzAbR2CI/aAjORLP/ZrpQrfkF8v7v6brvrA== X-Received: by 2002:a05:6512:4026:b0:4f9:570c:7b28 with SMTP id br38-20020a056512402600b004f9570c7b28mr20427762lfb.32.1693137053533; Sun, 27 Aug 2023 04:50:53 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id a8-20020a19f808000000b004ff9f88b86esm1114770lff.308.2023.08.27.04.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:50:53 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi , Stephan Gerhold Subject: [PATCH v4 23/23] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices Date: Sun, 27 Aug 2023 14:50:33 +0300 Message-Id: <20230827115033.935089-24-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> References: <20230827115033.935089-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index c3677440b786..191d1cb27cb7 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 { saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 {