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Tue, 29 Aug 2023 19:13:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AA.mail.protection.outlook.com (10.167.243.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.16 via Frontend Transport; Tue, 29 Aug 2023 19:13:33 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 29 Aug 2023 14:13:32 -0500 From: Mario Limonciello To: CC: , , , , , , Mario Limonciello Subject: [PATCH 1/3] pinctrl: amd: Clear `Less2secSts` and `Less10secSts` for GPIO0 Date: Tue, 29 Aug 2023 11:56:25 -0500 Message-ID: <20230829165627.156542-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829165627.156542-1-mario.limonciello@amd.com> References: <20230829165627.156542-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|DM4PR12MB6445:EE_ X-MS-Office365-Filtering-Correlation-Id: fa570ee3-e95f-4074-fc93-08dba8c409dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(39860400002)(346002)(136003)(396003)(1800799009)(451199024)(82310400011)(186009)(46966006)(36840700001)(40470700004)(1076003)(40460700003)(2616005)(4326008)(5660300002)(8676002)(8936002)(83380400001)(47076005)(36756003)(426003)(336012)(36860700001)(40480700001)(26005)(16526019)(6666004)(82740400003)(44832011)(356005)(70206006)(81166007)(7696005)(54906003)(70586007)(316002)(6916009)(478600001)(966005)(41300700001)(2906002)(86362001)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 19:13:33.4184 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa570ee3-e95f-4074-fc93-08dba8c409dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6445 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On systems that don't program GPIO0 through _AEI may still control the power button via this GPIO. When the GPIO master controller register has bit 15 configured for `EnWinBlueBtn` this will cause GPIO 0 to behave differently. If the user presses the button for less than 2 seconds or less than 10 seconds then it is expected that interrupt status must be cleared by the GPIO driver. Reported-by: Luca Pigliacampo Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217833 Fixes: a855724dc08b ("pinctrl: amd: Fix mistake in handling clearing pins at startup") Link: https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/programmer-references/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf p948 Signed-off-by: Mario Limonciello --- drivers/pinctrl/pinctrl-amd.c | 9 +++++++++ drivers/pinctrl/pinctrl-amd.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 74241b2ff21e..37d64fa55b66 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -590,6 +590,7 @@ static const struct irq_chip amd_gpio_irqchip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +#define GPIO0_LESS_TIME (BIT(GPIO0_LESS_2_OFF) | BIT(GPIO0_LESS_10_OFF)) #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) static bool do_amd_gpio_irq_handler(int irq, void *dev_id) @@ -610,6 +611,14 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + /* check GPIO0 specifically for Less2 and Less10 */ + regval = readl(gpio_dev->base); + if (regval & GPIO0_LESS_TIME) { + pm_pr_dbg("GPIO0 was pressed for less than %d seconds\n", + regval & BIT(GPIO0_LESS_10_OFF) ? 10 : 2); + writel(regval | BIT(INTERRUPT_STS_OFF), gpio_dev->base); + } + /* Bit 0-45 contain the relevant status bits */ status &= (1ULL << 46) - 1; regs = gpio_dev->base; diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 34c5c3e71fb2..3ea9a5275845 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -45,6 +45,8 @@ #define WAKECNTRL_Z_OFF 27 #define INTERRUPT_STS_OFF 28 #define WAKE_STS_OFF 29 +#define GPIO0_LESS_2_OFF 30 +#define GPIO0_LESS_10_OFF 31 #define DB_TMR_OUT_MASK 0xFUL #define DB_CNTRl_MASK 0x3UL From patchwork Tue Aug 29 16:56:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 718438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB05C83F1A for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AA.mail.protection.outlook.com (10.167.243.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.16 via Frontend Transport; Tue, 29 Aug 2023 19:13:35 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 29 Aug 2023 14:13:32 -0500 From: Mario Limonciello To: CC: , , , , , , Mario Limonciello Subject: [PATCH 2/3] pinctrl: amd: Add a module parameter to configure power button behavior Date: Tue, 29 Aug 2023 11:56:26 -0500 Message-ID: <20230829165627.156542-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829165627.156542-1-mario.limonciello@amd.com> References: <20230829165627.156542-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|BY5PR12MB4276:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ed928a4-f814-42a1-1649-08dba8c40afb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 19:13:35.2934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ed928a4-f814-42a1-1649-08dba8c40afb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4276 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On pinctrl-amd supported systems there is a bit in the GPIO controller register that controls the debounce behavior. The traditional debounce behavior is configured by software, whereas the 'WinBlue' debounce behavior is handled internally in the GPIO controller and conforms to Microsoft requirements. For any users that find this behavior not desirable, add a module parameter to force the traditional debounce behavior. Signed-off-by: Mario Limonciello --- drivers/pinctrl/pinctrl-amd.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 37d64fa55b66..a2468a988be3 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -36,6 +36,11 @@ #include "pinctrl-utils.h" #include "pinctrl-amd.h" +static int powerbtn = -1; +module_param(powerbtn, int, 0444); +MODULE_PARM_DESC(powerbtn, + "Power button debouncing: 0=traditional, 1=windows, -1=auto"); + static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) { unsigned long flags; @@ -1075,6 +1080,30 @@ static void amd_get_iomux_res(struct amd_gpio *gpio_dev) desc->pmxops = NULL; } +static void handle_powerbtn(struct amd_gpio *gpio_dev) +{ + u32 pin_reg; + + if (powerbtn == -1) + return; + + pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + switch (powerbtn) { + case 0: + pin_reg &= ~INTERNAL_GPIO0_DEBOUNCE; + break; + case 1: + pin_reg |= INTERNAL_GPIO0_DEBOUNCE; + break; + default: + dev_err(&gpio_dev->pdev->dev, "Invalid module parameter %d\n", + powerbtn); + return; + } + + writel(pin_reg, gpio_dev->base + WAKE_INT_MASTER_REG); +} + static int amd_gpio_probe(struct platform_device *pdev) { int ret = 0; @@ -1095,6 +1124,8 @@ static int amd_gpio_probe(struct platform_device *pdev) return PTR_ERR(gpio_dev->base); } + handle_powerbtn(gpio_dev); + gpio_dev->irq = platform_get_irq(pdev, 0); if (gpio_dev->irq < 0) return gpio_dev->irq;