From patchwork Thu Sep 7 16:12:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 720691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2195AEC874D for ; Thu, 7 Sep 2023 18:36:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236726AbjIGSgN (ORCPT ); Thu, 7 Sep 2023 14:36:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231626AbjIGSgM (ORCPT ); Thu, 7 Sep 2023 14:36:12 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AA1C4; Thu, 7 Sep 2023 11:36:02 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1P-DW; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HUz-2h; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 3/6] pwm: dwc: add PWM bit unset in get_state call Date: Thu, 7 Sep 2023 17:12:39 +0100 Message-Id: <20230907161242.67190-4-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v9: - fixed multi-line comment - put authour back to codethink email from sifive v8: - fixed rename issues v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc-core.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 4b4b7b9e1d82..3fc281a78c9a 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -122,24 +122,32 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* + * If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = (ld + 1) * dwc->clk_ns; + period = (ld2 + 1) * dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } state->polarity = PWM_POLARITY_INVERSED; + state->period = period; + state->duty_cycle = duty; pm_runtime_put_sync(chip->dev); From patchwork Thu Sep 7 16:12:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 721324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51D26EC874E for ; Thu, 7 Sep 2023 18:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240655AbjIGSgQ (ORCPT ); Thu, 7 Sep 2023 14:36:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233879AbjIGSgQ (ORCPT ); Thu, 7 Sep 2023 14:36:16 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B501A8; Thu, 7 Sep 2023 11:36:09 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1Q-Gf; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HV4-2m; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 4/6] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Thu, 7 Sep 2023 17:12:40 +0100 Message-Id: <20230907161242.67190-5-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate calculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-König --- v9: - fixed commit spelling - changed to use codethink email instead of sifive v8: - fixup post rename - move to earlier in series --- drivers/pwm/pwm-dwc-core.c | 24 +++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 3fc281a78c9a..3b856685029d 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -49,13 +49,14 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp = state->duty_cycle * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; - tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp = (state->period - state->duty_cycle) * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -121,11 +122,14 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc = to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); + clk_rate = dwc->clk_rate; + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); @@ -137,17 +141,19 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty = (ld + 1) * dwc->clk_ns; - period = (ld2 + 1) * dwc->clk_ns; + duty = ld + 1; + period = ld2 + 1; period += duty; } else { - duty = (ld + 1) * dwc->clk_ns; + duty = ld + 1; period = duty * 2; } + duty *= NSEC_PER_SEC; + period *= NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity = PWM_POLARITY_INVERSED; - state->period = period; - state->duty_cycle = duty; pm_runtime_put_sync(chip->dev); @@ -168,7 +174,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; - dwc->clk_ns = 10; + dwc->clk_rate = NSEC_PER_SEC / 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 64795247c54c..e0a940fd6e87 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -42,7 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) From patchwork Thu Sep 7 16:12:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 720690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A93CDEC874D for ; Thu, 7 Sep 2023 18:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245034AbjIGSgX (ORCPT ); Thu, 7 Sep 2023 14:36:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344154AbjIGSgW (ORCPT ); Thu, 7 Sep 2023 14:36:22 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8765AA8; Thu, 7 Sep 2023 11:36:13 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1R-Ea; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HV9-2r; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 5/6] pwm: dwc: round rate divisions up Date: Thu, 7 Sep 2023 17:12:41 +0100 Message-Id: <20230907161242.67190-6-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As suggested, round up the counter variables to ensure we always produce a longer period calculation. Reported-by: Uwe Kleine-König Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 3b856685029d..6358e3345210 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -50,13 +50,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * 2^32 periods. */ tmp = state->duty_cycle * dwc->clk_rate; - tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + tmp = DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = (state->period - state->duty_cycle) * dwc->clk_rate; - tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + tmp = DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; From patchwork Thu Sep 7 16:12:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 721323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94B53EC8751 for ; Thu, 7 Sep 2023 18:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239636AbjIGSgY (ORCPT ); Thu, 7 Sep 2023 14:36:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344194AbjIGSgX (ORCPT ); Thu, 7 Sep 2023 14:36:23 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4081119AF; Thu, 7 Sep 2023 11:36:16 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1S-Fc; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HVE-2x; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 6/6] pwm: dwc: add of/platform support Date: Thu, 7 Sep 2023 17:12:42 +0100 Message-Id: <20230907161242.67190-7-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks --- v9: - add clk_rate_exclusive_get() to lock clock rate for now - fix email address from sifive to codethink - fix module namespace v8: - add compile test for of-case - add module namespace - move later in the series v7: - fixup kconfig from previous pcie changes v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name --- drivers/pwm/Kconfig | 10 ++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-core.c | 6 +++ drivers/pwm/pwm-dwc-of.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 1 + drivers/pwm/pwm-dwc.h | 1 + 6 files changed, 112 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 507c8b8547a5..22d58cb334e7 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -205,6 +205,16 @@ config PWM_DWC To compile this driver as a module, choose M here: the module will be called pwm-dwc. +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on HAS_IOMEM && (OF || COMPILE_TEST) + select PWM_DWC_CORE + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..e3c867cb13d1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) += pwm-dwc-of.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 6358e3345210..8b4d96d655c7 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,9 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, u32 high; u32 low; + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and @@ -128,6 +132,8 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_get_sync(chip->dev); + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); clk_rate = dwc->clk_rate; ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..30b860484895 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#define DEFAULT_MODULE_NAMESPACE dwc_pwm + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + int ret; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm = nr_pwm; + } + + dwc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk = devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + ret = clk_rate_exclusive_get(dwc->clk); + if (ret) + return dev_err_probe(dev, ret, + "clk_rate_exclusive_get() failed\n"); + + dwc->clk_rate = clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static int dwc_pwm_plat_remove(struct platform_device *pdev) +{ + struct dwc_pwm *dwc = dev_get_drvdata(&pdev->dev); + + clk_rate_exclusive_put(dwc->clk); + return 0; +} + +static const struct of_device_id dwc_pwm_dt_ids[] = { + { .compatible = "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver = { + .driver = { + .name = "dwc-pwm", + .of_match_table = dwc_pwm_dt_ids, + }, + .probe = dwc_pwm_plat_probe, + .remove = dwc_pwm_plat_remove, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index bd9cadb497d7..7c32bd06ed33 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index e0a940fd6e87..18e98c2c07d7 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -42,6 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; };