From patchwork Mon Oct 9 09:29:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 732149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DF9E95A97 for ; Mon, 9 Oct 2023 09:29:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345822AbjJIJ3a (ORCPT ); Mon, 9 Oct 2023 05:29:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345742AbjJIJ33 (ORCPT ); Mon, 9 Oct 2023 05:29:29 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76C3DB6 for ; Mon, 9 Oct 2023 02:29:26 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-50307acd445so5412675e87.0 for ; Mon, 09 Oct 2023 02:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696843764; x=1697448564; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RVwMJP0/SPDt31jQ8TATKalr6/tapoN+GlCQyYbUs7w=; b=XwGm5F9dgEXc49w7srF/PZco05xQuO5fX6e+RAw/U7QcnLHiu74NkJQVJb1yiKIyD0 MAtIekFx+BPjBUAs9Usylw2yvu6aCr7Fk/lfVyiEyVhgYGlEv7IXsZp/ocicDyyeatFw 81xIfceyCjwKBMNftZPv67mKWOi6/8k7H14Ud7dSUO1pv5DOVEYcS+WbxCcMNCyGeFDe V5Ev8fgeVNDvwA2/VJ0vaDQ0jGgOBkcfy+34v/kPEucr1wKfuGkA6sph+IuZxgF8y3WW jPh9wtLkh55Ozj0QKPEcelghXGn6IxV5t3R/C6Ez1Z8dMS2tyiZ7IkgN2qSDM6lpoMYO OGfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696843764; x=1697448564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RVwMJP0/SPDt31jQ8TATKalr6/tapoN+GlCQyYbUs7w=; b=FxakVNeUxon6hdEsLPtol1dP5v60hdazcjBG5cT73w7Lwmiygz1Gzt5KzWbxgc1JWi FnZ4mHB9EJzXQBreONcINfb/WFt6pDz9sSGqSl2blF3ntE4b6xSD8CPt33n5l4Xy4IMf qZZz3LFkRLI8gLt0Z51mxVmz4ekHHeme44alQRdEUk+kgfFGrU7KQ3Uhc6hO3t93aj5q KukaNiRwBOsoBQmRFMeMLHOqHwh4eoPKsahES8+smQzdmv9AIaXSjTv1MO92cNoiw5oQ pBKYedD95xahizGpk5GZZBiwhTb+amFsAKxfk+57eIm7dK734BPXtisJzk84KqUyp1qd oVOA== X-Gm-Message-State: AOJu0Yy0prwtn3p+mBsQcAQDqctncEFAuaKbeTuOHtrpG8SBuf8bjsUW ZivBIvCTGmqpEdjReRcOS6UuKjQ/KcKW0fltVWoNvOJH X-Google-Smtp-Source: AGHT+IENgnpVlTSE4EbQuRQOvobKoDdXbS3pi3c/w5mJlgvj+8wCbA82iDef+CFSDsFtGMG4sjqGUw== X-Received: by 2002:a05:6512:39d1:b0:504:30eb:f2ac with SMTP id k17-20020a05651239d100b0050430ebf2acmr15447702lfu.68.1696843764463; Mon, 09 Oct 2023 02:29:24 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id n24-20020a195518000000b004ff9ab6463fsm1377495lfe.87.2023.10.09.02.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 02:29:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 1/3] drm/msm/dpu: split irq_control into irq_enable and _disable Date: Mon, 9 Oct 2023 12:29:20 +0300 Message-Id: <20231009092922.2590891-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> References: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The single helper for both enable and disable cases is too complicated, especially if we start adding more code to these helpers. Split it into irq_enable and irq_disable cases. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ++++++++--- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 63 ++++++++++--------- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 44 +++++++------ .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 29 ++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 62 +++++++++++++----- 6 files changed, 156 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1cf7ff6caff4..46f4abe54cbd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -729,7 +729,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, } } -static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) +static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; int i; @@ -741,14 +741,32 @@ static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) dpu_enc = to_dpu_encoder_virt(drm_enc); - DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); + DPU_DEBUG_ENC(dpu_enc, "\n"); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys->ops.irq_control) - phys->ops.irq_control(phys, enable); + phys->ops.irq_enable(phys); + } +} + +static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + int i; + + if (!drm_enc) { + DPU_ERROR("invalid encoder\n"); + return; } + dpu_enc = to_dpu_encoder_virt(drm_enc); + + DPU_DEBUG_ENC(dpu_enc, "\n"); + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + + phys->ops.irq_disable(phys); + } } static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, @@ -774,11 +792,11 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, pm_runtime_get_sync(&dpu_kms->pdev->dev); /* enable all the irq */ - _dpu_encoder_irq_control(drm_enc, true); + _dpu_encoder_irq_enable(drm_enc); } else { /* disable all the irq */ - _dpu_encoder_irq_control(drm_enc, false); + _dpu_encoder_irq_disable(drm_enc); /* disable DPU core clks */ pm_runtime_put_sync(&dpu_kms->pdev->dev); @@ -839,7 +857,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, } if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) - _dpu_encoder_irq_control(drm_enc, true); + _dpu_encoder_irq_enable(drm_enc); else _dpu_encoder_resource_control_helper(drm_enc, true); @@ -894,7 +912,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { - _dpu_encoder_irq_control(drm_enc, true); + _dpu_encoder_irq_enable(drm_enc); } /* skip if is already OFF or IDLE, resources are off already */ else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || @@ -969,7 +987,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, } if (is_vid_mode) - _dpu_encoder_irq_control(drm_enc, false); + _dpu_encoder_irq_disable(drm_enc); else _dpu_encoder_resource_control_helper(drm_enc, false); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 6f04c3d56e77..f241d7312279 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -84,7 +84,8 @@ struct dpu_encoder_phys; * @handle_post_kickoff: Do any work necessary post-kickoff work * @trigger_start: Process start event on physical encoder * @needs_single_flush: Whether encoder slaves need to be flushed - * @irq_control: Handler to enable/disable all the encoder IRQs + * @irq_enable: Handler to enable all the encoder IRQs + * @irq_disable: Handler to disable all the encoder IRQs * @prepare_idle_pc: phys encoder can update the vsync_enable status * on idle power collapse prepare * @restore: Restore all the encoder configs. @@ -111,7 +112,8 @@ struct dpu_encoder_phys_ops { void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); void (*trigger_start)(struct dpu_encoder_phys *phys_enc); bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); - void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); + void (*irq_enable)(struct dpu_encoder_phys *phys); + void (*irq_disable)(struct dpu_encoder_phys *phys); void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); void (*restore)(struct dpu_encoder_phys *phys); int (*get_line_count)(struct dpu_encoder_phys *phys); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index be185fe69793..6b902d3fcebe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -280,40 +280,42 @@ static int dpu_encoder_phys_cmd_control_vblank_irq( return ret; } -static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, - bool enable) +static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) { - trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - enable, atomic_read(&phys_enc->vblank_refcount)); - - if (enable) { - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_PINGPONG], - dpu_encoder_phys_cmd_pp_tx_done_irq, - phys_enc); + trace_dpu_enc_phys_cmd_irq_enable(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + atomic_read(&phys_enc->vblank_refcount)); + + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_PINGPONG], + dpu_encoder_phys_cmd_pp_tx_done_irq, + phys_enc); + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN], + dpu_encoder_phys_cmd_underrun_irq, + phys_enc); + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); + + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN], - dpu_encoder_phys_cmd_underrun_irq, - phys_enc); - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); + phys_enc->irq[INTR_IDX_CTL_START], + dpu_encoder_phys_cmd_ctl_start_irq, + phys_enc); +} - if (dpu_encoder_phys_cmd_is_master(phys_enc)) - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_CTL_START], - dpu_encoder_phys_cmd_ctl_start_irq, - phys_enc); - } else { - if (dpu_encoder_phys_cmd_is_master(phys_enc)) - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_CTL_START]); +static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) +{ + trace_dpu_enc_phys_cmd_irq_disable(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + atomic_read(&phys_enc->vblank_refcount)); + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN]); - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_PINGPONG]); - } + phys_enc->irq[INTR_IDX_CTL_START]); + + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]); + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]); } static void dpu_encoder_phys_cmd_tearcheck_config( @@ -739,7 +741,8 @@ static void dpu_encoder_phys_cmd_init_ops( ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank; ops->trigger_start = dpu_encoder_phys_cmd_trigger_start; ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush; - ops->irq_control = dpu_encoder_phys_cmd_irq_control; + ops->irq_enable = dpu_encoder_phys_cmd_irq_enable; + ops->irq_disable = dpu_encoder_phys_cmd_irq_disable; ops->restore = dpu_encoder_phys_cmd_enable_helper; ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index a01fda711883..d9dcf3e87bd1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -610,30 +610,33 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( } } -static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, - bool enable) +static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc) { int ret; - trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), - phys_enc->hw_intf->idx - INTF_0, - enable, - atomic_read(&phys_enc->vblank_refcount)); + trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent), + phys_enc->hw_intf->idx - INTF_0, + atomic_read(&phys_enc->vblank_refcount)); - if (enable) { - ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); - if (WARN_ON(ret)) - return; + ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); + if (WARN_ON(ret)) + return; - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN], - dpu_encoder_phys_vid_underrun_irq, - phys_enc); - } else { - dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN]); - } + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN], + dpu_encoder_phys_vid_underrun_irq, + phys_enc); +} + +static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc) +{ + trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent), + phys_enc->hw_intf->idx - INTF_0, + atomic_read(&phys_enc->vblank_refcount)); + + dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN]); } static int dpu_encoder_phys_vid_get_line_count( @@ -686,7 +689,8 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank; - ops->irq_control = dpu_encoder_phys_vid_irq_control; + ops->irq_enable = dpu_encoder_phys_vid_irq_enable; + ops->irq_disable = dpu_encoder_phys_vid_irq_disable; ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 870a1f5060e3..9b0f73955d9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -376,21 +376,31 @@ static void dpu_encoder_phys_wb_done_irq(void *arg) } /** - * dpu_encoder_phys_wb_irq_ctrl - irq control of WB + * dpu_encoder_phys_wb_irq_enable - irq control of WB * @phys: Pointer to physical encoder - * @enable: indicates enable or disable interrupts */ -static void dpu_encoder_phys_wb_irq_ctrl( - struct dpu_encoder_phys *phys, bool enable) +static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys) { struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); - if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1) + if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1) dpu_core_irq_register_callback(phys->dpu_kms, - phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys); - else if (!enable && - atomic_dec_return(&wb_enc->wbirq_refcount) == 0) + phys->irq[INTR_IDX_WB_DONE], + dpu_encoder_phys_wb_done_irq, + phys); +} + +/** + * dpu_encoder_phys_wb_irq_disable - irq control of WB + * @phys: Pointer to physical encoder + */ +static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys) +{ + + struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); + + if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0) dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); } @@ -665,7 +675,8 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) ops->trigger_start = dpu_encoder_helper_trigger_start; ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job; ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job; - ops->irq_control = dpu_encoder_phys_wb_irq_ctrl; + ops->irq_enable = dpu_encoder_phys_wb_irq_enable; + ops->irq_disable = dpu_encoder_phys_wb_irq_disable; ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 35d03b121a0b..95ce7647ff76 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -514,24 +514,41 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, __entry->expected_time, __entry->atomic_cnt) ); -TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, - TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, +TRACE_EVENT(dpu_enc_phys_cmd_irq_enable, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int refcnt), - TP_ARGS(drm_id, pp, enable, refcnt), + TP_ARGS(drm_id, pp, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_pingpong, pp ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->pp = pp; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, + __entry->pp, + __entry->refcnt) +); + +TRACE_EVENT(dpu_enc_phys_cmd_irq_disable, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, + int refcnt), + TP_ARGS(drm_id, pp, refcnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_pingpong, pp ) - __field( bool, enable ) __field( int, refcnt ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->pp = pp; - __entry->enable = enable; __entry->refcnt = refcnt; ), - TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, - __entry->pp, __entry->enable ? "true" : "false", + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, + __entry->pp, __entry->refcnt) ); @@ -592,24 +609,41 @@ TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) ); -TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, - TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, +TRACE_EVENT(dpu_enc_phys_vid_irq_enable, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, int refcnt), - TP_ARGS(drm_id, intf_idx, enable, refcnt), + TP_ARGS(drm_id, intf_idx, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_intf, intf_idx ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->intf_idx = intf_idx; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, + __entry->intf_idx, + __entry->drm_id) +); + +TRACE_EVENT(dpu_enc_phys_vid_irq_disable, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, + int refcnt), + TP_ARGS(drm_id, intf_idx, refcnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intf, intf_idx ) - __field( bool, enable ) __field( int, refcnt ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->intf_idx = intf_idx; - __entry->enable = enable; __entry->refcnt = refcnt; ), - TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, - __entry->intf_idx, __entry->enable ? "true" : "false", + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, + __entry->intf_idx, __entry->drm_id) ); From patchwork Mon Oct 9 09:29:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 731091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07AE6E95A96 for ; Mon, 9 Oct 2023 09:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345697AbjJIJ3b (ORCPT ); Mon, 9 Oct 2023 05:29:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345801AbjJIJ3a (ORCPT ); Mon, 9 Oct 2023 05:29:30 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C7AD8E for ; Mon, 9 Oct 2023 02:29:27 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-50337b43ee6so5485558e87.3 for ; Mon, 09 Oct 2023 02:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696843765; x=1697448565; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Ft8rzeFfb+3Zy/RVc4524NJ3uIXFMLtpNTcOuyG46Y=; b=OLcEy191EMEOn1Fqk0MM8+EM9iyACquFPQgmMST8GhyQsC5C497R7FgkktPOGBinHU LEiEWTwIiw12ns7yhrRmRA69UqAipilW81ekJEl/MxTZT/73bw5VwHW7qKQJfca+L1gT rc9bvFIaqHaiMiZdQlg3muflFsHHWpatGaiv096ao63Jwd9vaOjrepjXitK+jqX2Kw5h i3iC/7nFSD1ZH/C+M4GeGDXdqL/B32z1/f/dompFmyF8ngjE5oLljn9BiSuPYV6cbi9e RP9QbVmj1HTnYSOtzDMtmyiU63kdwHZYAXN659HtrNWatfVfi5RbRUL8sIs13oxndNig 8HLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696843765; x=1697448565; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Ft8rzeFfb+3Zy/RVc4524NJ3uIXFMLtpNTcOuyG46Y=; b=Lk28FbQhOMQvFJfyZpAGfPEQzGZN9DXA9NrI18v5xZB9BNT7vHrIui5okbo8TGZHOG H99K4PYqmc+JDJpXmH80AH83WnKfeb7srXRCsCj6cjCT1A8m0JGqL4TZV1y84dNcenJz CHgrUH7oCBSNx0BF8BVxq9zIPZCpZcpT6rZM0rDbBBkK0LnIT2eLBxn/iHzcbSVw1KPf wdci6gvCuT+uAGpelSsIjqGx5xIxtJkVK4yZO0YO/KmAuxobL4j7+EkOROmT1BbyDhYt 9b/hluvz35SiSeskolsXZjnARg0Wd0IobDn7Np5n/3z1jFK0emJxWWzwQMNctJwOcQX1 4VuA== X-Gm-Message-State: AOJu0YyYlsHPMxuKNfG4KSk/WqqpExz3cJne/3kJqRm3sZVQEEJghLn7 WenpiheANVD6OcShPGAWlcEyMZ2h99SGgViAER3NlWPD X-Google-Smtp-Source: AGHT+IE7WPTOf1bnyWz4aVrT9CULFFmLQuJdpxXr+CL8+LIIBWtl4V7TvzdA9XT+E7C5rdUqCL/DRQ== X-Received: by 2002:a05:6512:308a:b0:502:e651:129b with SMTP id z10-20020a056512308a00b00502e651129bmr14703016lfd.19.1696843765485; Mon, 09 Oct 2023 02:29:25 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id n24-20020a195518000000b004ff9ab6463fsm1377495lfe.87.2023.10.09.02.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 02:29:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 2/3] drm/msm/dpu: split _dpu_encoder_resource_control_helper() Date: Mon, 9 Oct 2023 12:29:21 +0300 Message-Id: <20231009092922.2590891-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> References: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Follow the _dpu_encoder_irq_control() change and split the _dpu_encoder_resource_control_helper() into enable and disable parts. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +++++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 12 ++++-- 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 46f4abe54cbd..30c457541645 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -769,8 +769,7 @@ static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) } } -static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, - bool enable) +static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc) { struct msm_drm_private *priv; struct dpu_kms *dpu_kms; @@ -780,28 +779,42 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); - trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); + trace_dpu_enc_rc_enable(DRMID(drm_enc)); if (!dpu_enc->cur_master) { DPU_ERROR("encoder master not set\n"); return; } - if (enable) { - /* enable DPU core clks */ - pm_runtime_get_sync(&dpu_kms->pdev->dev); + /* enable DPU core clks */ + pm_runtime_get_sync(&dpu_kms->pdev->dev); - /* enable all the irq */ - _dpu_encoder_irq_enable(drm_enc); + /* enable all the irq */ + _dpu_encoder_irq_enable(drm_enc); +} - } else { - /* disable all the irq */ - _dpu_encoder_irq_disable(drm_enc); +static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc) +{ + struct msm_drm_private *priv; + struct dpu_kms *dpu_kms; + struct dpu_encoder_virt *dpu_enc; - /* disable DPU core clks */ - pm_runtime_put_sync(&dpu_kms->pdev->dev); + dpu_enc = to_dpu_encoder_virt(drm_enc); + priv = drm_enc->dev->dev_private; + dpu_kms = to_dpu_kms(priv->kms); + + trace_dpu_enc_rc_disable(DRMID(drm_enc)); + + if (!dpu_enc->cur_master) { + DPU_ERROR("encoder master not set\n"); + return; } + /* disable all the irq */ + _dpu_encoder_irq_disable(drm_enc); + + /* disable DPU core clks */ + pm_runtime_put_sync(&dpu_kms->pdev->dev); } static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, @@ -859,7 +872,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) _dpu_encoder_irq_enable(drm_enc); else - _dpu_encoder_resource_control_helper(drm_enc, true); + _dpu_encoder_resource_enable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; @@ -954,7 +967,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, * and in IDLE state the resources are already disabled */ if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) - _dpu_encoder_resource_control_helper(drm_enc, false); + _dpu_encoder_resource_disable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; @@ -989,7 +1002,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, if (is_vid_mode) _dpu_encoder_irq_disable(drm_enc); else - _dpu_encoder_resource_control_helper(drm_enc, false); + _dpu_encoder_resource_disable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 95ce7647ff76..bd92fb2979aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -273,6 +273,14 @@ DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, TP_PROTO(uint32_t drm_id), TP_ARGS(drm_id) ); +DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_enable, + TP_PROTO(uint32_t drm_id), + TP_ARGS(drm_id) +); +DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_disable, + TP_PROTO(uint32_t drm_id), + TP_ARGS(drm_id) +); TRACE_EVENT(dpu_enc_enable, TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), @@ -342,10 +350,6 @@ DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, TP_printk("id=%u, enable=%s", __entry->drm_id, __entry->enable ? "true" : "false") ); -DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper, - TP_PROTO(uint32_t drm_id, bool enable), - TP_ARGS(drm_id, enable) -); DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, TP_PROTO(uint32_t drm_id, bool enable), TP_ARGS(drm_id, enable) From patchwork Mon Oct 9 09:29:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 732148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 413CFE95A8E for ; Mon, 9 Oct 2023 09:29:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345686AbjJIJ3c (ORCPT ); Mon, 9 Oct 2023 05:29:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345804AbjJIJ3a (ORCPT ); Mon, 9 Oct 2023 05:29:30 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F87597 for ; Mon, 9 Oct 2023 02:29:28 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-50307acd445so5412723e87.0 for ; Mon, 09 Oct 2023 02:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696843766; x=1697448566; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D+Mqi5c1Bq5zEgEXT+2RNxnYSta98kdM85CCq97LjCY=; b=NIa6sXimfAYtqNs3xuNUNTx4khkucKg4AR1hMoUo5PRR1YfQgrhHtRMoH8ov5oX3/4 iy7n6Yh+cJQw/ANlrVvmyuTvg8AWKDM2zkWDVZ5gsLCtWlLIefwHBflKQcY/TWQo1IYv JD8GiF9pYMkqAcSmLQyYYM3spjFpUNsOZc8rE66XVtMabxP6h/OB9QOBKQmtikaJgwZv mLxlvz5YbGvT2ftJG2V7zXD6K5uFryLDsvU0ZnrAcXAOL7M24e5cxXv3EOkbHGFKTYOP S0Acrn3Zk4BdnDatbjVJsjeopYg7/fXNuqkzDTl7XyPMeduj9TnKdLTU2+pIcVexGKJN PSFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696843766; x=1697448566; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D+Mqi5c1Bq5zEgEXT+2RNxnYSta98kdM85CCq97LjCY=; b=Ubnf4qiSTw3S5K15IHMzIoDFGHfdabEesrk4yEOD+DRJE7kAuxCyXHupG2mIVDESiX W07nFx/A0cqCLxqEZXpoDKhBItoasghjaZ/mv6xuYqDy7eP7WucwcOrBjUtbx19/6e4d +c7odTD1hogmd9WT7thxGz+2Mxc6UUPCxXK8mUZdj4XVomtlU/0z4OzrNxO80ZGEWGgt EKEzVfnsse8MbS0piWJcoLu0Mmkz2oFrAdh01a2iMGFxXa2ZQdSg1VwF+O/9uT8QS6Ac R/QthPa4rB3njLrCy41ZRWkCrvzwBUEKYnyZZIaCBYjR6yZnbFD9Xvom8/ZgQQ9ydet7 i8zA== X-Gm-Message-State: AOJu0Yxvs1Ac3RAetoMIuEQuDwCRxCIHTonl9isda/LSZFihZnOC2Ovn 3e7lsKNVAbOYRffvYKW+8ZaoHQ== X-Google-Smtp-Source: AGHT+IGjqHc0m60QQgu6hLj2HGT74p5zL6ya1rpdmNQN6x0kGgxWTzSnMtHMe9KEyQbBjP2E1DW27w== X-Received: by 2002:a05:6512:4026:b0:500:94c5:6e06 with SMTP id br38-20020a056512402600b0050094c56e06mr16091853lfb.56.1696843766326; Mon, 09 Oct 2023 02:29:26 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id n24-20020a195518000000b004ff9ab6463fsm1377495lfe.87.2023.10.09.02.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 02:29:25 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 3/3] drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set Date: Mon, 9 Oct 2023 12:29:22 +0300 Message-Id: <20231009092922.2590891-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> References: <20231009092922.2590891-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the INTF and WB are statically allocated to each encoder/phys_enc, drop the atomic_mode_set callback and set the IRQs during encoder init. For the CMD panel usecase some of IRQ indexes depend on the selected resources. Move setting them to the irq_enable() callback. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 --- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32 ++++++++----------- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 ++------ .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 11 +------ 5 files changed, 17 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 30c457541645..0551851fdfed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1158,8 +1158,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); phys->cached_mode = crtc_state->adjusted_mode; - if (phys->ops.atomic_mode_set) - phys->ops.atomic_mode_set(phys, crtc_state, conn_state); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index f241d7312279..eb811cbc420d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -67,8 +67,6 @@ struct dpu_encoder_phys; * @is_master: Whether this phys_enc is the current master * encoder. Can be switched at enable time. Based * on split_role and current mode (CMD/VID). - * @atomic_mode_set: DRM Call. Set a DRM mode. - * This likely caches the mode, for use at enable. * @enable: DRM Call. Enable a DRM mode. * @disable: DRM Call. Disable mode. * @atomic_check: DRM Call. Atomic check new DRM state. @@ -95,9 +93,6 @@ struct dpu_encoder_phys; struct dpu_encoder_phys_ops { void (*prepare_commit)(struct dpu_encoder_phys *encoder); bool (*is_master)(struct dpu_encoder_phys *encoder); - void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); void (*enable)(struct dpu_encoder_phys *encoder); void (*disable)(struct dpu_encoder_phys *encoder); int (*atomic_check)(struct dpu_encoder_phys *encoder, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 6b902d3fcebe..8c203da5c653 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -140,23 +140,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg) dpu_encoder_underrun_callback(phys_enc->parent, phys_enc); } -static void dpu_encoder_phys_cmd_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; - - phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; - - if (phys_enc->has_intf_te) - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; - else - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( struct dpu_encoder_phys *phys_enc) { @@ -286,6 +269,14 @@ static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(&phys_enc->vblank_refcount)); + phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; + phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; + + if (phys_enc->has_intf_te) + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; + else + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; + dpu_core_irq_register_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG], dpu_encoder_phys_cmd_pp_tx_done_irq, @@ -316,6 +307,10 @@ static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]); dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]); + + phys_enc->irq[INTR_IDX_CTL_START] = 0; + phys_enc->irq[INTR_IDX_PINGPONG] = 0; + phys_enc->irq[INTR_IDX_RDPTR] = 0; } static void dpu_encoder_phys_cmd_tearcheck_config( @@ -730,7 +725,6 @@ static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_cmd_is_master; - ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->destroy = dpu_encoder_phys_cmd_destroy; @@ -768,6 +762,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_CMD; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; + cmd_enc->stream_sel = 0; if (!phys_enc->hw_intf) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index d9dcf3e87bd1..29ea0c9fcd55 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -347,16 +347,6 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void dpu_encoder_phys_vid_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int dpu_encoder_phys_vid_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) @@ -681,7 +671,6 @@ static int dpu_encoder_phys_vid_get_frame_count( static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; - ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->destroy = dpu_encoder_phys_vid_destroy; @@ -720,6 +709,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( dpu_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_VIDEO; + phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 9b0f73955d9f..d7ef36a2d315 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -404,15 +404,6 @@ static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys) dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); } -static void dpu_encoder_phys_wb_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - - phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; -} - static void _dpu_encoder_phys_wb_handle_wbdone_timeout( struct dpu_encoder_phys *phys_enc) { @@ -663,7 +654,6 @@ static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phy static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_wb_is_master; - ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; ops->enable = dpu_encoder_phys_wb_enable; ops->disable = dpu_encoder_phys_wb_disable; ops->destroy = dpu_encoder_phys_wb_destroy; @@ -710,6 +700,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init( dpu_encoder_phys_wb_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_WB_LINE; + phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; atomic_set(&wb_enc->wbirq_refcount, 0);