From patchwork Tue Oct 10 13:26:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 731558 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 397008F5D for ; Tue, 10 Oct 2023 13:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="RjmFxK0k" Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15A2FC4 for ; Tue, 10 Oct 2023 06:27:13 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9ae2cc4d17eso1015828266b.1 for ; Tue, 10 Oct 2023 06:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1696944431; x=1697549231; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Iig9ag63aVzgMKeY4TwjyQYW3SBdv2Ym+GOOusSElI8=; b=RjmFxK0khafMxqzsB4Od0FtHja4eGFDM6JsRgpnvl3TEMkm9CYaCd6klRgAK0F0z0O KcBsgWVuvi3dsu+VLecVUhQmioVnToYNx+WwnVOYginzbKByZlu4uAOZimeNitYYy60k QVATuuZKuySqjYqruwS+KjsjxH1SMnrvv3bIL1uQMPPV8Ho/3tci5S1uVU2gLIHn2uQL G49Qv9qbLjK9b9SRSu+VMFb6vsWOevBnoJzDZkDcWs4apduC1vP/pHNSGpB/v3ZsmPdG 5YmrQTOZsEXz05sJ8Tv4X4+sl7kO5SQbKd0i+Q/tHcC5RrjPpP3G8JleUXc5SPqn5R1d BAzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696944431; x=1697549231; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Iig9ag63aVzgMKeY4TwjyQYW3SBdv2Ym+GOOusSElI8=; b=lsz/s925w6YRYj7BqLa/3NJZbCHRKrUomVEMpVLC1mN0mF8EH+n1WaMKITukUE8piC Za1VmeqG1sGpoxc2U76icTuC8oAe5ItuHEBIIR+FXIn9V7qfNdP3CnWfT9vX0HAFbxa8 b16qJMk/2jVpZDT/tQO8bASgguLU84Gux+ajqgQLoMwfcLEUNla+72/i647KZIjDHObg meOXrWUrE4darO+bsfK208zGVWs2pA8f/h6s7uGHfrrlb4DT29DH+PWsxjog02opF7+c VRgcGwzkK+qhZva3x1/6+w5dUyF7FQXkxNl0kaqX4W/YdeZqTF0IJWasaK8bQRknD3I4 NNug== X-Gm-Message-State: AOJu0YywMaoz3j1iVNY6S5v/7A+6VyBeI1G7p6KtXtMfBJUTXzG5j7vJ DjOa0RYRJflL1x78bNy/YbcTAg== X-Google-Smtp-Source: AGHT+IH/4VgcQTIb7nq7GquauPcHOWu6jQZTwpKEVREMKXrZskqhEh3KwuV8ijbjiN+arTCLWWjT0Q== X-Received: by 2002:a17:906:8a59:b0:9b2:e26f:3636 with SMTP id gx25-20020a1709068a5900b009b2e26f3636mr15771125ejc.13.1696944430759; Tue, 10 Oct 2023 06:27:10 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 1/6] clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() Date: Tue, 10 Oct 2023 16:26:56 +0300 Message-Id: <20231010132701.1658737-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Use %x format specifier to print CLK_ON_R(). This is easier when debugging as the value printed will be hexadecimal like in the hardware manual. Along with it "0x" has been added in front of the printed value. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index d62f1bc1f60e..764bd72cf059 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1213,7 +1213,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) return 0; } - dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, + dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk, enable ? "ON" : "OFF"); value = bitmask << 16; From patchwork Tue Oct 10 13:26:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 732890 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CE7E4737C for ; Tue, 10 Oct 2023 13:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="PWpyvZE/" Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4CD8C6 for ; Tue, 10 Oct 2023 06:27:13 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9a58dbd5daeso1011683166b.2 for ; Tue, 10 Oct 2023 06:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1696944432; x=1697549232; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Myh0EUpEAAbOhx8NqaptdLIeko5fmhcaUFegO6OZMwQ=; b=PWpyvZE/U8dQZWe9j+BnwokxPRQ5YLlqlvWzkOJVpTQHawG//mOrWg5WK7keye2vJ/ 3RjDUgzfHzjS9j+nYUKglTe7MAv6/lfNzrIZ5URIZVxiCcyl2sSkMSCvMP3XCjNjwYrJ 8dB2YGEpcFHCl0QkjbysXJ1tZWQIgkPGSFggkFUfei2PpgF0scryHla/NO4QWupMtPZI TATUHTVE9aTzVlFduE+SwrIAKVyIZ8dyXDzthGYnsrmZxUzZp4VBqITwvIzeFoQ+8/CR LbuuR4FBLlZjbqxpXza+qQkc/Bk51kpMLa3u+UrRhhiTSWh//Ul+yk/ExyElnmm3ypp/ YEgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696944432; x=1697549232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Myh0EUpEAAbOhx8NqaptdLIeko5fmhcaUFegO6OZMwQ=; b=Ah4Y01FZNzEdpzeAhMfWkgZ4SfGCM3/PJcPQ1QIZe3FLHfCluZADT6SLyWOPusfGlS 9slCI0MTiLWk5rR4NK+zQfHtuRbfHZxzswYFMT0iQt9kRXmFfqjwCsjx1npkeL6vNqOr Qh5rJxqmcnjEX8ZH8GtBzZvwaimWXte4X/uiiVhBbp2APIYVzL+i4y1pcbeXAo08IUGT HCRCCbyfdQHIl+K3YctHIJsUfcU6eaU80QaKBSdeU1q8pWnbtCHfEA/l0lFa2ogZPQVI CGRUNUjHM2u3UqyFhDjzCz9ZLy95o2m4ZWl7ZSsrg7jmXGBDynQXjN9tMjZ7mNWQRPDO uJ1w== X-Gm-Message-State: AOJu0YxChIJbbhNlC2UCNG+8NiV2AC32yTxgsgPsuCsuiaRYed1GhhBQ tRGrQPLRnwdtkg+hqUOWnpIsj+m6ApRXzBjv0LQ= X-Google-Smtp-Source: AGHT+IGBAr8Ny8/cCqvE4oomDYeBihBAoMzReOlbcfotM+sSSqBHLNRiziqJw2nt7fa9wMLg9EKwtQ== X-Received: by 2002:a17:906:30db:b0:9ae:41db:c27f with SMTP id b27-20020a17090630db00b009ae41dbc27fmr17459264ejb.10.1696944432144; Tue, 10 Oct 2023 06:27:12 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 2/6] clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 Date: Tue, 10 Oct 2023 16:26:57 +0300 Message-Id: <20231010132701.1658737-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Add clock and reset support for SDHI1 and SDHI2 blocks on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 389d32b32168..4394cb241d99 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -25,6 +25,8 @@ /* RZ/G3S Specific division configuration. */ #define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) #define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) +#define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1) +#define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1) /* RZ/G3S Clock status configuration. */ #define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) @@ -33,13 +35,19 @@ #define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) #define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) #define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) +#define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1) +#define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1) #define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) #define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) +#define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1) +#define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1) /* RZ/G3S Specific clocks select. */ #define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) #define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) +#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2) +#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2) /* PLL 1/4/6 configuration registers macro. */ #define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) @@ -74,10 +82,14 @@ enum clk_ids { CLK_PLL6, CLK_PLL6_DIV2, CLK_SEL_SDHI0, + CLK_SEL_SDHI1, + CLK_SEL_SDHI2, CLK_SEL_PLL4, CLK_P1_DIV2, CLK_P3_DIV2, CLK_SD0_DIV4, + CLK_SD1_DIV4, + CLK_SD2_DIV4, /* Module Clocks */ MOD_CLK_BASE, @@ -136,6 +148,10 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sd1", CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi, + mtable_sd, 0, NULL), + DEF_SD_MUX(".sel_sd2", CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi, + mtable_sd, 0, NULL), DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, mtable_pll4, CLK_SET_PARENT_GATE, NULL), @@ -147,7 +163,15 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD1", R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS, + dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), + DEF_G3S_DIV("SD2", R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS, + dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, + rzg3s_cpg_div_clk_notifier), DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), + DEF_FIXED(".sd1_div4", CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4), + DEF_FIXED(".sd2_div4", CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4), DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, dtable_1_32, 0, 0, 0, NULL), @@ -170,6 +194,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7), + DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8), + DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), + DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), + DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -178,6 +210,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), + DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), + DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), From patchwork Tue Oct 10 13:26:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 731557 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 043A64737A for ; Tue, 10 Oct 2023 13:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="JfHkcD89" Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F574A9 for ; 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([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 3/6] arm64: dts: renesas: r9a08g045: Add nodes for SDHI1 and SDHI2 Date: Tue, 10 Oct 2023 16:26:58 +0300 Message-Id: <20231010132701.1658737-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Add DT nodes for SDHI1 and SDHI2 available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 7971e44a5a0a..534b728a8e14 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -118,6 +118,36 @@ sdhi0: mmc@11c00000 { status = "disabled"; }; + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@11c20000 { + compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c20000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A08G045_SDHI2_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Tue Oct 10 13:26:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 732889 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A35354737A for ; Tue, 10 Oct 2023 13:27:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="G0/rVqXx" Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91D1ECA for ; Tue, 10 Oct 2023 06:27:16 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9adb9fa7200so1234263766b.0 for ; Tue, 10 Oct 2023 06:27:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1696944435; x=1697549235; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZGLi6ZZ7hP8CWSEWm0V3dbJhp2/y5MlpYoiVN1v/31o=; b=G0/rVqXxwIE8cxASApycEOgZax435tWrG5/ASY092Ueb1n5qQqH+93FL7NFgNUEBfb zEfH6Ta6tEm45H/YYkPD97Ux/aARZh/DVG7G3Dzpe9dJVRpz4rNjpiMokPwDtU6Fk7n3 gZC4FbmzySXZHuOJTu0Vp3JyzLenZXTLEZQcXLcM7r3aTHiE9OYjTjT/OZaW5J/8jn+n IZYhcxnW7YOem8I14ReHKLq8gpPKAs/FHayUFTJdYE/CKYnzcqLU9lOJEvZH+khWN55+ WZ/ChejtBLEohDc9DSf/tNE/fpxOCscYsBEP81lvvszYxYXN+lz6L1PuUp5DAwdudkcT Qdkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696944435; x=1697549235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZGLi6ZZ7hP8CWSEWm0V3dbJhp2/y5MlpYoiVN1v/31o=; b=PSPn5PSEOGJxNaHJupOk8Wjm+mujpkCBQeWWcWLqfutKRg8tR1zYfiQUplDSIrrxvH cu7NSiQ8pqpeEBfCRBgeZ5hx8THv8Kfyq7kARJrKNl+EkuGEOmVSa0EwA06/9u3qfvjy bToCzNZZc6uB1uHisssxSf7f+k/pXyGji31cCxToP5auNcUn9CSqhF1rCNZG4wQSjGZz VP2gI7aAV2BjHhy9y+zxu+6vODjR0sT6e53hG6EauxfdaPsE+3EAJmlxbOv/TlwyUD+5 dZtjWhwyP+K5vv32QdwtOJwy2wBBPzTeJfh3XSykuZYZrwCOgiNCum8BH8kUNiSDAWUI f1vQ== X-Gm-Message-State: AOJu0Yy7bqAB7aEcXy2he5hAt+wWb0uLqY5MiU/FNNkrX8glXHYHMW7k +wd9caRwn7rv55bstwq6QH8Nkw== X-Google-Smtp-Source: AGHT+IFr74XPhv9uN8f/L3p77Agl9GMFi4mm0SUDWnrX4Ed7pMAHJnq65qYO02jiiFCU37DK+rwKYg== X-Received: by 2002:a17:907:9491:b0:9a5:962c:cb6c with SMTP id dm17-20020a170907949100b009a5962ccb6cmr14152972ejc.31.1696944435109; Tue, 10 Oct 2023 06:27:15 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Date: Tue, 10 Oct 2023 16:26:59 +0300 Message-Id: <20231010132701.1658737-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3, IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch button. To be able to select b/w these a compilation flag has been added (SW_SD2_EN) at the moment being instantiated to select SDHI2. Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 185ca8289a35..58a68356b9d7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -13,14 +13,21 @@ * @SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC * 1 - SD0 is connected to uSD0 card + * @SW_SD2_EN: + * 0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC + * 1 - SD2 is connected to SoC */ #define SW_SD0_DEV_SEL 1 +#define SW_SD2_EN 1 / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; +#if SW_SD2_EN + mmc2 = &sdhi2; +#endif }; chosen { @@ -63,6 +70,24 @@ reg_1p8v: regulator1 { regulator-always-on; }; #endif + + vcc_sdhi2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_3p3v: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -100,6 +125,19 @@ &sdhi0 { }; #endif +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <®_3p3v>; + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; +#endif + &pinctrl { sdhi0_pins: sd0 { data { @@ -139,4 +177,26 @@ sdhi0_emmc_pins: sd0-emmc { "SD0_CLK", "SD0_CMD", "SD0_RST#"; power-source = <1800>; }; + + sdhi2_pins: sd2 { + data { + pins = "P11_2", "P11_3", "P12_0", "P12_1"; + input-enable; + }; + + ctrl { + pins = "P11_1"; + input-enable; + }; + + mux { + pinmux = , /* SD2_CLK */ + , /* SD2_CMD */ + , /* SD2_DATA0 */ + , /* SD2_DATA1 */ + , /* SD2_DATA2 */ + , /* SD2_DATA3 */ + ; /* SD2_CD# */ + }; + }; }; From patchwork Tue Oct 10 13:27:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 731556 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CDED4737E for ; Tue, 10 Oct 2023 13:27:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="gTFrILYK" Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 233CAC4 for ; Tue, 10 Oct 2023 06:27:18 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9b9a494cc59so948224866b.3 for ; Tue, 10 Oct 2023 06:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1696944436; x=1697549236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PTS0RsVqbjVNm/cAfof2qqXtb+VFg82/jG1YYiHr1T0=; b=gTFrILYKCcsIPK70wq4c8lJ5V0lvOwEru3v2+NBy/JLbnyO4AzZldFA0hixyyVlmHf Lg08TQXDD0Ftm2xVUiJ0rmUIqwRwc+vEArhuXqS3q+sDZBsIjJlrM4+h0Ynrnp0zIVWH QfDivPEcWc527hekFRsLjijnrHcHhCd2JZTULwLxo7ZklxGj8pC0XYZD5G4fwUQM2oV/ 18gNUm+TtUmXv/g7QhsJijTByBnhv/s0nxIo5eDOh2nILS1mdUBFOumetQogH9EU+iK+ 28NkN5nJ0jmQ1BikgAsVNSkSXvGiKw9O/LZ7iLQUy9uuusGuUul7Z02Clneu545aIxnt 48oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696944436; x=1697549236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PTS0RsVqbjVNm/cAfof2qqXtb+VFg82/jG1YYiHr1T0=; b=BTgdJOey+UME20osdLuwhwC1snVqI5Gk2DjELhz8Eq66ZTqjUu9g2fPHS33tuy8hyO RaVzxErTsGpc6o0nfsi3lRGGHtNrZqLhuaw92LTWWFdQkh32n9azEwAvlanZ2rnuUqD6 tZPP9mR61mCGAIQ+vHqCVVYIWp6cKdXUFiuqt/SZlAIOfDCJo/+VBR5ABnYqzYa8jTfh GqP/krk+FOu98GHxTTTUgJDkSGdJH7/ucli+kAYmGe2Bgsm9xoy/ISUx+3LZnfuhGPYX YItgOT7STwW4fruh+46ouPn5z7r06ac8aSNFEn5d7fc6aV1GZ6JKjz1IfR6327uZDCkv XzCw== X-Gm-Message-State: AOJu0YwlfaVjbdlou1byWnOX7zhEC0b7S/OL8UTWaqIl76wwm1ode1Js 1rsxIxyoiqbzKBXRtEkGBj/RgQ== X-Google-Smtp-Source: AGHT+IFqR5Nd0aHbkI7c4o1xnDoLgLUB07HdkarXNaM7IrjdRUuK3ik3XgXtC93V3/O2ewGZcptABA== X-Received: by 2002:a17:907:6c14:b0:9ae:5c99:f2e2 with SMTP id rl20-20020a1709076c1400b009ae5c99f2e2mr14341810ejc.43.1696944436632; Tue, 10 Oct 2023 06:27:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 5/6] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Date: Tue, 10 Oct 2023 16:27:00 +0300 Message-Id: <20231010132701.1658737-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Add SDHI1 to RZ/G3S Smarc Carrier-II board. This is connected to a uSD interface. Although Vccq doesn't cross the boundary of SoM it has been added to RZ/G3S Smarc Carrier-II dtsi to have all the bits related to SDHI1 in a single place. At the moment SoM is used only with RZ/G3S Smarc Carrier-II board. Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 66 ++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index e7073a09ed2e..71c0cbee6258 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,27 @@ / { aliases { serial0 = &scif0; + mmc1 = &sdhi1; + }; + + /* Reserved regulators 0-9 for SoM. */ + vcc_sdhi1: regulator10 { + compatible = "regulator-fixed"; + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator11 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; }; }; @@ -19,6 +40,38 @@ scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ }; + + sdhi1_pins: sd1 { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1-uhs { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; }; &scif0 { @@ -26,3 +79,16 @@ &scif0 { pinctrl-0 = <&scif0_pins>; status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +}; From patchwork Tue Oct 10 13:27:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 732888 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B66B39CA5A for ; Tue, 10 Oct 2023 13:27:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="fV3bkSN7" Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A896DD7 for ; Tue, 10 Oct 2023 06:27:19 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-9a6190af24aso983668766b.0 for ; Tue, 10 Oct 2023 06:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1696944438; x=1697549238; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qkrku1fg1ZERvoA0RMDfwo6BvhBgxWwyN5hzG0/9pUM=; b=fV3bkSN7GnViWSjZw6dO38V6viMaqIIltan5Z0CyuVt43mbdKhwmIDkuUqdRj0SkgG NFgxS51eSQKb2XD6UkzniRdZTR40VIDw1VTwqxIg7n1LIYgL0VyRlCVDktpTopw5MRvI 7nFxtJzizTjwGh32jXUSC5KbIpOOWJLZRdzfBh4F+5S4ZjDlAqzzsmQfF1UcgPRnrZWH el9v7Ya/oh14zQwLZlApBQXnkWzQ7H77fsGCpXeHhhdH8rgBlWm/1cgOd1u6QYQgGXf+ xHgIdsIZ/0iwGyVaS+yxTGSmd+pwVuQ7fqoUdtRV+kP6yWwd5PxRLteDPTQoq0FUZfVO E7Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696944438; x=1697549238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qkrku1fg1ZERvoA0RMDfwo6BvhBgxWwyN5hzG0/9pUM=; b=fy98jRgpzW9OcQ4RqR3tsCB3ofuaAiWW3HcNGlzVjTRk9cBM62KjrYejEIUONSYvZR golsMLk5y3IitK9W85KiuNIx45TkTwBuKuCWbQHdin5hZYm9K13u4Hsgs35mDkK1fbv7 vQCgRgKX3RAdR+wf/0/GpLNOPMu5RzdxjbDANIZKfZtWSpC6gQNlr+tFpFItIqXKfGSn yL5CeA5kuc5B0/e3T8qLnV3T2pxdrCxAzn5iwzbNbkBY+1U0D/Mxzz/+HHgDGelb3BJ5 J9Q0m0UMCB1lcQNjUroiQj1PdGLpFVQkhdlNR04ZbOB/jkM/YBKhsk8fhRo7b1tixzhC iPdw== X-Gm-Message-State: AOJu0Yz/x8MVHMfxo4SYlMgn6f9EycxGzR4UoSjB8DlEHjewJaXojPWW b/h/h41csPiQiYtBb9QnnSX2Zg== X-Google-Smtp-Source: AGHT+IEl9t6FRqcsOeqelqNqjCpGD0EHxzHxZXfuUwkHHG2ydOEmu/vjceFDSGDNxovT0X7EtnZ44g== X-Received: by 2002:a17:907:2715:b0:9b2:babd:cd44 with SMTP id w21-20020a170907271500b009b2babdcd44mr15731791ejk.44.1696944438037; Tue, 10 Oct 2023 06:27:18 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.152]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm8526578ejv.101.2023.10.10.06.27.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 06:27:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH 6/6] arm64: dts: renesas: rzg3s: Fix dtbs_check Date: Tue, 10 Oct 2023 16:27:01 +0300 Message-Id: <20231010132701.1658737-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> References: <20231010132701.1658737-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net From: Claudiu Beznea Fix the following DTBS check warnings: arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dt: /: memory@48000000: 'device-type' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/memory.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: /: memory@48000000: 'device_type' is a required property from schema $id: http://devicetree.org/schemas/memory.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: 'cache-level' is a required property from schema $id: http://devicetree.org/schemas/cache.yaml# arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dtb: cache-controller-0: Unevaluated properties are not allowed ('cache-size', 'cache-unified' were unexpected) from schema $id: http://devicetree.org/schemas/cache.yaml# Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 534b728a8e14..6c7b29b69d0e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -29,6 +29,7 @@ cpu0: cpu@0 { L3_CA55: cache-controller-0 { compatible = "cache"; + cache-level = <3>; cache-unified; cache-size = <0x40000>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 58a68356b9d7..fdb8053adde9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -36,7 +36,7 @@ chosen { }; memory@48000000 { - device-type = "memory"; + device_type = "memory"; /* First 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; };