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[209.132.180.131]) by mx.google.com with ESMTPS id f5si1902743plj.246.2019.08.09.08.34.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Aug 2019 08:34:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-506595-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="N/SGnJGB"; spf=pass (google.com: domain of gcc-patches-return-506595-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-506595-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=TJbgDGavwFzxxN02e/263maPCuGhPrJKVEWtFX7p5X+oN0f1FP Z4IWdrnIRBw+jHr4wYrY1y7myKZun51rN0L1yK7l4Fe9r3S/fHY2ZD89DB9KYrp2 hBdwMbAbh3g2m2tsY0FOZfIiWdFkKmxZDoRU+LNGCOcKYCb8Qpjlu9tgI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=PhkLxtnsfUAPZUWjekQS6tgFV8c=; b=N/SGnJGBDZ92LiOQMX5C Ez7xOoIrE85vyYr2liJJkb9sQ33fEH5jjJE8ySXbQdleQCuNoo6ybw29g82S2IpO peUOQPl0ZX1h1cxdL6RkVBJoX8BZKesELLqbq/YmroooL8nDYoOLj6GjsJ37wRas HYKnVdIF69vgrffWrxBRnfQ= Received: (qmail 122430 invoked by alias); 9 Aug 2019 15:34:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122381 invoked by uid 89); 9 Aug 2019 15:34:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Aug 2019 15:34:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E43415A2; Fri, 9 Aug 2019 08:34:40 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.91]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 180B73F575; Fri, 9 Aug 2019 08:34:39 -0700 (PDT) To: gcc-patches@gcc.gnu.org From: "Richard Earnshaw (lists)" Subject: [arm] Recognize thumb2 16-bit variants of the add and compare instructions Message-ID: Date: Fri, 9 Aug 2019 16:34:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 The addsi3_compare_op[12] patterns currently only have constraints to pick the 32-bit variants of the instructions. Although the assembler may sometimes opportunistically match a 16-bit t2 instruction, there's no real control over that within the compiler. Consequently we might emit a 32-bit adds instruction with a 16-bit subs instruction would serve equally well. We do, of course still have to be careful about the small number of boundary cases by controlling the order quite carefully. This patch adds the constraints and templates to match the t2 16-bit variants of these instructions. Now, for example, we can generate subs r0, r0, #1 // 16-bit instruction instead of adds r0, r0, #1 // 32-bit instruction. *config/arm/arm.md (addsi3_compare_op1): Add 16-bit thumb-2 variants. (addsi3_compare_op2): Likewise. Committed to trunk. R. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7ab939a35f5..f2739aa57c6 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -930,35 +930,49 @@ (define_peephole2 (define_insn "*addsi3_compare_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) (match_dup 1))) - (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ + adds%?\\t%0, %1, %2 + adds%?\\t%0, %0, %2 + subs%?\\t%0, %1, #%n2 + subs%?\\t%0, %0, #%n2 adds%?\\t%0, %1, %2 subs%?\\t%0, %1, #%n2 adds%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*,*") + (set_attr "length" "2,2,2,2,4,4,4") + (set_attr "type" + "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*addsi3_compare_op2" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "arm_add_operand" "I,L,r")) + (plus:SI (match_operand:SI 1 "s_register_operand" "l,0,l,0,r,r,r") + (match_operand:SI 2 "arm_add_operand" "lPd,Py,lPx,Pw,I,L,r")) (match_dup 2))) - (set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,l,l,l,r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ + adds%?\\t%0, %1, %2 + adds%?\\t%0, %0, %2 + subs%?\\t%0, %1, #%n2 + subs%?\\t%0, %0, #%n2 adds%?\\t%0, %1, %2 subs%?\\t%0, %1, #%n2 adds%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_sreg")] + (set_attr "arch" "t2,t2,t2,t2,*,*,*") + (set_attr "length" "2,2,2,2,4,4,4") + (set_attr "type" + "alus_sreg,alus_imm,alus_sreg,alus_imm,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*compare_addsi2_op0"