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X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC DEBUG PATCH 1/3] vl: Fix broken thread=xxx option of the --accel parameter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth Commit bde4d9205 ("Fix the -accel parameter and the documentation for 'hax'") introduced a regression by adding a new local accel_opts variable which shadows the variable with the same name that is declared at the beginning of the main() scope. This causes the qemu_tcg_configure() call later to be always called with NULL, so that the thread=xxx option gets ignored. Fix it by removing the local accel_opts variable and use "opts" instead, which is meant for storing temporary QemuOpts values. And while we're at it, also change the exit(1) here to exit(0) since asking for help is not an error. Fixes: bde4d9205ee9def98852ff6054cdef4efd74e1f8 Reported-by: Markus Armbruster Reported-by: Emilio G. Cota Signed-off-by: Thomas Huth --- vl.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) -- 2.13.0 diff --git a/vl.c b/vl.c index be4dcf25ba..5aba544f67 100644 --- a/vl.c +++ b/vl.c @@ -3757,21 +3757,18 @@ int main(int argc, char **argv, char **envp) qdev_prop_register_global(&kvm_pit_lost_tick_policy); break; } - case QEMU_OPTION_accel: { - QemuOpts *accel_opts; - + case QEMU_OPTION_accel: accel_opts = qemu_opts_parse_noisily(qemu_find_opts("accel"), optarg, true); optarg = qemu_opt_get(accel_opts, "accel"); if (!optarg || is_help_option(optarg)) { error_printf("Possible accelerators: kvm, xen, hax, tcg\n"); - exit(1); + exit(0); } - accel_opts = qemu_opts_create(qemu_find_opts("machine"), NULL, - false, &error_abort); - qemu_opt_set(accel_opts, "accel", optarg, &error_abort); + opts = qemu_opts_create(qemu_find_opts("machine"), NULL, + false, &error_abort); + qemu_opt_set(opts, "accel", optarg, &error_abort); break; - } case QEMU_OPTION_usb: olist = qemu_find_opts("machine"); qemu_opts_parse_noisily(olist, "usb=on", false); From patchwork Fri Jun 9 17:00:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 103536 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp301696qgd; Fri, 9 Jun 2017 10:01:17 -0700 (PDT) X-Received: by 10.237.42.15 with SMTP id c15mr41620699qtd.74.1497027677152; Fri, 09 Jun 2017 10:01:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497027677; cv=none; d=google.com; s=arc-20160816; b=IScvsgAZF1yU3ZdMnMRCriu9tIevSToaXdEBBimHFbpool/tvA0H8UhjFUt3NcIcTf CVD8AJzDi6I/k9AVG1mJT9LvcIZoJB+SCQA7r37r2bZM9RtTaFs0YsvtFTrJg21BJr5c /EP/OOnsis50anAUyAeSGlaUPmljTCzhcZ9315mKWwnER7jf+1SPXJDKt5XkSO819Pha x3K6VrtBTbjWch/ijtqlzHoalO8soRoXwAgxp3wem8DBafCq5+TLk4qpFnFZVtX8YpnM wrA0sBkQNv3LMyzayZ2AHFhJIqeuNyxht4JXAAdnUhpltQj5nqHQ9lgXUpCdCi7/jtDU R2ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Xq305igwf68GoY7TpagijCF2pomAUxdWnGhiCPKuLhk=; b=wERAT5Y3NWQHSmnb7zl9T+NcmMNT6vj+kPBG6q+S7n7bD24waUYrslkCfmq8vMldne iXTYedfREM2bxiXqHeXzaMnFrrVmmVeWlmpHbU0sem/yfhCGcUxiPWvxTlAL73fOoRcU x8cBz9r3Mv4FlpgjqXaiIEB3NBfTFliJBly9Hs4gh111a/t1kDlKilbhrpnhZBpc5Upk g3tPHBHVLWqehli5A7EuIjCfXnCtSDqV+VHoJeU+2jgxAS55ZQOhbZI7GRY+fgk+BBXm cq1xQPTU1BGHrX1cEUjmZAYD41CK7JNRYPlitGJnfROVSS1suDqmnDJD0CSYso0sFj/8 34JQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22d Subject: [Qemu-devel] [RFC DEBUG PATCH 2/3] tcg-runtime: light re-factor of lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Just a little precursor re-factoring before I was going to add a trace point: - single return point, defaulting to tcg_ctx.code_gen_epilogue - move cs_base, pc and flags inside the jump cache hit scope - calculate the tb_jmp_cache hash once Signed-off-by: Alex Bennée --- tcg-runtime.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) -- 2.13.0 diff --git a/tcg-runtime.c b/tcg-runtime.c index 7fa90ce508..e987c1f6bb 100644 --- a/tcg-runtime.c +++ b/tcg-runtime.c @@ -147,30 +147,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) { CPUState *cpu = ENV_GET_CPU(env); + unsigned int addr_hash = tb_jmp_cache_hash_func(addr); + void * code_ptr = NULL; TranslationBlock *tb; - target_ulong cs_base, pc; - uint32_t flags; - tb = atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(addr)]); + tb = atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); if (likely(tb)) { + target_ulong cs_base, pc; + uint32_t flags; + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + if (likely(tb->pc == addr && tb->cs_base == cs_base && tb->flags == flags)) { - goto found; - } - tb = tb_htable_lookup(cpu, addr, cs_base, flags); - if (likely(tb)) { - atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(addr)], tb); - goto found; + code_ptr = tb->tc_ptr; + } else { + /* If we didn't find it in the jmp_cache we still might + * find it in the global tb_htable + */ + tb = tb_htable_lookup(cpu, addr, cs_base, flags); + if (likely(tb)) { + atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + code_ptr = tb->tc_ptr; + } } } - return tcg_ctx.code_gen_epilogue; - found: - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, - "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); - return tb->tc_ptr; + + return code_ptr ? code_ptr : tcg_ctx.code_gen_epilogue; } void HELPER(exit_atomic)(CPUArchState *env) From patchwork Fri Jun 9 17:01:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 103539 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp303007qgd; Fri, 9 Jun 2017 10:03:46 -0700 (PDT) X-Received: by 10.55.15.159 with SMTP id 31mr49552589qkp.197.1497027826223; Fri, 09 Jun 2017 10:03:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497027826; cv=none; d=google.com; s=arc-20160816; b=OfdT17KUeh1K90EMRUvumMRlI19PHC002xUjmbUdP/d5m6K5VhtgIqbGtEO9l2q51/ BZy0yE+Tq6rC58hP1amvgy7gL7aIr0Ui3zuvYeT2g8iRmxoc39ux67adcuHhzNxNMWOH QDPH2Ps/0BFVpM5IoiODF9xqP8pRyLUS8i5aZo2MBMOfim++t3mgtzAVHJnJ/9ZuCMaa gb1u38REleZJ6VPCw9AQP0XUX/GO+8vRb3EiJNLvlF4/dyxjtqrnsBo6SBuU2ObuITuY mLBxm/RVNGvxrGxTxCDt0dflAH5zSxz/zYPgGeP7UZqnkLXd+/pgliYDJc2kQfE13u5P 4dmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=igsvQhyPFDht8bq6A7FrVqe0H/G7CAivfmB0xWpKJx8=; b=jXW0zUNLgddxgdu9MA1D1RmlG1adGwVlKPp0W6xNQm+j58PdOM8oLhbZtA9iaTY3Sl RJqIDIkZlffYhQrc/tTUsHCBMjhoMb/1lZIUMwV8kjDWEqZaRNsZP5SaKEkapYnvZ0zB flb72lGG2hrn1Rf2IjM8vB0mzU/4MBWJQ3dOxnF8HY+Y00UxDF4L6FxsSb0jVmYY6zOA nkm9KbxjSehXufJtb9dvvVE8UrZEObztpc/wiBivrq24mPDkguWAKPTI695OdEWyMGk2 GurulCjZgtq7+veUtNUHX623jac+0XY2uWPodogMfDVVjnJ18Vfq2szxs4p5ubxkdldm bSjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::235 Subject: [Qemu-devel] [RFC DEBUG PATCH 3/3] translate-a64: fix lookup_tb_ptr hang (DEBUG!) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org, "open list:ARM" , Peter Crosthwaite Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" THIS IS A DEBUG PATCH DO NOT MERGE I include all the comments to show my working. I was trying to isolate which instructions cause the problem. It turns out it is the RET instruction. I don't understand why because AFAICT it is a pretty much a BR instruction. Signed-off-by: Alex Bennée --- include/exec/exec-all.h | 2 ++ target/arm/translate-a64.c | 21 +++++++++++++++++---- target/arm/translate.h | 2 ++ tcg-runtime.c | 4 +++- 4 files changed, 24 insertions(+), 5 deletions(-) -- 2.13.0 Tested-by: Alex Bennée diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 87ae10bcc9..6c0c4825aa 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -326,6 +326,8 @@ struct TranslationBlock { uint16_t invalid; + bool is_magic; + void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 860e279658..6dd6fd70d0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1394,6 +1394,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * any pending interrupts immediately. */ s->is_jmp = DISAS_UPDATE; + /* s->is_magic = true; */ return; default: unallocated_encoding(s); @@ -1423,6 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, tcg_temp_free_i32(tcg_imm); tcg_temp_free_i32(tcg_op); s->is_jmp = DISAS_UPDATE; + /* s->is_magic = true; */ break; } default: @@ -1592,12 +1594,14 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->is_jmp = DISAS_UPDATE; + /* s->is_magic = true; */ } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ s->is_jmp = DISAS_UPDATE; + /* s->is_magic = true; */ } } @@ -1772,13 +1776,18 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) switch (opc) { case 0: /* BR */ + /* s->is_magic = true; */ + gen_a64_set_pc(s, cpu_reg(s, rn)); + break; case 1: /* BLR */ - case 2: /* RET */ + /* s->is_magic = true; */ gen_a64_set_pc(s, cpu_reg(s, rn)); /* BLR also needs to load return address */ - if (opc == 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); - } + tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); + break; + case 2: /* RET */ + s->is_magic = true; + gen_a64_set_pc(s, cpu_reg(s, rn)); break; case 4: /* ERET */ if (s->current_el == 0) { @@ -1787,6 +1796,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } gen_helper_exception_return(cpu_env); s->is_jmp = DISAS_JUMP; + /* s->is_magic = true; */ return; case 5: /* DRPS */ if (rn != 0x1f) { @@ -11250,6 +11260,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); + dc->is_magic = false; init_tmp_a64_array(dc); @@ -11281,6 +11292,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ dc->is_jmp = DISAS_UPDATE; + /* dc->is_magic = true; */ } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be @@ -11367,6 +11379,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) gen_a64_set_pc_im(dc->pc); /* fall through */ case DISAS_JUMP: + tb->is_magic = dc->is_magic; tcg_gen_lookup_and_goto_ptr(cpu_pc); break; case DISAS_TB_JUMP: diff --git a/target/arm/translate.h b/target/arm/translate.h index 15d383d9af..786eb19335 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -62,6 +62,8 @@ typedef struct DisasContext { bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; + + bool is_magic; /* TCG op index of the current insn_start. */ int insn_start_idx; #define TMP_A64_MAX 16 diff --git a/tcg-runtime.c b/tcg-runtime.c index e987c1f6bb..d9d7c52ae9 100644 --- a/tcg-runtime.c +++ b/tcg-runtime.c @@ -168,7 +168,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) tb = tb_htable_lookup(cpu, addr, cs_base, flags); if (likely(tb)) { atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); - code_ptr = tb->tc_ptr; + if (!tb->is_magic) { + code_ptr = tb->tc_ptr; + } } } }