From patchwork Wed Nov 15 03:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 744151 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1418928F1; Wed, 15 Nov 2023 03:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Ye0LBeIB" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FDE1E4; Tue, 14 Nov 2023 19:25:52 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AELobgR025640; Wed, 15 Nov 2023 03:25:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=wEIeVH/JUTYsKX98+jAp94M88ARF24QQm86idVJCH0g=; b=Ye0LBeIBao8X/Yp01dmbWaNaI1aolrwixiNs61hKToSKviQ6i29tf2Gz7BhRZgOxFE9l x7qHvGKBBOracstOgqW2bIHQX3rNIv7EkPSZD0EdwoSasZAziY0Ump/MxgFWLX03IygV nvbXpO4hUTF7vshw7sinzmS8Qbz2WEvmP5778NVvlNTIj/MpOxcsvkkdeA3dP5Ijv3bH vIBEOM4rU7ROQA80nM0Zno1nCdCE6NlXoU9cosidO2P6EWaScu+e58DPRgiFXLukw71o hBuGGZgPZDQzhAR60q/cMOJMF2aHQ0EDo52T1YU45hTst8uByYzwZN1pk0q/aJnrQf67 eg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ucfka8u83-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:39 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PdaH016200 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:39 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:34 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 2/9] net: mdio: ipq4019: Enable the clocks for ipq5332 platform Date: Wed, 15 Nov 2023 11:25:08 +0800 Message-ID: <20231115032515.4249-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FOHgjdOsE8aPEiwjEgtTyPlMMSho_lpP X-Proofpoint-GUID: FOHgjdOsE8aPEiwjEgtTyPlMMSho_lpP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 For the platform ipq5332, the related GCC clocks need to be enabled to make the GPIO reset of the MDIO slave devices taking effect. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 67 +++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 7 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 9d444f5f7efb..a77982a1a1e1 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -34,16 +34,35 @@ /* MDIO clock source frequency is fixed to 100M */ #define IPQ_MDIO_CLK_RATE 100000000 +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000 +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000 #define IPQ_PHY_SET_DELAY_US 100000 /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +enum mdio_clk_id { + MDIO_CLK_MDIO_AHB, + MDIO_CLK_UNIPHY0_AHB, + MDIO_CLK_UNIPHY0_SYS, + MDIO_CLK_UNIPHY1_AHB, + MDIO_CLK_UNIPHY1_SYS, + MDIO_CLK_CNT +}; + struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; - struct clk *mdio_clk; + struct clk *clk[MDIO_CLK_CNT]; +}; + +const char *const mdio_clk_name[] = { + "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy1_sys_clk" }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) u32 val; int ret; + /* For the platform ipq5332, there are two uniphy available to connect the + * ethernet devices, the uniphy gcc clock should be enabled for resetting + * the connected device such as qca8386 switch or qca8081 PHY effectively. + */ + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { + int i; + unsigned long rate = 0; + + for (i = MDIO_CLK_UNIPHY0_AHB; i < MDIO_CLK_CNT; i++) { + switch (i) { + case MDIO_CLK_UNIPHY0_AHB: + case MDIO_CLK_UNIPHY1_AHB: + rate = IPQ_UNIPHY_AHB_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_SYS: + case MDIO_CLK_UNIPHY1_SYS: + rate = IPQ_UNIPHY_SYS_CLK_RATE; + break; + default: + break; + } + + ret = clk_set_rate(priv->clk[i], rate); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[i]); + if (ret) + return ret; + } + } + /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 * or more resource are specified in the device tree. */ @@ -225,11 +276,11 @@ static int ipq_mdio_reset(struct mii_bus *bus) } /* Configure MDIO clock source frequency if clock is specified in the device tree */ - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); + ret = clk_set_rate(priv->clk[MDIO_CLK_MDIO_AHB], IPQ_MDIO_CLK_RATE); if (ret) return ret; - ret = clk_prepare_enable(priv->mdio_clk); + ret = clk_prepare_enable(priv->clk[MDIO_CLK_MDIO_AHB]); if (ret == 0) mdelay(10); @@ -253,10 +304,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); - priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); - if (IS_ERR(priv->mdio_clk)) - return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018/IPQ5332 */ /* This resource is optional */ for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { @@ -266,6 +313,12 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) res->start, resource_size(res)); } + for (ret = 0; ret < MDIO_CLK_CNT; ret++) { + priv->clk[ret] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[ret]); + if (IS_ERR(priv->clk[ret])) + return PTR_ERR(priv->clk[ret]); + } + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Wed Nov 15 03:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 744150 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A7D74404; Wed, 15 Nov 2023 03:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HvPX18w0" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3D7418C; Tue, 14 Nov 2023 19:26:04 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AF3Ojid020450; Wed, 15 Nov 2023 03:25:52 GMT DKIM-Signature: v=1; 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Wed, 15 Nov 2023 03:25:51 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:47 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 5/9] net: mdio: ipq4019: support MDIO clock frequency divider Date: Wed, 15 Nov 2023 11:25:11 +0800 Message-ID: <20231115032515.4249-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Yn8tRo-Bwc-iLrmWU7cRIMRRpz2pQE-h X-Proofpoint-GUID: Yn8tRo-Bwc-iLrmWU7cRIMRRpz2pQE-h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 The MDIO clock frequency can be divided according to the register value. The MDIO system clock is fixed to 100MHZ, the working frequency is 100MHZ/(divider + 1), the divider value is from the bit[7:0] of control register 0x40. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index ca9cda98d1f8..44a8a866f8ee 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -30,6 +30,9 @@ /* 0 = Clause 22, 1 = Clause 45 */ #define MDIO_MODE_C45 BIT(8) +/* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is 100MHz */ +#define MDIO_CLK_DIV_MASK GENMASK(7, 0) + #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -65,6 +68,7 @@ struct ipq4019_mdio_data { void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; struct gpio_descs *reset_gpios; + int clk_div; }; const char *const mdio_clk_name[] = { @@ -98,6 +102,7 @@ static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -139,6 +144,7 @@ static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -171,6 +177,7 @@ static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -214,6 +221,7 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -431,6 +439,9 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset_gpios), "mii_bus %s couldn't get reset GPIO\n", bus->id); + /* MDIO default frequency is 6.25MHz */ + priv->clk_div = 0xf; + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Wed Nov 15 03:25:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 744149 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20E392E844; Wed, 15 Nov 2023 03:26:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SG1ICeDD" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5C1FED; Tue, 14 Nov 2023 19:26:09 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AF2kpSd006526; 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Wed, 15 Nov 2023 03:25:55 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:51 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 6/9] net: mdio: ipq4019: Support qca8084 switch register access Date: Wed, 15 Nov 2023 11:25:12 +0800 Message-ID: <20231115032515.4249-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: iRXbT_UTQK-CqxY2pwrtibLUTNavA9FY X-Proofpoint-GUID: iRXbT_UTQK-CqxY2pwrtibLUTNavA9FY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 For qca8084 chip, there are GCC, TLMM and security control modules besides the PHY, these moudles are accessed with 32 bits value, which has the special MDIO sequences to read or write this 32bit register. There are initial configurations needed to make qca8084 PHY probeable, and the PHY address of qca8084 can also be customized before creating the PHY device on MDIO bus register, all these configurations are located in switch modules that are accessed by the 32bit register. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 74 +++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 44a8a866f8ee..8dc611666c34 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -53,6 +53,14 @@ #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) +/* QCA8084 includes the PHY chip, GCC/TLMM and the control modules, + * except for the PHY register, other registers are accessed by MDIO bus + * with 32bit value, which has the special MDIO sequences to access the + * switch modules register. + */ +#define IPQ_HIGH_ADDR_PREFIX 0x18 +#define IPQ_LOW_ADDR_PREFIX 0x10 + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -243,6 +251,72 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, return 0; } +static inline void split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page, u16 *sw_addr) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *sw_addr = regaddr & 0xff; +} + +static int qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) +{ + return bus->write(bus, IPQ_HIGH_ADDR_PREFIX | (sw_addr >> 5), sw_addr & 0x1f, page); +} + +static int qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) +{ + int ret, data; + + ret = bus->read(bus, addr, reg); + if (ret >= 0) { + data = ret; + + ret = bus->read(bus, addr, reg | BIT(1)); + if (ret >= 0) + *val = data | ret << 16; + } + + return ret < 0 ? ret : 0; +} + +static int qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) +{ + int ret; + + ret = bus->write(bus, addr, reg, lower_16_bits(val)); + if (!ret) + ret = bus->write(bus, addr, reg | BIT(1), upper_16_bits(val)); + + return ret; +} + +static int qca8084_modify(struct mii_bus *bus, u32 regaddr, u32 clear, u32 set) +{ + u16 reg, addr, page, sw_addr; + u32 val; + int ret; + + split_addr(regaddr, ®, &addr, &page, &sw_addr); + ret = qca8084_set_page(bus, sw_addr, page); + if (ret < 0) + return ret; + + ret = qca8084_mii_read(bus, IPQ_LOW_ADDR_PREFIX | addr, reg, &val); + if (ret < 0) + return ret; + + val &= ~clear; + val |= set; + return qca8084_mii_write(bus, IPQ_LOW_ADDR_PREFIX | addr, reg, val); +}; + /* For the CMN PLL block, the reference clock can be configured according to * the device tree property "cmn_ref_clk", the internal 48MHZ is used by default * on the ipq533 platform. From patchwork Wed Nov 15 03:25:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 744148 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1BD8A5C; Wed, 15 Nov 2023 03:26:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Vnxid4PN" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF76F196; Tue, 14 Nov 2023 19:26:17 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AF10xXa023787; Wed, 15 Nov 2023 03:26:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=5DXY0nDZnSMr33KmsTLop3NblIPu7xp2y0ys9TqpYzU=; b=Vnxid4PN/+1p95xx6sth+Y5UZgJysrCR6CTAXy49HsmNNRHP2UIM7V+lELs/wt9bEHGQ pbTultwKW1DbnaNp6bGa0u+XVqCA0+TVCvRVwM63984fsQSFfLvTjGOL55LgsTXojKmq sR8QmX2xO6KZ4LGFUZEIv05dcnWRK8XqVINmYzta6hGftigvFrsNYfjWjohNTOMwHVfg YajzDrqiAt0tPHUqWcK+uGNLg/2XItsEyTNT+x1+vfYyRngSrU1TmdAPlG15r/aJPTI+ dKMCdVCe9gBue5IiJhPF82DW7Kzb+gKO76wery1z/Gs6O34cYLPYzyvrFoGOJ17sX4J4 Ug== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ucfke0tme-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:26:04 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3Q3AN027042 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:26:03 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:59 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations Date: Wed, 15 Nov 2023 11:25:14 +0800 Message-ID: <20231115032515.4249-9-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4NAnnWRyDbDXXoaCSaZvNVHyMXg0t5_- X-Proofpoint-ORIG-GUID: 4NAnnWRyDbDXXoaCSaZvNVHyMXg0t5_- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 mlxlogscore=976 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 The PHY & PCS clocks need to be enabled and the reset sequence needs to be completed to make qca8084 PHY probeable by MDIO bus. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 133 +++++++++++++++++++++++++++++++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 1c461c243ae0..9bdd49be2361 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -70,6 +70,30 @@ #define QCA8084_PHY_ADDR_MASK GENMASK(19, 0) #define QCA8084_PCS_ADDR_MASK GENMASK(14, 0) +/* QCA8084 GCC & security control registers */ +/* LDO control, BIT20 for PHY0 and PHY1, BIT21 for PHY2 and PHY3 */ +#define EPHY_CFG 0xC90F018 +#define EPHY_CFG_LDO_CTRL GENMASK(21, 20) + +/* GEPHY TX&RX clock control register starts from GEPHY0_TX, + * end with GEPHY3_RX, the gap is 0x20. + */ +#define GEPHY0_TX_CBCR 0xC800058 +#define GEPHY3_RX_CBCR 0xC800138 +#define GEPHY_CBCR_GAP 0x20 + +#define SRDS0_SYS_CBCR 0xC8001A8 +#define SRDS1_SYS_CBCR 0xC8001AC +#define EPHY0_SYS_CBCR 0xC8001B0 +#define EPHY1_SYS_CBCR 0xC8001B4 +#define EPHY2_SYS_CBCR 0xC8001B8 +#define EPHY3_SYS_CBCR 0xC8001BC +#define CLK_EN BIT(0) +#define CLK_RESET BIT(2) + +#define GCC_GEPHY_MISC 0xC800304 +#define GCC_GEPHY_MISC_DSP_RESET GENMASK(4, 0) + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -412,14 +436,121 @@ static int ipq_phy_addr_fixup(struct mii_bus *bus, struct device_node *mdio_node return 0; } +static inline int qca8084_clock_en_set(struct mii_bus *bus, u32 reg, bool enable) +{ + return qca8084_modify(bus, reg, CLK_EN, enable ? CLK_EN : 0); +} + +static inline int qca8084_clock_reset(struct mii_bus *bus, u32 reg) +{ + int ret; + + ret = qca8084_modify(bus, reg, CLK_RESET, CLK_RESET); + if (ret) + return ret; + + usleep_range(20000, 21000); + return qca8084_modify(bus, reg, CLK_RESET, 0); +} + +static int qca8084_clock_config(struct mii_bus *bus) +{ + u32 reg; + int ret; + + /* Enable PCS */ + ret = qca8084_clock_en_set(bus, SRDS0_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, SRDS1_SYS_CBCR, true); + if (ret) + return ret; + + /* Reset PCS */ + ret = qca8084_clock_reset(bus, SRDS0_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, SRDS1_SYS_CBCR); + if (ret) + return ret; + + /* Disable EPHY GMII RX & TX clock */ + reg = GEPHY0_TX_CBCR; + while (reg <= GEPHY3_RX_CBCR) { + ret = qca8084_clock_en_set(bus, reg, false); + if (ret) + return ret; + + reg += GEPHY_CBCR_GAP; + } + + /* Enable EPHY */ + ret = qca8084_clock_en_set(bus, EPHY0_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY1_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY2_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY3_SYS_CBCR, true); + if (ret) + return ret; + + /* Reset EPHY */ + ret = qca8084_clock_reset(bus, EPHY0_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY1_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY2_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY3_SYS_CBCR); + if (ret) + return ret; + + /* Deassert EPHY DSP */ + ret = qca8084_modify(bus, GCC_GEPHY_MISC, GCC_GEPHY_MISC_DSP_RESET, 0); + if (ret) + return ret; + + /* Enable efuse loading into analog circuit */ + ret = qca8084_modify(bus, EPHY_CFG, EPHY_CFG_LDO_CTRL, 0); + if (ret) + return ret; + + /* Sleep 10ms */ + usleep_range(10000, 11000); + return 0; +} + static int ipq_mdio_preinit(struct mii_bus *bus) { + int ret; struct device_node *mdio_node = dev_of_node(&bus->dev); if (!mdio_node) return 0; - return ipq_phy_addr_fixup(bus, mdio_node); + ret = ipq_phy_addr_fixup(bus, mdio_node); + if (ret) + return ret; + + if (of_property_read_bool(mdio_node, "mdio-clk-fixup")) + ret = qca8084_clock_config(bus); + + return ret; } /* For the CMN PLL block, the reference clock can be configured according to