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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709C.mail.protection.outlook.com (10.167.18.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Tue, 28 Nov 2023 16:07:25 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 28 Nov 2023 10:07:23 -0600 From: Ben Cheatham To: , , , , , , , CC: , , , Subject: [PATCH v7 1/5] cxl/port: Add EINJ debugfs files and callback support Date: Tue, 28 Nov 2023 10:06:52 -0600 Message-ID: <20231128160656.166609-2-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> References: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709C:EE_|DM4PR12MB5748:EE_ X-MS-Office365-Filtering-Correlation-Id: e9050e4c-e4a8-429d-2426-08dbf02c1cc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 16:07:25.3701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9050e4c-e4a8-429d-2426-08dbf02c1cc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5748 Add creation of debugfs directories for ports and dports under /sys/kernel/debug/cxl when EINJ support is enabled. The dport directories will contain files for injecting CXL protocol errors. These files are only usable once the EINJ module has loaded and registered callback functions with the CXL core module, before that occurs (or if the EINJ module isn't loaded) the files will do nothing and return an ENODEV error. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- Documentation/ABI/testing/debugfs-cxl | 27 +++++++++ drivers/cxl/core/port.c | 84 +++++++++++++++++++++++++++ drivers/cxl/cxl.h | 10 ++++ 3 files changed, 121 insertions(+) diff --git a/Documentation/ABI/testing/debugfs-cxl b/Documentation/ABI/testing/debugfs-cxl index fe61d372e3fa..782a1bb78884 100644 --- a/Documentation/ABI/testing/debugfs-cxl +++ b/Documentation/ABI/testing/debugfs-cxl @@ -33,3 +33,30 @@ Description: device cannot clear poison from the address, -ENXIO is returned. The clear_poison attribute is only visible for devices supporting the capability. + +What: /sys/kernel/debug/cxl/portX/dportY/einj_types +Date: November, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Prints the CXL protocol error types made available by + the platform in the format "0x ". + The can be written to einj_inject to inject + into dportY. This file is only visible if + CONFIG_ACPI_APEI_EINJ is enabled, and the EINJ module must + be able to reach one (or both) of the CXL_ACPI or CXL_PORT + modules to be functional. + +What: /sys/kernel/debug/cxl/portX/dportY/einj_inject +Date: November, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (WO) Writing an integer to this file injects the corresponding + CXL protocol error into dportY (integer to type mapping is + available by reading from einj_types). If the dport was + enumerated in RCH mode, a CXL 1.1 error is injected, otherwise + a CXL 2.0 error is injected. This file is only visible if + CONFIG_ACPI_APEI_EINJ is enabled, and the EINJ module must + be able to reach one (or both) of the CXL_ACPI or CXL_PORT + modules to be functional. diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 38441634e4c6..acf10415a174 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -783,6 +783,72 @@ static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport, return rc; } +static struct cxl_einj_ops einj_ops; +void cxl_einj_set_ops_cbs(struct cxl_einj_ops *ops) +{ + if (!IS_REACHABLE(CONFIG_ACPI_APEI_EINJ) || !ops) + return; + + einj_ops = *ops; +} +EXPORT_SYMBOL_NS_GPL(cxl_einj_set_ops_cbs, CXL); + +static int cxl_einj_type_show(struct seq_file *f, void *data) +{ + if (!einj_ops.einj_type) + return -ENODEV; + + return einj_ops.einj_type(f, data); +} + +static int cxl_einj_inject(void *data, u64 type) +{ + struct cxl_dport *dport = data; + + if (!einj_ops.einj_inject) + return -ENODEV; + + return einj_ops.einj_inject(dport, type); +} +DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject, "%llx\n"); + +static int cxl_debugfs_create_dport_dir(struct dentry *port_dir, + struct cxl_dport *dport) +{ + struct dentry *dir; + char dir_name[32]; + + snprintf(dir_name, 31, "dport%d", dport->port_id); + dir = debugfs_create_dir(dir_name, port_dir); + if (IS_ERR(dir)) + return PTR_ERR(dir); + + debugfs_create_devm_seqfile(dport->dport_dev, "einj_types", dir, + cxl_einj_type_show); + + debugfs_create_file("einj_inject", 0200, dir, dport, + &cxl_einj_inject_fops); + return 0; +} + +static struct dentry *cxl_debugfs_create_port_dir(struct cxl_port *port) +{ + const char *dir_name = dev_name(&port->dev); + struct dentry *dir; + + if (!IS_ENABLED(CONFIG_ACPI_APEI_EINJ)) + return ERR_PTR(-ENODEV); + + dir = cxl_debugfs_create_dir(dir_name); + if (IS_ERR(dir)) { + dev_dbg(&port->dev, "Failed to create port debugfs dir: %ld\n", + PTR_ERR(dir)); + return dir; + } + + return dir; +} + static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, @@ -861,6 +927,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_dport *parent_dport) { struct cxl_port *port, *parent_port; + struct dentry *dir; port = __devm_cxl_add_port(host, uport_dev, component_reg_phys, parent_dport); @@ -878,6 +945,10 @@ struct cxl_port *devm_cxl_add_port(struct device *host, parent_port ? " to " : "", parent_port ? dev_name(&parent_port->dev) : "", parent_port ? "" : " (root port)"); + + dir = cxl_debugfs_create_port_dir(port); + if (!IS_ERR(dir)) + port->debug_dir = dir; } return port; @@ -1127,6 +1198,7 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, resource_size_t component_reg_phys) { struct cxl_dport *dport; + int rc; dport = __devm_cxl_add_dport(port, dport_dev, port_id, component_reg_phys, CXL_RESOURCE_NONE); @@ -1136,6 +1208,11 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "dport added to %s\n", dev_name(&port->dev)); + + rc = cxl_debugfs_create_dport_dir(port->debug_dir, dport); + if (rc) + dev_dbg(dport_dev, + "Failed to create dport debugfs dir: %d\n", rc); } return dport; @@ -1156,6 +1233,7 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, resource_size_t rcrb) { struct cxl_dport *dport; + int rc; if (rcrb == CXL_RESOURCE_NONE) { dev_dbg(&port->dev, "failed to add RCH dport, missing RCRB\n"); @@ -1170,6 +1248,12 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "RCH dport added to %s\n", dev_name(&port->dev)); + + rc = cxl_debugfs_create_dport_dir(port->debug_dir, dport); + if (rc) + dev_dbg(dport_dev, + "Failed to create rch dport debugfs dir: %d\n", + rc); } return dport; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 687043ece101..3c7744fc3106 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -590,6 +590,7 @@ struct cxl_dax_region { * @depth: How deep this port is relative to the root. depth 0 is the root. * @cdat: Cached CDAT data * @cdat_available: Should a CDAT attribute be available in sysfs + * @debug_dir: dentry for port in cxl debugfs (optional) */ struct cxl_port { struct device dev; @@ -612,6 +613,7 @@ struct cxl_port { size_t length; } cdat; bool cdat_available; + struct dentry *debug_dir; }; static inline struct cxl_dport * @@ -813,6 +815,14 @@ bool is_cxl_nvdimm_bridge(struct device *dev); int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); +struct cxl_einj_ops { + int (*einj_type)(struct seq_file *f, void *data); + int (*einj_inject)(struct cxl_dport *dport, u64 type); +}; + +void cxl_einj_set_ops_cbs(struct cxl_einj_ops *ops); + + #ifdef CONFIG_CXL_REGION bool is_cxl_pmem_region(struct device *dev); struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); From patchwork Tue Nov 28 16:06:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 748149 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="k8R4mEOy" Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2061.outbound.protection.outlook.com [40.107.212.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4867131; Tue, 28 Nov 2023 08:07:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TnmpAtfg8add3M11QLlgDROU39iuMrdBUK89/KqwycI5UNziyEDGhmLCr5HrC3CVCInTRUoghVnimGINth9eOkdCsonewxuxJ2MTsfp2ZDhJN3VqXVqzW/r9RPFJ+XswvZaV2KTUa9/HY/d9Sb/sr/UUG5i6lF7G3YWpqOVXwngQ0SgBSxaU+UaNRmSjJW+/1lHXSm8I0Urm8LQI/NYSavM3bQfABkwLjWPaa/XPx0AybU8h7lu7l9vL1QjmEiji5mgJ9pMn3WsKcd+Rey1ioTA6UAvhPhBi/2BwLYqg0nxvaeJUucZGjjJefFFyV3Sg+UYSCPuz5MlUYU6zj3qdvQ== ARC-Message-Signature: i=1; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709D.mail.protection.outlook.com (10.167.18.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Tue, 28 Nov 2023 16:07:39 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 28 Nov 2023 10:07:37 -0600 From: Ben Cheatham To: , , , , , , , CC: , , , Subject: [PATCH v7 2/5] ACPI: Add CXL protocol error defines Date: Tue, 28 Nov 2023 10:06:53 -0600 Message-ID: <20231128160656.166609-3-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> References: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|DM6PR12MB5005:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b5d0b65-41bc-4a51-3fc2-08dbf02c256d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- I made a pull request for adding this support into the acpica project that has already been merged [1], Feel free to discard this commit and use the acpica changes instead. [1]: Link: https://github.com/acpica/acpica/pull/884 --- include/acpi/actbl1.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index a33375e055ad..1f58c5d86869 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1096,6 +1096,12 @@ enum acpi_einj_command_status { #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) #define ACPI_EINJ_PLATFORM_FATAL (1<<11) +#define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) +#define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) +#define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) +#define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) +#define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) +#define ACPI_EINJ_CXL_MEM_FATAL (1<<17) #define ACPI_EINJ_VENDOR_DEFINED (1<<31) /******************************************************************************* From patchwork Tue Nov 28 16:06:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 747844 Authentication-Results: smtp.subspace.kernel.org; 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Tue, 28 Nov 2023 10:08:08 -0600 From: Ben Cheatham To: , , , , , , , CC: , , , Subject: [PATCH v7 3/5] EINJ: Separate CXL errors from other EINJ errors Date: Tue, 28 Nov 2023 10:06:54 -0600 Message-ID: <20231128160656.166609-4-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> References: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|SA1PR12MB9003:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f16708b-423c-4eb8-29e9-08dbf02c392e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xtjAwOR1okEFeUvySze1nwMYOPI1unPq3H/ucXGUjpiDki4+T4ilTZReVAIhXooDomu1AyugIwt3+hTvm1V9aUnUFy+BcB84wwV/MYy2peCgM4WwbRxywJmg1gt8pEI6BCl8oAUVzccXFrvggvN/JTm1EZfXPS/FuU+WDjj0cc2n5NYqZ0RIPFs+S4pMaaJbSPJFKj8h0ENeGoJocpIz/p50o40NT+1fmd0oQ93UZVU2J7vK7JtAqQiZab/SNN9K99fk7pKCr0j0zNbzbHISI5ASgDJDzHx1qCOLITYZ8+lwazKfM++XDAMMcDfA4U3dmwjVsvDY0gl4PfQgCoCAD+uHZF97c/QXQlDFMOSE40QeWnjsIwBfk7Eqsz/qR1iZuICfLyGdh/3zMXExgi1WmuvqJHxG1FbzUPj4530oTVv/J2HwkEgEz0scy1wQFhWESyyhHjo1yVFlpl7aUPDPyBmKBOKM0Qz1e0+qcU9B6GfPdOGPC9qmlYYKt1QCcAuo/MinD36W4MRkqPFNx6TYbMK09XaUUgrxaZ1vxPX6P6N1hhFVwedM9sM9DNIa+ITydIPKPZUMpEquSEZ74/tfEXMG9/Xprm3DVqQeUkANtZjU9NnX2zCqHkvqRQHzEVmHbWKtlk/W/XaYJSCQu0h2JJtEDPEjXS5lxFE5bSDl90iNiCr19kd6jvBa0ZA7rQbqwEeMVRF6rli6yi5UEDzGWNFRoI2DGKFzdFkrwr7bzxUq+y3QJ7BXIu4+mhJ8ycHdcUStlwF/09C5ujbIvnT6SQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9003 Separate CXL error types from other EINJ error types and disallow them in the legacy EINJ interface under /sys/kernel/debug/apei/einj. Support for the CXL error types will be added under /sys/kernel/debug/cxl in the next commit. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- drivers/acpi/apei/einj.c | 56 +++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 013eb621dc92..330329ac2f1f 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -36,6 +36,12 @@ #define MEM_ERROR_MASK (ACPI_EINJ_MEMORY_CORRECTABLE | \ ACPI_EINJ_MEMORY_UNCORRECTABLE | \ ACPI_EINJ_MEMORY_FATAL) +#define CXL_ERROR_MASK (ACPI_EINJ_CXL_CACHE_CORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_UNCORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_FATAL | \ + ACPI_EINJ_CXL_MEM_CORRECTABLE | \ + ACPI_EINJ_CXL_MEM_UNCORRECTABLE | \ + ACPI_EINJ_CXL_MEM_FATAL) /* * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action. @@ -537,8 +543,11 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, if (type & ACPI5_VENDOR_BIT) { if (vendor_flags != SETWA_FLAGS_MEM) goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) + } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { goto inject; + } else if ((type & CXL_ERROR_MASK) && (flags & SETWA_FLAGS_MEM)) { + goto inject; + } /* * Disallow crazy address masks that give BIOS leeway to pick @@ -590,6 +599,9 @@ static const char * const einj_error_type_string[] = { "0x00000200\tPlatform Correctable\n", "0x00000400\tPlatform Uncorrectable non-fatal\n", "0x00000800\tPlatform Uncorrectable fatal\n", +}; + +static const char * const einj_cxl_error_type_string[] = { "0x00001000\tCXL.cache Protocol Correctable\n", "0x00002000\tCXL.cache Protocol Uncorrectable non-fatal\n", "0x00004000\tCXL.cache Protocol Uncorrectable fatal\n", @@ -615,29 +627,21 @@ static int available_error_type_show(struct seq_file *m, void *v) DEFINE_SHOW_ATTRIBUTE(available_error_type); -static int error_type_get(void *data, u64 *val) -{ - *val = error_type; - - return 0; -} - -static int error_type_set(void *data, u64 val) +static int validate_error_type(u64 type) { + u32 tval, vendor, available_error_type = 0; int rc; - u32 available_error_type = 0; - u32 tval, vendor; /* Only low 32 bits for error type are valid */ - if (val & GENMASK_ULL(63, 32)) + if (type & GENMASK_ULL(63, 32)) return -EINVAL; /* * Vendor defined types have 0x80000000 bit set, and * are not enumerated by ACPI_EINJ_GET_ERROR_TYPE */ - vendor = val & ACPI5_VENDOR_BIT; - tval = val & 0x7fffffff; + vendor = type & ACPI5_VENDOR_BIT; + tval = type & 0x7fffffff; /* Only one error type can be specified */ if (tval & (tval - 1)) @@ -646,9 +650,31 @@ static int error_type_set(void *data, u64 val) rc = einj_get_available_error_type(&available_error_type); if (rc) return rc; - if (!(val & available_error_type)) + if (!(type & available_error_type)) return -EINVAL; } + + return 0; +} + +static int error_type_get(void *data, u64 *val) +{ + *val = error_type; + + return 0; +} + +static int error_type_set(void *data, u64 val) +{ + int rc; + + if (val & CXL_ERROR_MASK && !(val & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(val); + if (rc) + return rc; + error_type = val; return 0; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001709C.mail.protection.outlook.com (10.167.18.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Tue, 28 Nov 2023 16:08:25 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 28 Nov 2023 10:08:22 -0600 From: Ben Cheatham To: , , , , , , , CC: , , , Subject: [PATCH v7 4/5] cxl/port, EINJ: Add CXL EINJ callback functions Date: Tue, 28 Nov 2023 10:06:55 -0600 Message-ID: <20231128160656.166609-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> References: <20231128160656.166609-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709C:EE_|SJ2PR12MB9244:EE_ X-MS-Office365-Filtering-Correlation-Id: db7a791d-87ce-4709-d996-08dbf02c4066 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 16:08:25.1985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db7a791d-87ce-4709-d996-08dbf02c4066 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9244 Add functions to the EINJ module to be used in the CXL module for CXL protocol error injection. The callbacks implement the einj_types and einj_inject files under /sys/kernel/debug/cxl/portX/dportY. These two files work in the same way as the available_error_types and error_inject files under /sys/kernel/debug/apei/einj, but only for CXL error types. If the dport is enumerated in RCH (CXL 1.1) mode, a CXL 1.1 error is injected into the dport; a CXL 2.0 error is injected otherwise. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- drivers/acpi/apei/Kconfig | 3 ++ drivers/acpi/apei/einj.c | 105 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 6b18f8bc7be3..100c27beb581 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -11,6 +11,9 @@ config ACPI_APEI select PSTORE select UEFI_CPER depends on HAVE_ACPI_APEI + imply CXL_BUS + imply CXL_ACPI + imply CXL_PORT help APEI allows to report errors (for example from the chipset) to the operating system. This improves NMI handling diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 330329ac2f1f..98d5e6d60a02 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -21,9 +21,11 @@ #include #include #include +#include #include #include "apei-internal.h" +#include "../../cxl/cxl.h" #undef pr_fmt #define pr_fmt(fmt) "EINJ: " fmt @@ -627,6 +629,25 @@ static int available_error_type_show(struct seq_file *m, void *v) DEFINE_SHOW_ATTRIBUTE(available_error_type); +static int cxl_einj_available_error_type(struct seq_file *m, void *v) +{ + int cxl_err, rc; + u32 available_error_type = 0; + + rc = einj_get_available_error_type(&available_error_type); + if (rc) + return rc; + + for (int pos = 0; pos < ARRAY_SIZE(einj_cxl_error_type_string); pos++) { + cxl_err = ACPI_EINJ_CXL_CACHE_CORRECTABLE << pos; + + if (available_error_type & cxl_err) + seq_puts(m, einj_cxl_error_type_string[pos]); + } + + return 0; +} + static int validate_error_type(u64 type) { u32 tval, vendor, available_error_type = 0; @@ -657,6 +678,68 @@ static int validate_error_type(u64 type) return 0; } +static int cxl_dport_get_sbdf(struct cxl_dport *dport, u64 *sbdf) +{ + struct pci_dev *pdev; + struct pci_bus *pbus; + struct pci_host_bridge *bridge; + u64 seg = 0, bus; + + if (!dev_is_pci(dport->dport_dev)) + return -EINVAL; + + pdev = to_pci_dev(dport->dport_dev); + pbus = pdev->bus; + bridge = pci_find_host_bridge(pbus); + + if (!bridge) + return -ENODEV; + + if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET) + seg = bridge->domain_nr << 24; + + bus = pbus->number << 16; + *sbdf = seg | bus | pdev->devfn; + + return 0; +} + +static int cxl_einj_inject_error(struct cxl_dport *dport, u64 type) +{ + u64 param1 = 0, param2 = 0, param4 = 0; + u32 flags; + int rc; + + /* Only CXL error types can be specified */ + if (type & ~CXL_ERROR_MASK || (type & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(type); + if (rc) + return rc; + + /* + * If dport is in restricted mode, inject a CXL 1.1 error, + * otherwise inject a CXL 2.0 error + */ + if (dport->rch) { + if (dport->rcrb.base == CXL_RESOURCE_NONE) + return -EINVAL; + + param1 = (u64) dport->rcrb.base; + param2 = 0xfffffffffffff000; + flags = 0x2; + } else { + rc = cxl_dport_get_sbdf(dport, ¶m4); + if (rc) + return rc; + + flags = 0x4; + } + + return einj_error_inject(type, flags, param1, param2, 0, param4); +} + static int error_type_get(void *data, u64 *val) { *val = error_type; @@ -668,6 +751,7 @@ static int error_type_set(void *data, u64 val) { int rc; + /* CXL error types have to be injected from cxl debugfs */ if (val & CXL_ERROR_MASK && !(val & ACPI5_VENDOR_BIT)) return -EINVAL; @@ -714,6 +798,7 @@ static int __init einj_init(void) { int rc; acpi_status status; + struct cxl_einj_ops cxl_ops; struct apei_exec_context ctx; if (acpi_disabled) { @@ -793,6 +878,15 @@ static int __init einj_init(void) einj_debug_dir, &vendor_flags); } + if (IS_REACHABLE(CONFIG_CXL_ACPI) || IS_REACHABLE(CONFIG_CXL_PORT)) { + cxl_ops = (struct cxl_einj_ops) { + .einj_type = cxl_einj_available_error_type, + .einj_inject = cxl_einj_inject_error, + }; + + cxl_einj_set_ops_cbs(&cxl_ops); + } + pr_info("Error INJection is initialized.\n"); return 0; @@ -810,8 +904,18 @@ static int __init einj_init(void) static void __exit einj_exit(void) { + struct cxl_einj_ops cxl_ops; struct apei_exec_context ctx; + if (IS_REACHABLE(CONFIG_CXL_ACPI) || IS_REACHABLE(CONFIG_CXL_PORT)) { + cxl_ops = (struct cxl_einj_ops) { + .einj_type = NULL, + .einj_inject = NULL, + }; + + cxl_einj_set_ops_cbs(&cxl_ops); + } + if (einj_param) { acpi_size size = (acpi5) ? sizeof(struct set_error_type_with_address) : @@ -832,4 +936,5 @@ module_exit(einj_exit); MODULE_AUTHOR("Huang Ying"); MODULE_DESCRIPTION("APEI Error INJection support"); +MODULE_IMPORT_NS(CXL); MODULE_LICENSE("GPL"); From patchwork Tue Nov 28 16:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 747843 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="La+tLA2H" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2057.outbound.protection.outlook.com [40.107.220.57]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E33F2127; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 16:08:39.8475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68f7ca55-d69d-4f25-1b02-08dbf02c4922 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6230 Update EINJ documentation with build requirements for CXL error types and how to inject CXL error types. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- Documentation/firmware-guide/acpi/apei/einj.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index d6b61d22f525..83afe3bac793 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -181,6 +181,18 @@ You should see something like this in dmesg:: [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) +CXL error types are supported from ACPI 6.5 onwards. These error types +are not available in the legacy interface at /sys/kernel/debug/apei/einj, +but are instead at /sys/kernel/debug/cxl/portX/dportY. Inside the dportY +directory are two files, einj_types and einj_inject. These files work the +same as the available_error_type and error_inject files (read the error +types from einj_types and write the type to inject to einj_inject). + +To use these error types one of (or both) ``CONFIG_CXL_ACPI`` or +``CONFIG_CXL_PORT`` must be reachable by the EINJ module; if +``CONFIG_ACPI_APEI_EINJ`` == y/m, then at least one of ``CONFIG_CXL_ACPI`` +or ``CONFIG_CXL_PORT`` must also be set to y/m. + Special notes for injection into SGX enclaves: There may be a separate BIOS setup option to enable SGX injection.