From patchwork Tue Aug 27 12:13:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172274 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5701689ily; Tue, 27 Aug 2019 05:14:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqwVL6fjKY9+FSRt6fgfXCy02HpEvpPJa/dzeD+3/OZ9OYhpQvUDOoPLYAvvMJz3WrqLokH3 X-Received: by 2002:a62:e910:: with SMTP id j16mr26462363pfh.123.1566908068217; Tue, 27 Aug 2019 05:14:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908068; cv=none; d=google.com; s=arc-20160816; b=SbE5rMv1fLHnzWqlJeJj1cCIG3sx9F4o54h8dIfXCwmSzj4T+Dw9TovecK0Yua6sO+ wvAxZQ/IjRX/613N+Fn8jw9pxDknHE5E9iRdiiXDs8eAbDClScR3E4KTl7ScweuexP20 hYz7gK11wiascNy1Ia53AF8MjOJzNkBIciHfeoFUQlDdr/dggZkcJI3mCtTrNOx8BXEi d/x4Tiolgkx4OhQtu7S3ZkdWla7uUB68g2KKbdI0mWbgViZUCahh9YxtrE2K1Q+0o3uo TGFEcK7zwV+vDa9buxEBTe4WKptYA/ABUIcolxYDkVBOjCEaKu28D1NVGBoiZ4LAaHwn p8IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=9mtKoSMez54d8NJGT8JTZoc4JmxmRZktoKl1k+QGsQs=; b=jpuYJcD3bcqE2b4fbMWKwt6y8ekVotjtJwI5dkFrWi9nL55Wl0ETsonepvpeoIuWiA EO9B7CgjcdFA6WqJq8lWsO2iPp6+FQSB9Y+2epSnTa+oyCXWnoHzcqyAWVVQ6OWxiyZc Oc8qUVXiKEJpWD+yVdVvgQOIJKqgzHyog9D0Xj0cD1OfN0+XY8wAQbU9YVHazgOuAEwm mB/YuHnEmuNP9HIPy70dVsoYhbBSEtDOr1nRMNHTa+D80lYKUbaz/R83YH1eUez+9T+M Fyuh6cC/LANtNJAW0fXztSofuWUKrxJJKq28NGt36DLR+o8EYxg0ZdthbuHWTxLh5mMo XFwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwHyoJ5O; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v189si11823811pgd.289.2019.08.27.05.14.27; Tue, 27 Aug 2019 05:14:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwHyoJ5O; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728222AbfH0MO1 (ORCPT + 16 others); Tue, 27 Aug 2019 08:14:27 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:45643 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729313AbfH0MO1 (ORCPT ); Tue, 27 Aug 2019 08:14:27 -0400 Received: by mail-pg1-f195.google.com with SMTP id o13so12585936pgp.12 for ; Tue, 27 Aug 2019 05:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=9mtKoSMez54d8NJGT8JTZoc4JmxmRZktoKl1k+QGsQs=; b=gwHyoJ5OivXK8jYHbUrKV6ew1FVaKQgpKRP/HhGzFtZ1VF4YknWTMo279VngkF2yLX qbjXRPSqNgUmvkVo7ZZufjsd5juW5JP08bquqWLiqEZxMTRlMZ2H3UQUqAgqd87xGIlm G0TZpY4aSj+bg12S4SuLHHcNU0Zix0vZ08KFu1xHwxkDU/d4+b9j0ZlpR4Lkv1g3ZvdA iVZ2KMkNkPuHYcJ0wdcIGJaI+SX9/6vAVEhPsPZyLX1phHC7A9qs/JzffNDxiWlk1wMW 1hWZuQnDdL9mWnBeg+1TJMf7rGoF+ypDxSpigO1xl/Mlueb5UJLCAKEyM/PM5lijoaZw /cGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9mtKoSMez54d8NJGT8JTZoc4JmxmRZktoKl1k+QGsQs=; b=lDI0yNhxcm0OEjgGv2AxPX3QjoZO2hclosbJ7EWQvm8RrAmE7mBM/j/4ehh0gkesma leNmgkMEEV1bEVBeVM9fVz6P0bjZb3NnrQpHVSDDUWlaqVeLcKDtcSr5t2VU4mk/gP/a +uwCAYZFDdhfnfJhjn/Gd4A98KhGpOVZ75ALnkvTxqYS7aGAlpDR3xAApcAQZBjTdAhP AI/VwofPY/viUNlMZ3Ce09DOc2IBJ4Uz6RctfX01YNBUYUOh+UwDhu2tJTHoAWgZPXmL X5IR3b0KpH/UsLA6FqS2THKJhYnWRebt8Lj5MMM5ZM4fQUKPSWrZtYda0Ij28EIiJknD khNQ== X-Gm-Message-State: APjAAAUKIHQnPat+qDGRTdv3G127ZGJN2dwy1y1UIhqSfKKLs5t+ZH0t cRU5euLJVxtCE+jkFpKU1W+REQ== X-Received: by 2002:a17:90a:9f09:: with SMTP id n9mr25204629pjp.72.1566908066115; Tue, 27 Aug 2019 05:14:26 -0700 (PDT) Received: from localhost ([49.248.54.193]) by smtp.gmail.com with ESMTPSA id g18sm15347679pgm.9.2019.08.27.05.14.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Aug 2019 05:14:25 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, sboyd@kernel.org, masneyb@onstation.org, marc.w.gonzalez@free.fr, Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v2 01/15] drivers: thermal: tsens: Get rid of id field in tsens_sensor Date: Tue, 27 Aug 2019 17:43:57 +0530 Message-Id: <7a6e3d73c68d3fcf4674a6bcccc960505a601414.1566907161.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are two fields - id and hw_id - to track what sensor an action was to performed on. This was because the sensors connected to a TSENS IP might not be contiguous i.e. 1, 2, 4, 5 with 3 being skipped. This causes confusion in the code which uses hw_id sometimes and id other times (tsens_get_temp, tsens_get_trend). Switch to only using the hw_id field to track the physical ID of the sensor. When we iterate through all the sensors connected to an IP block, we use an index i to loop through the list of sensors, and then return the actual hw_id that is registered on that index. Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-8960.c | 4 ++-- drivers/thermal/qcom/tsens-common.c | 16 +++++++++------- drivers/thermal/qcom/tsens.c | 11 +++++------ drivers/thermal/qcom/tsens.h | 10 ++++------ 4 files changed, 20 insertions(+), 21 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 8d9b721dadb65..3e1436fda1ebd 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -243,11 +243,11 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } -static int get_temp_8960(struct tsens_priv *priv, int id, int *temp) +static int get_temp_8960(struct tsens_sensor *s, int *temp) { int ret; u32 code, trdy; - const struct tsens_sensor *s = &priv->sensor[id]; + struct tsens_priv *priv = s->priv; unsigned long timeout; timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 528df88012543..c037bdf92c663 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -83,11 +83,12 @@ static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) return degc; } -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; - u32 temp_idx = LAST_TEMP_0 + s->hw_id; - u32 valid_idx = VALID_0 + s->hw_id; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; + u32 temp_idx = LAST_TEMP_0 + hw_id; + u32 valid_idx = VALID_0 + hw_id; u32 last_temp = 0, valid, mask; int ret; @@ -123,12 +124,13 @@ int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp) return 0; } -int get_temp_common(struct tsens_priv *priv, int i, int *temp) +int get_temp_common(struct tsens_sensor *s, int *temp) { - struct tsens_sensor *s = &priv->sensor[i]; + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; int last_temp = 0, ret; - ret = regmap_field_read(priv->rf[LAST_TEMP_0 + s->hw_id], &last_temp); + ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); if (ret) return ret; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0627d8615c307..6ed687a6e53cd 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -14,19 +14,19 @@ static int tsens_get_temp(void *data, int *temp) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; - return priv->ops->get_temp(priv, s->id, temp); + return priv->ops->get_temp(s, temp); } static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend) { - const struct tsens_sensor *s = data; + struct tsens_sensor *s = data; struct tsens_priv *priv = s->priv; if (priv->ops->get_trend) - return priv->ops->get_trend(priv, s->id, trend); + return priv->ops->get_trend(s, trend); return -ENOTSUPP; } @@ -86,8 +86,7 @@ static int tsens_register(struct tsens_priv *priv) for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; - priv->sensor[i].id = i; - tzd = devm_thermal_zone_of_sensor_register(priv->dev, i, + tzd = devm_thermal_zone_of_sensor_register(priv->dev, priv->sensor[i].hw_id, &priv->sensor[i], &tsens_of_ops); if (IS_ERR(tzd)) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2fd94997245bf..d022e726d0747 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -31,7 +31,6 @@ enum tsens_ver { * @priv: tsens device instance that this sensor is connected to * @tzd: pointer to the thermal zone that this sensor is in * @offset: offset of temperature adjustment curve - * @id: Sensor ID * @hw_id: HW ID can be used in case of platform-specific IDs * @slope: slope of temperature adjustment curve * @status: 8960-specific variable to track 8960 and 8660 status register offset @@ -40,7 +39,6 @@ struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; int offset; - unsigned int id; unsigned int hw_id; int slope; u32 status; @@ -61,13 +59,13 @@ struct tsens_ops { /* mandatory callbacks */ int (*init)(struct tsens_priv *priv); int (*calibrate)(struct tsens_priv *priv); - int (*get_temp)(struct tsens_priv *priv, int i, int *temp); + int (*get_temp)(struct tsens_sensor *s, int *temp); /* optional callbacks */ int (*enable)(struct tsens_priv *priv, int i); void (*disable)(struct tsens_priv *priv); int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); - int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend); + int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ @@ -313,8 +311,8 @@ struct tsens_priv { char *qfprom_read(struct device *dev, const char *cname); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); -int get_temp_tsens_valid(struct tsens_priv *priv, int i, int *temp); -int get_temp_common(struct tsens_priv *priv, int i, int *temp); +int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); +int get_temp_common(struct tsens_sensor *s, int *temp); /* TSENS target */ extern const struct tsens_plat_data data_8960; From patchwork Tue Aug 27 12:13:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172275 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5701805ily; Tue, 27 Aug 2019 05:14:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqxkM/XnZhMRMSsM/KW12T1mZ2d9PUS+yJlLbDTnUTluSUVteuVC09GR02KDCvrQLdiESaMa X-Received: by 2002:a63:69c1:: with SMTP id e184mr20089863pgc.198.1566908073791; Tue, 27 Aug 2019 05:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908073; cv=none; d=google.com; s=arc-20160816; b=NHBTzetUHKHVUpWV69MS8URCre9PBvN8rRpvvE3zyteJC4uLbwoi/tFNjfCfzHeytF opLHjQ8r7x4WhLOrV4ccTkBeQe3ipv8QadMl/J9B9+go5ptehxW8eudS3T1cggvBnoSE E+ZvSRbj8UOz6wCgAZmwwFQ11WIg7MvJKTdRhY/yyU4A8OSEHpN4sWIiGb12+0/b/p5T NtAikL1WT8VB5Myh+TmWBtP1FrMLNFtHMihhSOheWLlwVPFahlT1JzLDVhy/eArEQM+1 UK17f6xxRsq1wB3Ej+00dSaSADfuqrwFMtjkTMmTu/RvgHJAGFraZH8K0QlGz64/Hf35 htsQ== ARC-Message-Signature: i=1; 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Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 6ed687a6e53cd..542a7f8c3d962 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -149,6 +149,8 @@ static int tsens_probe(struct platform_device *pdev) priv->feat = data->feat; priv->fields = data->fields; + platform_set_drvdata(pdev, priv); + if (!priv->ops || !priv->ops->init || !priv->ops->get_temp) return -EINVAL; @@ -167,11 +169,7 @@ static int tsens_probe(struct platform_device *pdev) } } - ret = tsens_register(priv); - - platform_set_drvdata(pdev, priv); - - return ret; + return tsens_register(priv); } static int tsens_remove(struct platform_device *pdev) From patchwork Tue Aug 27 12:13:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172276 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5701889ily; Tue, 27 Aug 2019 05:14:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxl85XQpUmnkPskHX4UymwqPPPRKOkF01emUedRSCtf44pa3c1FsnVqrpBfQ2B+Ill78Axv X-Received: by 2002:a65:68d9:: with SMTP id k25mr21115642pgt.337.1566908077879; Tue, 27 Aug 2019 05:14:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908077; cv=none; d=google.com; s=arc-20160816; b=u3lt9Q8O2ztnSRQ1JDQHcLUqpb/KA/d9CIFTmomyP9X0WD+si8m1tEHzWKRWgZSHzh tLUMmW0rw7mFKwbMGjlRkvr40nEkz53JrGjSQA3QtD+Okj28lq+ocFHkFMbsu3amhNjJ jet8RnhP5bofdlLkDISgz9Vx81eyyXJyrNDeA+DKWFv+fLBRlAtbtOnU07vc9liMd+5+ wouNYC4tBsRu95zDPLKBIzroF2BL4PXmogpLd55z3Cp0qXNVT1KwuOyBdWxOUqy51wiq UvVeH+zSJ6RH1NDZbJKQ0JdUhOpMhvWOz1XregE1tUdsPAzgHCCvsTHuKi7xUaomatcr Fw1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=cALbZwSOU8EvtF0iOAGpF4/JluhlENqnhyD2XhJQYmg=; b=y0LVpKXOCG98JYFTf2/ISUAvHBhvrh30Fg0aUJ7voKuQZGAAyVUtGUMnAE9N9rhvVu irjjggX2u/Rq67o1ksNTravtUeZ15ETt/f50Uxgl/Jn8gPz2umk5MeqjCjsvn8LLBfLz A7kc4FLZ1XCPMYyCgbzHoaSDhaCXyr3DVMl9HCwZh13uzbAmuNzmi1j5jKeldayChy6k IpctwXng8uNQG903yq/gzN+UqgxNPwi8B5N9L+MtgjQDMnPkknKDhpLUi2rxi2XDEP0O 0FsbdE2eydnnwj6KIguZy6/2ZkD4NN5U2I22aAiVjTGyyruHUtCjvSbkOagHVeh9O/WB HkfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mcxwMmfb; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria Reviewed-by: Stephen Boyd Reviewed-by: Daniel Lezcano --- drivers/thermal/qcom/tsens-common.c | 8 ++++---- drivers/thermal/qcom/tsens.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index c037bdf92c663..7437bfe196e50 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -42,8 +42,8 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, for (i = 0; i < priv->num_sensors; i++) { dev_dbg(priv->dev, - "sensor%d - data_point1:%#x data_point2:%#x\n", - i, p1[i], p2[i]); + "%s: sensor%d - data_point1:%#x data_point2:%#x\n", + __func__, i, p1[i], p2[i]); priv->sensor[i].slope = SLOPE_DEFAULT; if (mode == TWO_PT_CALIB) { @@ -60,7 +60,7 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - (CAL_DEGC_PT1 * priv->sensor[i].slope); - dev_dbg(priv->dev, "offset:%d\n", priv->sensor[i].offset); + dev_dbg(priv->dev, "%s: offset:%d\n", __func__, priv->sensor[i].offset); } } @@ -209,7 +209,7 @@ int __init init_common(struct tsens_priv *priv) if (ret) goto err_put_device; if (!enabled) { - dev_err(dev, "tsens device is not enabled\n"); + dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; } diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 542a7f8c3d962..06c6bbd69a1a7 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -127,7 +127,7 @@ static int tsens_probe(struct platform_device *pdev) of_property_read_u32(np, "#qcom,sensors", &num_sensors); if (num_sensors <= 0) { - dev_err(dev, "invalid number of sensors\n"); + dev_err(dev, "%s: invalid number of sensors\n", __func__); return -EINVAL; } @@ -156,7 +156,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->init(priv); if (ret < 0) { - dev_err(dev, "tsens init failed\n"); + dev_err(dev, "%s: init failed\n", __func__); return ret; } @@ -164,7 +164,7 @@ static int tsens_probe(struct platform_device *pdev) ret = priv->ops->calibrate(priv); if (ret < 0) { if (ret != -EPROBE_DEFER) - dev_err(dev, "tsens calibration failed\n"); + dev_err(dev, "%s: calibration failed\n", __func__); return ret; } } From patchwork Tue Aug 27 12:14:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172277 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5701994ily; Tue, 27 Aug 2019 05:14:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPJsv6HuUhThb8pQ0eBPtvWGGhjTHQrdsw4RqUtNuasbd8p8CAkTHbcywLW1U+8eZNat8S X-Received: by 2002:aa7:94a8:: with SMTP id a8mr25563915pfl.75.1566908082911; Tue, 27 Aug 2019 05:14:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908082; cv=none; d=google.com; s=arc-20160816; b=Zem5fMs2iaif5bRxNlfKQ9GPx8HBmHiuZXUmhCCxGqZ0qvskzOhlC6nq2BzC9VEsQO gGd72kxJtjm6Eu7iiZsZGTGmihUiQLC2zJuuMt7BhszKZUL5saZ8AjHi5HDlWcd4wgNl /FUrAtdB04vGoUMXLrtTQHJbY0bYhEXCgmT2Li0BIEd5fsK0cfumPiYUfsUHQa2qxGIr dfsU07kxoN7QIa/mhtl1GalOM9w5mRpW7UJUL+1Uvrq6DWPaVCXB5y/ywz3nHdljNVPb WArheN1sbL9GYZuKIHx6FEJjyiOk4jt/BGU3SOv+n5niqNsomdEgGBrsv4t+R2Fn8WMp G6ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=txPasp1wzNBQGWPXENBmgM/OMI6t6T6Qqvvtan2Z3Gs=; b=pSVpdS/wmXgP7J58cc+I1ZDS/ry9CiDYiIxxbDhISGyieZuelDA/KrdZ3Svis/KGuQ A/BGhEZiFHyxAqrGwEDW9/HZcAVwgYxVQs+CVSM2GqCOBYNhgRPxtUY8Isk+xb+sOc0u Vnyq2g/Zi49uoSlim0ZitLrIUImyePyNVRD01d1jJzid9HphuJuBjtbqWSo7zWORr2Fl UHUS8Lxrqn8vhiv3pc6cjp71TT9zkz138WcTgfb0+KdvhGF+oMOhcMESI/zlwEU3k0sK Li5j4MIwR/QaGVEE811521TmkUkhGT2ZfgGOyOxVSmkU0rKMdZk4UOa1tx3knLk9Qr+Q CT9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hccm/k4B"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q206si11550504pgq.483.2019.08.27.05.14.42; Tue, 27 Aug 2019 05:14:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hccm/k4B"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729729AbfH0MOl (ORCPT + 16 others); Tue, 27 Aug 2019 08:14:41 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:38176 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729706AbfH0MOk (ORCPT ); Tue, 27 Aug 2019 08:14:40 -0400 Received: by mail-pf1-f196.google.com with SMTP id o70so14014837pfg.5 for ; Tue, 27 Aug 2019 05:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=txPasp1wzNBQGWPXENBmgM/OMI6t6T6Qqvvtan2Z3Gs=; b=hccm/k4BT6LsSDKcZ7iWMQe5ikVb9f2HaL9Zxp8U+ENditovQoGgf7xJxZt8bcUX+b /tZFFzoSb/Opj7lG41EVMTiVk3o6awWJKG8f/yIqR7ZS1LnbAmAA46ONjbycW4jayWuN Agz5GNuPAx2YQbhBVwFm9ZQNEXs1yU9Pk6h3QPGpJbmkKr7IGmUztr+4tecwrWN+qxc9 RK+pjRTyWTa9CBNqKC+5BdTkAYDoIQCztH++Z4gIeqAu+lse5FwnuzW11esiXk6kWMwS gqKqgiQUKJzD6a+JXsbvGuxVl3cWkZrLO0PkcmeFQ92W3W3eBDO1haebMkIidfLiP0M5 UgDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=txPasp1wzNBQGWPXENBmgM/OMI6t6T6Qqvvtan2Z3Gs=; b=AhEd9cs8JziIvUm3cQTyRxz22dkBeA+5CstkA3AApRxCr0U3SmkKNGVwJtCklOGDIz oWlsT5F5sYskvZn0qnESYKPXapjYQmv08ECz9LobiB7+SnnxcKu35Z369jZ/eKyCLSIr Zv6CdyFuoVMMySefUHklBUixVbpI6YSQOhQafYhGkhZfx5MgdQYxcryKWZqaw/8aqmCP 628Pf8VUKeBa9PsmbDbGnU84wyd8ol7KKbkT1bxj9hJBNaIl1+OUhjzApkA76C8oj9To Ss0z70QYBax429FLzegU2S0K3ct/ln5+K/UAjLg7eeTnh0R8SHKFtd4p+fIuYa/GjEfl 2vLQ== X-Gm-Message-State: APjAAAXXsfz3JwXY6qWuBWyg2YoMH7v6y/mGMw6BdDIpNOUk8vVDWutI bg70zPmrR264Ub+p5RWwTHn5fw== X-Received: by 2002:a63:5d54:: with SMTP id o20mr21212194pgm.413.1566908079872; Tue, 27 Aug 2019 05:14:39 -0700 (PDT) Received: from localhost ([49.248.54.193]) by smtp.gmail.com with ESMTPSA id y10sm2584243pjp.27.2019.08.27.05.14.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Aug 2019 05:14:39 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, agross@kernel.org, sboyd@kernel.org, masneyb@onstation.org, marc.w.gonzalez@free.fr, Daniel Lezcano , Mark Rutland , Rob Herring , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCH v2 04/15] drivers: thermal: tsens: Add debugfs support Date: Tue, 27 Aug 2019 17:44:00 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Dump some basic version info and sensor details into debugfs. Example from qcs404 below: --(/sys/kernel/debug) $ ls tsens/ 4a9000.thermal-sensor version --(/sys/kernel/debug) $ cat tsens/version 1.4.0 --(/sys/kernel/debug) $ cat tsens/4a9000.thermal-sensor/sensors max: 11 num: 10 id slope offset ------------------------ 0 3200 404000 1 3200 404000 2 3200 404000 3 3200 404000 4 3200 404000 5 3200 404000 6 3200 404000 7 3200 404000 8 3200 404000 9 3200 404000 Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 83 +++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 + drivers/thermal/qcom/tsens.h | 6 +++ 3 files changed, 91 insertions(+) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 7437bfe196e50..ea2c46cc6a66a 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -139,6 +140,77 @@ int get_temp_common(struct tsens_sensor *s, int *temp) return 0; } +#ifdef CONFIG_DEBUG_FS +static int dbg_sensors_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + int i; + + seq_printf(s, "max: %2d\nnum: %2d\n\n", + priv->feat->max_sensors, priv->num_sensors); + + seq_puts(s, " id slope offset\n--------------------------\n"); + for (i = 0; i < priv->num_sensors; i++) { + seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id, + priv->sensor[i].slope, priv->sensor[i].offset); + } + + return 0; +} + +static int dbg_version_show(struct seq_file *s, void *data) +{ + struct platform_device *pdev = s->private; + struct tsens_priv *priv = platform_get_drvdata(pdev); + u32 maj_ver, min_ver, step_ver; + int ret; + + if (tsens_ver(priv) > VER_0_1) { + ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[VER_STEP], &step_ver); + if (ret) + return ret; + seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); + } else { + seq_puts(s, "0.1.0\n"); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(dbg_version); +DEFINE_SHOW_ATTRIBUTE(dbg_sensors); + +static void tsens_debug_init(struct platform_device *pdev) +{ + struct tsens_priv *priv = platform_get_drvdata(pdev); + struct dentry *root, *file; + + root = debugfs_lookup("tsens", NULL); + if (!root) + priv->debug_root = debugfs_create_dir("tsens", NULL); + else + priv->debug_root = root; + + file = debugfs_lookup("version", priv->debug_root); + if (!file) + debugfs_create_file("version", 0444, priv->debug_root, + pdev, &dbg_version_fops); + + /* A directory for each instance of the TSENS IP */ + priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); + debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); +} +#else +static inline void tsens_debug_init(struct platform_device *pdev) {} +#endif + static const struct regmap_config tsens_config = { .name = "tm", .reg_bits = 32, @@ -199,6 +271,15 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + if (tsens_ver(priv) > VER_0_1) { + for (i = VER_MAJOR; i <= VER_STEP; i++) { + priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[i]); + if (IS_ERR(priv->rf[i])) + return PTR_ERR(priv->rf[i]); + } + } + priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_EN]); if (IS_ERR(priv->rf[TSENS_EN])) { @@ -238,6 +319,8 @@ int __init init_common(struct tsens_priv *priv) } } + tsens_debug_init(op); + return 0; err_put_device: diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 06c6bbd69a1a7..772aa76b50e12 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -176,6 +177,7 @@ static int tsens_remove(struct platform_device *pdev) { struct tsens_priv *priv = platform_get_drvdata(pdev); + debugfs_remove_recursive(priv->debug_root); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index d022e726d0747..e1d6af71b2b9a 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -292,6 +292,8 @@ struct tsens_context { * @feat: features of the IP * @fields: bitfield locations * @ops: pointer to list of callbacks supported by this device + * @debug_root: pointer to debugfs dentry for all tsens + * @debug: pointer to debugfs dentry for tsens controller * @sensor: list of sensors attached to this device */ struct tsens_priv { @@ -305,6 +307,10 @@ struct tsens_priv { const struct tsens_features *feat; const struct reg_field *fields; const struct tsens_ops *ops; + + struct dentry *debug_root; + struct dentry *debug; + struct tsens_sensor sensor[0]; }; From patchwork Tue Aug 27 12:14:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172279 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5702154ily; Tue, 27 Aug 2019 05:14:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqz89H2xa4O3h0jbGJK/5/lXZjReL/Tf8jXTNwtfLWJDQdqGKe12GUhDJ55D+zdgG6jmsop0 X-Received: by 2002:a17:902:e9:: with SMTP id a96mr12172090pla.169.1566908091491; Tue, 27 Aug 2019 05:14:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908091; cv=none; d=google.com; s=arc-20160816; b=ivWDzgGVZkAyAMci7x31n3gboVltbuWAdjL6ERFYQng5LKpJDSIv+6EknsQoiVLZoH e+W5nQPIgbFCr0qNIy/p7dJhoDNz28hsfI1h9h8jr4kjTm4YLXheJ+kVwD5IRJuXAh5Q qLUs7qMDP+rE5ebqlT1UfhgGR0SvplxgNUHrfkkcv/izLLUabanm9BLwRylOSHnN2yA8 UsXikozericihxqXUFRokt6z9cmVpNBC7a1+shUnQuiXTE/QVDWwNPzPGWR4aOqG597b n3hzrvCNLVGWphC8F8TDLh4Ugb9KOpOk+mBqoF9B//NWFzQqZ/nQ7hrbHU2xi6sTg9fc iZyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=MENoYed9rPqZPrA/Y9pbBbNZ42AOAV3KIOD7B7ZsAOc=; b=aQIfn5gUVDRbIFCKRh2ia9cPgUWseqw+WNshMD9MdYgVoYS9ByaY9oea5PMkRbanxd B8XtGQKAS8nmVbrAMQEiICajbntCRtIGe0JXV8b8AUrsxv9TNW2/UyTdi4c+leDPnsWJ wZenm0jXQM/TRZbPohM7vRScEJh1+nfajon/sdUdYfZJfrFBK7JptAIdAqGTfpzz1+sj N8990utcheLZ5GzGYc54M5YSQMeVMzB42aQNLucHV1hY+vXLSP3VEdTeABmKUs8Mcvd9 KTwtxECa8oA93WOM51R56SJRc5VHfGAmZ05e4PSOKtZB3DvIUuXDcaFCS7rj4fvepCGa adFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cq7XwNmG; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Sensor 3 is NOT used. Fixup the device tree so that the correct sensor ID is used and as a result we can actually check the temperature for the cpu2_3 sensor. Signed-off-by: Amit Kucheria Reviewed-by: Daniel Lezcano --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Stephen Boyd diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87d..8686e101905cc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -179,7 +179,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 4>; + thermal-sensors = <&tsens 5>; trips { cpu0_1_alert0: trip-point@0 { @@ -209,7 +209,7 @@ polling-delay-passive = <250>; polling-delay = <1000>; - thermal-sensors = <&tsens 3>; + thermal-sensors = <&tsens 4>; trips { cpu2_3_alert0: trip-point@0 { From patchwork Tue Aug 27 12:14:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172283 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5702551ily; Tue, 27 Aug 2019 05:15:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqx52ee7M8fU/13ODd9KLeIUyyrHwfJAkmDnG4Xn3/UxITF5bP5gSDGJFG6pJ+7TqWdHdCFV X-Received: by 2002:a65:500a:: with SMTP id f10mr4769557pgo.105.1566908109995; Tue, 27 Aug 2019 05:15:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908109; cv=none; d=google.com; s=arc-20160816; b=zqhIFDE2qLGulm+mtSkp+QBPSI261kvcP9SpIKYN8Wc/AH+uYtNslEkRM4ga+DNY2p DavhY+FdbZ3WKQbj/B04jCjD4uSeL3mXKnPpr5TnqIFl7WIv8gq+vqVGl1p3Tebqb55V l+0qnLIFiYeXT8nfTkh/iN78NHcQELQ23zapeoOdU6kCoc/uR6IT0v7zVDUPrSojcgk/ A8U3Noz94ftyYW8xF8yKj0dtGrz/SC9pAJI+b6fNdRnO58wlu5GHTw8fNjB4cNUIqTe/ WvAsK218bWp+plEldBz5+DVCipzz/MD6wzcqSLJM2BiQ++EmNjGee1VkM/aq3SD3kOHJ eiFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=jsacasSdR4EmC5KykVj3gAAOQ3NwmmFKtHpE2Pab4bk=; b=dSOEPi7yKRMi33+6fEQn8mIPbR723dgJ+dSnheg59G5bVimZLj2NOkprnWQPRQS781 l29uLIpdnaBxQa5kiDq0FVFYMGH9JWBmgTloMfJTSQbKy/NAkVDkuqForxx/tlKWuwbd spWs165r2tEoHxTdd+eH2q/ro6I4XFIitZvWTannmMTHG9TxFnp++clZjJYvNMvokIJj +IzEdUMCp/s57FdDGH2eKxaGSbcCjc1ABle//Mr3gc7kH5HYNGd6ihrMEjGNdVsSIl7v 8RkpY21uH+OQMGgVgFgYEYW8f1f6GgMUAmMfkHZmfG8dWikAJL7/NzroOdfFBJkl9wSJ uFqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OQ9KIMH2; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 82 ++++++++++++++------------- 1 file changed, 42 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c13ed7aeb1e0c..1e2f77b38f2c1 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -440,8 +440,8 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -461,8 +461,8 @@ }; cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -482,8 +482,8 @@ }; cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -503,8 +503,8 @@ }; cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -524,8 +524,8 @@ }; cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -545,8 +545,8 @@ }; cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -566,8 +566,8 @@ }; cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -587,8 +587,8 @@ }; cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -608,8 +608,8 @@ }; gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -623,8 +623,8 @@ }; gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -638,8 +638,8 @@ }; clust0-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -653,8 +653,8 @@ }; clust1-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -668,8 +668,8 @@ }; cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -683,8 +683,8 @@ }; modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -698,8 +698,8 @@ }; mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -713,8 +713,8 @@ }; wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -728,8 +728,8 @@ }; q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -743,8 +743,8 @@ }; camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -758,8 +758,8 @@ }; multimedia-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -845,8 +845,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x10ab000 0x1000>, /* TM */ <0x10aa000 0x1000>; /* SROT */ - #qcom,sensors = <14>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -854,8 +855,9 @@ compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; reg = <0x10ae000 0x1000>, /* TM */ <0x10ad000 0x1000>; /* SROT */ - #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; From patchwork Tue Aug 27 12:14:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 172288 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp5703027ily; Tue, 27 Aug 2019 05:15:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZzbxGTuWGkhNtopkzXoP8wip4i2N6lCfYkNTlsZXGDoaLnO63Xpa/MvJoGDQKv1bSAHf6 X-Received: by 2002:a65:5584:: with SMTP id j4mr20832555pgs.258.1566908130028; Tue, 27 Aug 2019 05:15:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566908130; cv=none; d=google.com; s=arc-20160816; b=vBXNs9b9Zp7iClnsIZSeMogB9Hs+ZPTkGNYptn4PKjNm8m5Fn1zN9xhDGtaR0l6J3y JKhdRajGMt4jdF2I9YmKAboYb7Sw72tTFZm+ODsgQVxjOKj1aQTeD0v5O0XTHFJbcF0n 4HEkUuMATzIz/NTXg5mkIrt7QmBOZ7EyF9/C+cJ41nk5U+nBFmG07HnueiKxwdfT2M0I eFo+wwcJJd9XMO/nuoroAHbPLPZRx0sgwwqqGBghekxWDjTyMYts8iwh2ltCljjrQb7K TC9pAXGA26kZAE/uWQwYFqvr/ZDa1SN5WziQsVODu+i9pYv2sDt/mqF5VFP7ZCpvHsec V+Dg== ARC-Message-Signature: i=1; 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We only add support for upper and lower threshold interrupts for now. TSENSv2 has an irq [status|clear|mask] bit tuple for each sensor while earlier versions only have a single bit per sensor to denote status and clear. At each interrupt, we reprogram the new upper and lower threshold in the .set_trip callback. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 377 ++++++++++++++++++++++++++-- drivers/thermal/qcom/tsens-v0_1.c | 11 + drivers/thermal/qcom/tsens-v1.c | 29 +++ drivers/thermal/qcom/tsens-v2.c | 13 + drivers/thermal/qcom/tsens.c | 32 ++- drivers/thermal/qcom/tsens.h | 270 ++++++++++++++++---- 6 files changed, 669 insertions(+), 63 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 06b44cfd5eab9..c549f8e1488ba 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -13,6 +13,30 @@ #include #include "tsens.h" +/** struct tsens_irq_data - IRQ status and temperature violations + * @up_viol: upper threshold violated + * @up_thresh: upper threshold temperature value + * @up_irq_mask: mask register for upper threshold irqs + * @up_irq_clear: clear register for uppper threshold irqs + * @low_viol: lower threshold violated + * @low_thresh: lower threshold temperature value + * @low_irq_mask: mask register for lower threshold irqs + * @low_irq_clear: clear register for lower threshold irqs + * + * Structure containing data about temperature threshold settings and + * irq status if they were violated. + */ +struct tsens_irq_data { + u32 up_viol; + int up_thresh; + u32 up_irq_mask; + u32 up_irq_clear; + u32 low_viol; + int low_thresh; + u32 low_irq_mask; + u32 low_irq_clear; +}; + char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; @@ -65,6 +89,14 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1, } } +static inline u32 degc_to_code(int degc, const struct tsens_sensor *sensor) +{ + u64 code = (degc * sensor->slope + sensor->offset) / SLOPE_FACTOR; + + pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc); + return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE); +} + static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s) { int degc, num, den; @@ -114,6 +146,314 @@ static int tsens_hw_to_mC(struct tsens_sensor *s, int field) return sign_extend32(temp, priv->tempres) * 100; } +/** + * tsens_mC_to_hw - Return correct value to be written to threshold + * registers, whether in ADC code or deciCelsius depending on IP version + */ +static int tsens_mC_to_hw(struct tsens_sensor *s, int temp) +{ + struct tsens_priv *priv = s->priv; + + if (priv->feat->adc) { + /* milliC to C to adc code */ + return degc_to_code(temp / 1000, s); + } + + /* milliC to deciC */ + return temp / 100; +} + +static inline unsigned int tsens_ver(struct tsens_priv *priv) +{ + return priv->feat->ver_major; +} + +/** + * tsens_set_interrupt_v1 - Disable an interrupt (enable = false) + * Re-enable an interrupt (enable = true) + */ +static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index; + + if (enable) { + switch (irq_type) { + case UPPER: + index = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index], 0); + } else { + switch (irq_type) { + case UPPER: + index = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index], 1); + } +} + +/** + * tsens_set_interrupt_v2 - Disable an interrupt (enable = false) + * Re-enable an interrupt (enable = true) + */ +static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + u32 index_mask, index_clear; + + if (enable) { + switch (irq_type) { + case UPPER: + index_mask = UP_INT_MASK_0 + hw_id; + break; + case LOWER: + index_mask = LOW_INT_MASK_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index_mask], 0); + } else { + /* To disable the interrupt flag for a sensor: + * 1. Mask further interrupts for this sensor + * 2. Write 1 followed by 0 to clear the interrupt + */ + switch (irq_type) { + case UPPER: + index_mask = UP_INT_MASK_0 + hw_id; + index_clear = UP_INT_CLEAR_0 + hw_id; + break; + case LOWER: + index_mask = LOW_INT_MASK_0 + hw_id; + index_clear = LOW_INT_CLEAR_0 + hw_id; + break; + } + regmap_field_write(priv->rf[index_mask], 1); + regmap_field_write(priv->rf[index_clear], 1); + regmap_field_write(priv->rf[index_clear], 0); + } +} + +/** + * tsens_set_interrupt - Disable an interrupt (enable = false) + * Re-enable an interrupt (enable = true) + */ +static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id, + enum tsens_irq_type irq_type, bool enable) +{ + dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__, + irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW", + enable ? "en" : "dis"); + if (tsens_ver(priv) > VER_1_X) + tsens_set_interrupt_v2(priv, hw_id, irq_type, enable); + else + tsens_set_interrupt_v1(priv, hw_id, irq_type, enable); +} + +/** + * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold + * + * Return: 0 if threshold was not violated, 1 if it was violated and negative + * errno in case of errors + */ +static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id, + struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol); + if (ret) + return ret; + if (d->up_viol || d->low_viol) + return 1; + + return 0; +} + +static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id, + struct tsens_sensor *s, struct tsens_irq_data *d) +{ + int ret; + + ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear); + if (ret) + return ret; + if (tsens_ver(priv) > VER_1_X) { + ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask); + if (ret) + return ret; + ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask); + if (ret) + return ret; + } else { + /* No mask register on older TSENS */ + d->up_irq_mask = 0; + d->low_irq_mask = 0; + } + + d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id); + d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id); + + dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u) | clr(%u|%u) | mask(%u|%u)\n", + hw_id, __func__, (d->up_viol || d->low_viol) ? "(V)" : "", + d->low_viol, d->up_viol, d->low_irq_clear, d->up_irq_clear, + d->low_irq_mask, d->up_irq_mask); + dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d)\n", hw_id, __func__, + (d->up_viol || d->low_viol) ? "(violation)" : "", + d->low_thresh, d->up_thresh); + + return 0; +} + +static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver) +{ + if (ver > VER_1_X) + return mask & (1 << hw_id); + + /* v1, v0.1 don't have a irq mask register */ + return 0; +} + +irqreturn_t tsens_irq_thread(int irq, void *data) +{ + struct tsens_priv *priv = data; + struct tsens_irq_data d; + bool enable = true, disable = false; + unsigned long flags; + int temp, ret, i; + + /* + * Check if any sensor raised an IRQ - for each sensor connected to the + * TSENS block if it set the threshold violation bit. + */ + for (i = 0; i < priv->num_sensors; i++) { + bool trigger = 0; + struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + + if (IS_ERR(priv->sensor[i].tzd)) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; + ret = get_temp_tsens_valid(s, &temp); + if (ret) { + dev_err(priv->dev, "[%u] %s: error reading sensor\n", hw_id, __func__); + continue; + } + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + if (d.up_viol && + !masked_irq(hw_id, d.up_irq_mask, tsens_ver(priv))) { + tsens_set_interrupt(priv, hw_id, UPPER, disable); + if (d.up_thresh > temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm upper\n", + priv->sensor[i].hw_id, __func__); + /* unmask the interrupt for this sensor */ + tsens_set_interrupt(priv, hw_id, UPPER, enable); + } else { + trigger = 1; + /* Keep irq masked */ + } + } else if (d.low_viol && + !masked_irq(hw_id, d.low_irq_mask, tsens_ver(priv))) { + tsens_set_interrupt(priv, hw_id, LOWER, disable); + if (d.low_thresh < temp) { + dev_dbg(priv->dev, "[%u] %s: re-arm low\n", + priv->sensor[i].hw_id, __func__); + /* unmask the interrupt for this sensor */ + tsens_set_interrupt(priv, hw_id, LOWER, enable); + } else { + trigger = 1; + /* Keep irq masked */ + } + } + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + if (trigger) { + dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n", + hw_id, __func__, temp); + thermal_zone_device_update(priv->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } else { + dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", + hw_id, __func__, temp); + } + } + + return IRQ_HANDLED; +} + +int tsens_set_trips(void *_sensor, int low, int high) +{ + struct tsens_sensor *s = _sensor; + struct tsens_priv *priv = s->priv; + struct device *dev = priv->dev; + struct tsens_irq_data d; + unsigned long flags; + int high_val, low_val, cl_high, cl_low; + bool enable = true; + u32 hw_id = s->hw_id; + + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", + hw_id, __func__, low, high); + + cl_high = clamp_val(high, -40000, 120000); + cl_low = clamp_val(low, -40000, 120000); + + high_val = tsens_mC_to_hw(s, cl_high); + low_val = tsens_mC_to_hw(s, cl_low); + + spin_lock_irqsave(&priv->ul_lock, flags); + + tsens_read_irq_state(priv, hw_id, s, &d); + + /* Write the new thresholds and clear the status */ + regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val); + regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val); + tsens_set_interrupt(priv, hw_id, LOWER, enable); + tsens_set_interrupt(priv, hw_id, UPPER, enable); + + spin_unlock_irqrestore(&priv->ul_lock, flags); + + dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n", + s->hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high); + + return 0; +} + +int tsens_enable_irq(struct tsens_priv *priv) +{ + int ret; + int val = tsens_ver(priv) > VER_1_X ? 7 : 1; + + ret = regmap_field_write(priv->rf[INT_EN], val); + if (ret < 0) + dev_err(priv->dev, "%s: failed to enable interrupts\n", __func__); + + return ret; +} + +void tsens_disable_irq(struct tsens_priv *priv) +{ + regmap_field_write(priv->rf[INT_EN], 0); +} + int get_temp_tsens_valid(struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; @@ -319,28 +659,31 @@ int __init init_common(struct tsens_priv *priv) ret = PTR_ERR(priv->rf[SENSOR_EN]); goto err_put_device; } - /* now alloc regmap_fields in tm_map */ - for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; - } + priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[INT_EN]); + if (IS_ERR(priv->rf[INT_EN])) { + ret = PTR_ERR(priv->rf[INT_EN]); + goto err_put_device; } - /* Save away resolution of signed temperature value for this IP */ - priv->tempres = priv->fields[LAST_TEMP_0].msb - priv->fields[LAST_TEMP_0].lsb; - - for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) { - priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map, - priv->fields[j]); - if (IS_ERR(priv->rf[j])) { - ret = PTR_ERR(priv->rf[j]); - goto err_put_device; + /* This loop might need changes if enum regfield_ids is reordered */ + for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { + int idx = j + i; + + priv->rf[idx] = devm_regmap_field_alloc(dev, priv->tm_map, + priv->fields[idx]); + if (IS_ERR(priv->rf[idx])) { + ret = PTR_ERR(priv->rf[idx]); + goto err_put_device; + } } } + /* Save away resolution of signed temperature value for this IP */ + priv->tempres = priv->fields[LAST_TEMP_0].msb - priv->fields[LAST_TEMP_0].lsb; + spin_lock_init(&priv->ul_lock); + tsens_enable_irq(priv); tsens_debug_init(op); return 0; diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6f26fadf4c279..a267b66e61d6b 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -339,9 +339,20 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + + /* NO CRITICAL INTERRUPT SUPPORT on v0.1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), /* No VALID field on v0.1 */ + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 10b595d4f6199..86259c9821be8 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -17,6 +17,8 @@ #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 #define TM_Sn_STATUS_OFF 0x0044 #define TM_TRDY_OFF 0x0084 +#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 +#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 @@ -167,9 +169,36 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* INTERRUPT ENABLE */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + /* UPPER/LOWER TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + + /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ + REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), + [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), + [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), + [LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3), + [LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4), + [LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5), + [LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6), + [LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7), + [UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8), + [UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9), + [UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10), + [UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11), + [UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12), + [UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13), + [UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14), + [UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15), + + /* NO CRITICAL INTERRUPT SUPPORT on v1 */ + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 0a4f2b8fcab6c..a4d15e1abfddd 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -50,9 +50,22 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */ [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2), + /* TEMPERATURE THRESHOLDS */ + REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11), + REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23), + + /* INTERRUPTS [CLEAR/STATUS/MASK] */ + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF), + REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF), + /* Sn_STATUS */ REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11), REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21), + /* xxx_STATUS bits: 1 == threshold violated */ REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16), REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17), REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18), diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 772aa76b50e12..a4335717aeede 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -78,12 +79,14 @@ MODULE_DEVICE_TABLE(of, tsens_table); static const struct thermal_zone_of_device_ops tsens_of_ops = { .get_temp = tsens_get_temp, .get_trend = tsens_get_trend, + .set_trips = tsens_set_trips, }; static int tsens_register(struct tsens_priv *priv) { - int i; + int i, ret, irq; struct thermal_zone_device *tzd; + struct platform_device *pdev; for (i = 0; i < priv->num_sensors; i++) { priv->sensor[i].priv = priv; @@ -96,7 +99,33 @@ static int tsens_register(struct tsens_priv *priv) if (priv->ops->enable) priv->ops->enable(priv, i); } + + pdev = of_find_device_by_node(priv->dev->of_node); + if (!pdev) { + dev_err(&pdev->dev, "%s: device node not found in DT\n", __func__); + return -ENODEV; + } + + irq = platform_get_irq_byname(pdev, "uplow"); + if (irq < 0) { + dev_err(&pdev->dev, "%s: missing irq in dt: uplow\n", __func__); + return irq; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, tsens_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "%s: failed to get irq\n", __func__); + goto err_put_device; + } + enable_irq_wake(irq); return 0; + +err_put_device: + put_device(&pdev->dev); + return ret; } static int tsens_probe(struct platform_device *pdev) @@ -178,6 +207,7 @@ static int tsens_remove(struct platform_device *pdev) struct tsens_priv *priv = platform_get_drvdata(pdev); debugfs_remove_recursive(priv->debug_root); + tsens_disable_irq(priv); if (priv->ops->disable) priv->ops->disable(priv); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 409395e436f32..b960c77168347 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -13,8 +13,10 @@ #define CAL_DEGC_PT2 120 #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 +#define THRESHOLD_MAX_ADC_CODE 0x3ff +#define THRESHOLD_MIN_ADC_CODE 0x0 - +#include #include #include @@ -26,6 +28,11 @@ enum tsens_ver { VER_2_X, }; +enum tsens_irq_type { + LOWER, + UPPER, +}; + /** * struct tsens_sensor - data for each sensor connected to the tsens device * @priv: tsens device instance that this sensor is connected to @@ -99,22 +106,66 @@ struct tsens_ops { [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) -/* reg_field IDs to use as an index into an array */ +#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 0, 0), \ + [_name##_##1] = REG_FIELD(_offset, 1, 1), \ + [_name##_##2] = REG_FIELD(_offset, 2, 2), \ + [_name##_##3] = REG_FIELD(_offset, 3, 3), \ + [_name##_##4] = REG_FIELD(_offset, 4, 4), \ + [_name##_##5] = REG_FIELD(_offset, 5, 5), \ + [_name##_##6] = REG_FIELD(_offset, 6, 6), \ + [_name##_##7] = REG_FIELD(_offset, 7, 7), \ + [_name##_##8] = REG_FIELD(_offset, 8, 8), \ + [_name##_##9] = REG_FIELD(_offset, 9, 9), \ + [_name##_##10] = REG_FIELD(_offset, 10, 10), \ + [_name##_##11] = REG_FIELD(_offset, 11, 11), \ + [_name##_##12] = REG_FIELD(_offset, 12, 12), \ + [_name##_##13] = REG_FIELD(_offset, 13, 13), \ + [_name##_##14] = REG_FIELD(_offset, 14, 14), \ + [_name##_##15] = REG_FIELD(_offset, 15, 15) + +#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ + [_name##_##0] = REG_FIELD(_offset, 16, 16), \ + [_name##_##1] = REG_FIELD(_offset, 17, 17), \ + [_name##_##2] = REG_FIELD(_offset, 18, 18), \ + [_name##_##3] = REG_FIELD(_offset, 19, 19), \ + [_name##_##4] = REG_FIELD(_offset, 20, 20), \ + [_name##_##5] = REG_FIELD(_offset, 21, 21), \ + [_name##_##6] = REG_FIELD(_offset, 22, 22), \ + [_name##_##7] = REG_FIELD(_offset, 23, 23), \ + [_name##_##8] = REG_FIELD(_offset, 24, 24), \ + [_name##_##9] = REG_FIELD(_offset, 25, 25), \ + [_name##_##10] = REG_FIELD(_offset, 26, 26), \ + [_name##_##11] = REG_FIELD(_offset, 27, 27), \ + [_name##_##12] = REG_FIELD(_offset, 28, 28), \ + [_name##_##13] = REG_FIELD(_offset, 29, 29), \ + [_name##_##14] = REG_FIELD(_offset, 30, 30), \ + [_name##_##15] = REG_FIELD(_offset, 31, 31) + +/* + * reg_field IDs to use as an index into an array + * If you change the order of the entries, check the devm_regmap_field_alloc() + * calls in init_common() + */ enum regfield_ids { /* ----- SROT ------ */ /* HW_VER */ - VER_MAJOR = 0, + VER_MAJOR, VER_MINOR, VER_STEP, /* CTRL_OFFSET */ - TSENS_EN = 3, + TSENS_EN, TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, /* ----- TM ------ */ + /* TRDY */ + TRDY, + /* INTERRUPT ENABLE */ + INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ /* STATUS */ - LAST_TEMP_0 = 7, /* Last temperature reading */ + LAST_TEMP_0, /* Last temperature reading */ LAST_TEMP_1, LAST_TEMP_2, LAST_TEMP_3, @@ -130,7 +181,7 @@ enum regfield_ids { LAST_TEMP_13, LAST_TEMP_14, LAST_TEMP_15, - VALID_0 = 23, /* VALID reading or not */ + VALID_0, /* VALID reading or not */ VALID_1, VALID_2, VALID_3, @@ -146,38 +197,6 @@ enum regfield_ids { VALID_13, VALID_14, VALID_15, - MIN_STATUS_0, /* MIN threshold violated */ - MIN_STATUS_1, - MIN_STATUS_2, - MIN_STATUS_3, - MIN_STATUS_4, - MIN_STATUS_5, - MIN_STATUS_6, - MIN_STATUS_7, - MIN_STATUS_8, - MIN_STATUS_9, - MIN_STATUS_10, - MIN_STATUS_11, - MIN_STATUS_12, - MIN_STATUS_13, - MIN_STATUS_14, - MIN_STATUS_15, - MAX_STATUS_0, /* MAX threshold violated */ - MAX_STATUS_1, - MAX_STATUS_2, - MAX_STATUS_3, - MAX_STATUS_4, - MAX_STATUS_5, - MAX_STATUS_6, - MAX_STATUS_7, - MAX_STATUS_8, - MAX_STATUS_9, - MAX_STATUS_10, - MAX_STATUS_11, - MAX_STATUS_12, - MAX_STATUS_13, - MAX_STATUS_14, - MAX_STATUS_15, LOWER_STATUS_0, /* LOWER threshold violated */ LOWER_STATUS_1, LOWER_STATUS_2, @@ -194,6 +213,70 @@ enum regfield_ids { LOWER_STATUS_13, LOWER_STATUS_14, LOWER_STATUS_15, + LOW_INT_STATUS_0, /* LOWER interrupt status */ + LOW_INT_STATUS_1, + LOW_INT_STATUS_2, + LOW_INT_STATUS_3, + LOW_INT_STATUS_4, + LOW_INT_STATUS_5, + LOW_INT_STATUS_6, + LOW_INT_STATUS_7, + LOW_INT_STATUS_8, + LOW_INT_STATUS_9, + LOW_INT_STATUS_10, + LOW_INT_STATUS_11, + LOW_INT_STATUS_12, + LOW_INT_STATUS_13, + LOW_INT_STATUS_14, + LOW_INT_STATUS_15, + LOW_INT_CLEAR_0, /* LOWER interrupt clear */ + LOW_INT_CLEAR_1, + LOW_INT_CLEAR_2, + LOW_INT_CLEAR_3, + LOW_INT_CLEAR_4, + LOW_INT_CLEAR_5, + LOW_INT_CLEAR_6, + LOW_INT_CLEAR_7, + LOW_INT_CLEAR_8, + LOW_INT_CLEAR_9, + LOW_INT_CLEAR_10, + LOW_INT_CLEAR_11, + LOW_INT_CLEAR_12, + LOW_INT_CLEAR_13, + LOW_INT_CLEAR_14, + LOW_INT_CLEAR_15, + LOW_INT_MASK_0, /* LOWER interrupt mask */ + LOW_INT_MASK_1, + LOW_INT_MASK_2, + LOW_INT_MASK_3, + LOW_INT_MASK_4, + LOW_INT_MASK_5, + LOW_INT_MASK_6, + LOW_INT_MASK_7, + LOW_INT_MASK_8, + LOW_INT_MASK_9, + LOW_INT_MASK_10, + LOW_INT_MASK_11, + LOW_INT_MASK_12, + LOW_INT_MASK_13, + LOW_INT_MASK_14, + LOW_INT_MASK_15, + LOW_THRESH_0, /* LOWER threshold values */ + LOW_THRESH_1, + LOW_THRESH_2, + LOW_THRESH_3, + LOW_THRESH_4, + LOW_THRESH_5, + LOW_THRESH_6, + LOW_THRESH_7, + LOW_THRESH_8, + LOW_THRESH_9, + LOW_THRESH_10, + LOW_THRESH_11, + LOW_THRESH_12, + LOW_THRESH_13, + LOW_THRESH_14, + LOW_THRESH_15, UPPER_STATUS_0, /* UPPER threshold violated */ UPPER_STATUS_1, UPPER_STATUS_2, @@ -210,6 +293,70 @@ enum regfield_ids { UPPER_STATUS_13, UPPER_STATUS_14, UPPER_STATUS_15, + UP_INT_STATUS_0, /* UPPER interrupt status */ + UP_INT_STATUS_1, + UP_INT_STATUS_2, + UP_INT_STATUS_3, + UP_INT_STATUS_4, + UP_INT_STATUS_5, + UP_INT_STATUS_6, + UP_INT_STATUS_7, + UP_INT_STATUS_8, + UP_INT_STATUS_9, + UP_INT_STATUS_10, + UP_INT_STATUS_11, + UP_INT_STATUS_12, + UP_INT_STATUS_13, + UP_INT_STATUS_14, + UP_INT_STATUS_15, + UP_INT_CLEAR_0, /* UPPER interrupt clear */ + UP_INT_CLEAR_1, + UP_INT_CLEAR_2, + UP_INT_CLEAR_3, + UP_INT_CLEAR_4, + UP_INT_CLEAR_5, + UP_INT_CLEAR_6, + UP_INT_CLEAR_7, + UP_INT_CLEAR_8, + UP_INT_CLEAR_9, + UP_INT_CLEAR_10, + UP_INT_CLEAR_11, + UP_INT_CLEAR_12, + UP_INT_CLEAR_13, + UP_INT_CLEAR_14, + UP_INT_CLEAR_15, + UP_INT_MASK_0, /* UPPER interrupt mask */ + UP_INT_MASK_1, + UP_INT_MASK_2, + UP_INT_MASK_3, + UP_INT_MASK_4, + UP_INT_MASK_5, + UP_INT_MASK_6, + UP_INT_MASK_7, + UP_INT_MASK_8, + UP_INT_MASK_9, + UP_INT_MASK_10, + UP_INT_MASK_11, + UP_INT_MASK_12, + UP_INT_MASK_13, + UP_INT_MASK_14, + UP_INT_MASK_15, + UP_THRESH_0, /* UPPER threshold values */ + UP_THRESH_1, + UP_THRESH_2, + UP_THRESH_3, + UP_THRESH_4, + UP_THRESH_5, + UP_THRESH_6, + UP_THRESH_7, + UP_THRESH_8, + UP_THRESH_9, + UP_THRESH_10, + UP_THRESH_11, + UP_THRESH_12, + UP_THRESH_13, + UP_THRESH_14, + UP_THRESH_15, CRITICAL_STATUS_0, /* CRITICAL threshold violated */ CRITICAL_STATUS_1, CRITICAL_STATUS_2, @@ -226,13 +373,38 @@ enum regfield_ids { CRITICAL_STATUS_13, CRITICAL_STATUS_14, CRITICAL_STATUS_15, - /* TRDY */ - TRDY, - /* INTERRUPT ENABLE */ - INT_EN, /* Pre-V1, V1.x */ - LOW_INT_EN, /* V2.x */ - UP_INT_EN, /* V2.x */ - CRIT_INT_EN, /* V2.x */ + MIN_STATUS_0, /* MIN threshold violated */ + MIN_STATUS_1, + MIN_STATUS_2, + MIN_STATUS_3, + MIN_STATUS_4, + MIN_STATUS_5, + MIN_STATUS_6, + MIN_STATUS_7, + MIN_STATUS_8, + MIN_STATUS_9, + MIN_STATUS_10, + MIN_STATUS_11, + MIN_STATUS_12, + MIN_STATUS_13, + MIN_STATUS_14, + MIN_STATUS_15, + MAX_STATUS_0, /* MAX threshold violated */ + MAX_STATUS_1, + MAX_STATUS_2, + MAX_STATUS_3, + MAX_STATUS_4, + MAX_STATUS_5, + MAX_STATUS_6, + MAX_STATUS_7, + MAX_STATUS_8, + MAX_STATUS_9, + MAX_STATUS_10, + MAX_STATUS_11, + MAX_STATUS_12, + MAX_STATUS_13, + MAX_STATUS_14, + MAX_STATUS_15, /* Keep last */ MAX_REGFIELDS @@ -304,6 +476,10 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + + /* lock for upper/lower threshold interrupts */ + spinlock_t ul_lock; + struct regmap_field *rf[MAX_REGFIELDS]; struct tsens_context ctx; const struct tsens_features *feat; @@ -321,6 +497,10 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(struct tsens_sensor *s, int *temp); int get_temp_common(struct tsens_sensor *s, int *temp); +int tsens_enable_irq(struct tsens_priv *priv); +void tsens_disable_irq(struct tsens_priv *priv); +int tsens_set_trips(void *_sensor, int low, int high); +irqreturn_t tsens_irq_thread(int irq, void *data); /* TSENS target */ extern const struct tsens_plat_data data_8960;