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Mon, 11 Dec 2023 13:20:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 01/24] exec: Include 'cpu.h' before validating CPUArchState placement Date: Mon, 11 Dec 2023 22:19:38 +0100 Message-ID: <20231211212003.21686-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUArchState 'env' field is defined within the ArchCPU structure, so we need to include each target "cpu.h" header which defines it. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Warner Losh Reviewed-by: Warner Losh --- include/exec/cpu-all.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5340907cfd..9a7b5737d3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -411,10 +411,6 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); -/* Validate correct placement of CPUArchState. */ -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); - /** * env_archcpu(env) * @env: The architecture environment @@ -437,4 +433,9 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } +/* Validate correct placement of CPUArchState. */ +#include "cpu.h" +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); + #endif /* CPU_ALL_H */ From patchwork Mon Dec 11 21:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752531 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1547409wrs; Mon, 11 Dec 2023 13:23:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IGUl5QcaDSrjVFSSI706nsUopps+f7VeqbpsmDhKfBkDRg6wHPMW34yLkCb2lmjkd1+9FcT X-Received: by 2002:ac8:5942:0:b0:419:8f42:8c45 with SMTP id 2-20020ac85942000000b004198f428c45mr6850955qtz.8.1702329826209; Mon, 11 Dec 2023 13:23:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329826; cv=none; d=google.com; s=arc-20160816; b=GjUH+prI6IJWgnoGpL91fdFc8HN4twqQVgCn1k0HFL+K27r3beZHmuX6fUvdOVRM0Z Mhp4O9wREcL+G5M4xgVXnVA7lV7/u2F7W0lxaHefeKQdK6E3uzqHbzJMLRIAqnHRmaia lv2vcEdQ9m2UdkM2bR7tWAhTrLOiISznmaoHzodCjEjiXqU9nbUPo2ZJSkmLWwOFtnWf GRDGC7/dzPmnxECuGNAoyhw3mGYNskGRk4tv4X35pnk/5exx14c/UuaXUBlNizLQXXeA aT3hm+wNvYvOAsiRGpeJkX7/hc2tyc8SFD8aoX4se9m9WczxIaiFFEs1U6RcIjd5J4+S oNxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wgiAOK8BuLaD0cXDs62KfIAvV8sc/YA5HaZCqiUDiy0=; fh=jr6BeAjRBF2hKKiijQk6ZwQLKxSmFaSzke8XrKLKGCU=; b=Zch2icSN9DxeeRUAr+y7sX0a1xFK1Xap8guUCKVUPHde1+TUAFRDKrx7gVULVYlKKG Pj9r/BYL8qJbank40wrdaR473Egqo3z2aAAJV3wD/Ep4wtUgZaqkYAayfVL2E5so2MtI Uccm5L+dpPhaY4Wgc5j8r1QGrMQeV93JVc+AuydXQGd2JqiiDBAh37+BxGSfDo2FGg4V 4MCERG/2QW3RFsWrboBca2AzKaHIV15HVPT2waudEMxcaBZyOUAI2netB13tmAqhEM5H n5OliwElcwPDwNXyDTuO8lJYI6sRHLiERl9UMv2WWU96HMD6zJCxHO79naa3XolFq6RL cbfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MmvNvQ1d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:20:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc?= =?utf-8?q?-Andr=C3=A9_Lureau?= Subject: [PATCH 02/24] exec: Expose 'target_page.h' API to user emulation Date: Mon, 11 Dec 2023 22:19:39 +0100 Message-ID: <20231211212003.21686-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org User-only objects might benefit from the "exec/target_page.h" API, which allows to build some objects once for all targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- meson.build | 2 +- page-target.c | 43 +++++++++++++++++++++++++++++++++++++++++++ system/physmem.c | 35 ----------------------------------- 3 files changed, 44 insertions(+), 36 deletions(-) create mode 100644 page-target.c diff --git a/meson.build b/meson.build index d2c4c2adb3..5fdc4ef8db 100644 --- a/meson.build +++ b/meson.build @@ -3488,7 +3488,7 @@ if get_option('b_lto') pagevary = declare_dependency(link_with: pagevary) endif common_ss.add(pagevary) -specific_ss.add(files('page-vary-target.c')) +specific_ss.add(files('page-target.c', 'page-vary-target.c')) subdir('backends') subdir('disas') diff --git a/page-target.c b/page-target.c new file mode 100644 index 0000000000..d286e2d58b --- /dev/null +++ b/page-target.c @@ -0,0 +1,43 @@ +/* + * QEMU page values getters (target independent) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "exec/target_page.h" +#include "exec/cpu-defs.h" +#include "exec/cpu-all.h" + +size_t qemu_target_page_size(void) +{ + return TARGET_PAGE_SIZE; +} + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} + +int qemu_target_page_bits(void) +{ + return TARGET_PAGE_BITS; +} + +int qemu_target_page_bits_min(void) +{ + return TARGET_PAGE_BITS_MIN; +} + +/* Convert target pages to MiB (2**20). */ +size_t qemu_target_pages_to_MiB(size_t pages) +{ + int page_bits = TARGET_PAGE_BITS; + + /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ + g_assert(page_bits < 20); + + return pages >> (20 - page_bits); +} diff --git a/system/physmem.c b/system/physmem.c index a63853a7bc..4bdb3d0592 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3422,41 +3422,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, return 0; } -/* - * Allows code that needs to deal with migration bitmaps etc to still be built - * target independent. - */ -size_t qemu_target_page_size(void) -{ - return TARGET_PAGE_SIZE; -} - -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - -int qemu_target_page_bits(void) -{ - return TARGET_PAGE_BITS; -} - -int qemu_target_page_bits_min(void) -{ - return TARGET_PAGE_BITS_MIN; -} - -/* Convert target pages to MiB (2**20). */ -size_t qemu_target_pages_to_MiB(size_t pages) -{ - int page_bits = TARGET_PAGE_BITS; - - /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ - g_assert(page_bits < 20); - - return pages >> (20 - page_bits); -} - bool cpu_physical_memory_is_io(hwaddr phys_addr) { MemoryRegion*mr; From patchwork Mon Dec 11 21:19:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752526 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1546318wrs; Mon, 11 Dec 2023 13:21:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IH1SR7D5FrWWVO3GPVbsffFc2WTOZPqIcJa2dNe9XjFwHbzX8vrpolbOzEDcoRKTev0FxGV X-Received: by 2002:a05:620a:19a4:b0:77d:98bc:fd7e with SMTP id bm36-20020a05620a19a400b0077d98bcfd7emr6035659qkb.50.1702329678183; Mon, 11 Dec 2023 13:21:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329678; cv=none; d=google.com; s=arc-20160816; b=yLKgvAHk74Rfi174Hh+RMuOdPg8Gq4DSR9ozsF7CUTjpJTL/zJNUnt54awMK8LuO7e SzapWKhweJzomIxJj4w9phn2ufJHL2V3ikxbe6626RyRYMRf04aP9L20rgcRQ5tVAr3y 4BDRk37CjoKcHjRgTdCawoJo1DL62F2cX2XiRSPCyxvqDiE15yjMuXTjHkXlHk3pgUx5 CgRRjuXDNf26VBvjs9tfO3+RKlW6RfoWhVOvAPI5EKtpMhjM62ZSU6vcqrUaZaB+Wzx2 mlsLygtJlsL5Ej58obSAX9iA3c6QsFGYUGo+WSsh4zFH9rcX+nGmg2JGq2UcdgpbZ5q4 v5Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LE+pAT5eOraZQypD/hJ2MWwgMdewzhE5rLiStCzLeZU=; fh=maUM8bI93AUwqA1DXvK6kYzdDa5LpS5xH/i8BcETBKw=; b=wsETn+eklI5jGydR6WBQpiBJ+dpFB0o8+d2ay3I517+B7FoGgHF17X1Ru3UhWvdGFz GsRuxbktDkOVdf+6XNL1f/rI1stc4W2rNlSWOTcEZ8WRYbyWromAQR4U7e+p27C4FU10 8ptyRN6ilOTeopmQfYFKtM+CB/30/mC2i10ZwT4PFI+RvCyjn/RQQ90J27ihk9daexJ+ etyfHRJJZhDoj2acSFXqPVGjKJEmH4HxAeOxfGcrBh1nc8FcEFq0pXWUhMC2TGg7v9mJ xvVeciCkne33sBYEKgFVU/fVqHpRRYdKoUSkhyGg70KqBro50ZMBHXFs4VWZhaP4Js/H AfvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxntjrcK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Artyom Tarasenko , Max Filippov Subject: [PATCH 03/24] target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h' Date: Mon, 11 Dec 2023 22:19:40 +0100 Message-ID: <20231211212003.21686-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Nicholas Piggin (ppc) --- target/alpha/cpu-param.h | 3 +++ target/alpha/cpu.h | 3 --- target/arm/cpu-param.h | 8 +++++--- target/arm/cpu.h | 3 --- target/avr/cpu-param.h | 2 ++ target/avr/cpu.h | 2 -- target/hppa/cpu-param.h | 6 ++++++ target/hppa/cpu.h | 6 ------ target/i386/cpu-param.h | 3 +++ target/i386/cpu.h | 3 --- target/loongarch/cpu-param.h | 2 ++ target/loongarch/cpu.h | 2 -- target/microblaze/cpu-param.h | 3 +++ target/microblaze/cpu.h | 3 --- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/ppc/cpu-param.h | 2 ++ target/ppc/cpu.h | 2 -- target/riscv/cpu-param.h | 2 ++ target/riscv/cpu.h | 2 -- target/s390x/cpu-param.h | 6 ++++++ target/s390x/cpu.h | 3 --- target/sparc/cpu-param.h | 23 +++++++++++++++++++++++ target/sparc/cpu.h | 23 ----------------------- target/xtensa/cpu-param.h | 3 +++ target/xtensa/cpu.h | 3 --- 28 files changed, 64 insertions(+), 62 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 68c46f7998..419e454702 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -15,4 +15,7 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 44 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +/* Alpha processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d672e911dd..5d9aa09ed9 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index f9b462a98f..59a5f9e480 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -23,14 +23,16 @@ # ifdef TARGET_AARCH64 # define TARGET_TAGGED_ADDRESSES # endif -#else +#else /* !CONFIG_USER_ONLY */ /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 - -#endif +#endif /* !CONFIG_USER_ONLY */ + +/* ARM processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d28..ea5c8660dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -27,9 +27,6 @@ #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #ifdef TARGET_AARCH64 #define KVM_HAVE_MCE_INJECTION 1 #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9a92bc74fc..93c2f470d0 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -32,4 +32,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7960c5c57a..02a787b4f3 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -30,8 +30,6 @@ #define CPU_RESOLVING_TYPE TYPE_AVR_CPU -#define TCG_GUEST_DEFAULT_MO 0 - /* * AVR has two memory spaces, data & code. * e.g. both have 0 address diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index bb3d7ef6f7..4548103a18 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,4 +21,10 @@ #define TARGET_PAGE_BITS 12 +/* PA-RISC 1.x processors have a strong memory model. */ +/* ??? While we do not yet implement PA-RISC 2.0, those processors have + a weak memory model, but with TLB bits that force ordering on a per-page + basis. It's probably easier to fall back to a strong memory model. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8be45c69c9..6b10ab20ba 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -25,12 +25,6 @@ #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" -/* PA-RISC 1.x processors have a strong memory model. */ -/* ??? While we do not yet implement PA-RISC 2.0, those processors have - a weak memory model, but with TLB bits that force ordering on a per-page - basis. It's probably easier to fall back to a strong memory model. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 #define MMU_KERNEL_IDX 8 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 911b4cd51b..5e15335203 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,4 +24,7 @@ #endif #define TARGET_PAGE_BITS 12 +/* The x86 has a strong memory model with some store-after-load re-ordering */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cd2e295bd6..852adf35db 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -30,9 +30,6 @@ #define XEN_NR_VIRQS 24 -/* The x86 has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define KVM_HAVE_MCE_INJECTION 1 /* support for self modifying code even if the modified instruction is diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index cfe195db4e..db5ad1c69f 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -14,4 +14,6 @@ #define TARGET_PAGE_BITS 12 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 00d1fba597..dd1ab75ce9 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -39,8 +39,6 @@ #define IOCSR_MEM_SIZE 0x428 -#define TCG_GUEST_DEFAULT_MO (0) - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 9770b0eb52..e530fead1c 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,4 +29,7 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 +/* MicroBlaze is always in-order. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..943bae67d1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 594c91a156..6f6ac1688f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -30,4 +30,6 @@ #define TARGET_PAGE_BITS_MIN 12 #endif +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 52f13f0363..620db820f8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -10,8 +10,6 @@ #include "hw/clock.h" #include "mips-defs.h" -#define TCG_GUEST_DEFAULT_MO (0) - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; /* MSA Context */ diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 3f08207485..fbfc0f568b 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -13,4 +13,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index dedeb89f8e..e757e84caf 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#define TCG_GUEST_DEFAULT_MO (0) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 0a0416e0a8..c5565beae2 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -33,4 +33,6 @@ #endif #define TARGET_PAGE_BITS 12 +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..f21d8de6ff 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -29,8 +29,6 @@ #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define TCG_GUEST_DEFAULT_MO 0 - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index b2a9396dec..1fbd64939d 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -28,4 +28,6 @@ * - M mode HLV/HLVX/HSV 0b111 */ +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..01cddf5180 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -42,8 +42,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define TCG_GUEST_DEFAULT_MO 0 - /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 84ca08626b..11d23b600d 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -13,4 +13,10 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..10a63821b5 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -33,9 +33,6 @@ #define ELF_MACHINE_UNAME "S390X" -/* The z/Architecture has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define TARGET_HAS_PRECISE_SMC #define TARGET_INSN_START_EXTRA_WORDS 2 diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index cb11980404..82293fb844 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,4 +23,27 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never implemented + * in a SPARC V9 implementation and is not included in the Oracle SPARC + * Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) + #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 6999a10a40..10b04d37c6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -6,29 +6,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemented - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index b1da0555de..0000725f2f 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -17,4 +17,7 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8a423706d8..ca32657041 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -34,9 +34,6 @@ #include "hw/clock.h" #include "xtensa-isa.h" -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, From patchwork Mon Dec 11 21:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752543 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549151wrs; Mon, 11 Dec 2023 13:27:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IGxYEVqh7TFiaXePzizkp49ytWl7XhSQeKyoA2XK7wfb1pibU45KAXxk4mZ2A+CRCogbmdC X-Received: by 2002:a05:6214:1412:b0:67a:a3bd:8ca5 with SMTP id pr18-20020a056214141200b0067aa3bd8ca5mr4966365qvb.19.1702330079550; Mon, 11 Dec 2023 13:27:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330079; cv=none; d=google.com; s=arc-20160816; b=bvc7YbJeHzUe89f9Je2X/lRsl99yBLU4B2c6JgFRCjO0cUICQ0y9CSpeJhdWMrNkkg ilgRSLC84HWww2ggJAAkn4Bk+4rjDnDFmNGEhPFsF4JlZRCtzBDFQoFveBFVOh2pebTn 9L40QnaccnkS3LaMcadaqOKpLcQdpuOL8LKsWMveiqadbOYKaOfioSADG40HDIuXTa2I ur15UoykXfaZhkjJK0aczMuHyn5qJlRGtb1JNuEqQB6CNicLmsbXqSpQ0xUC39M03lYH /m8FbYSEUQwOtxv4nr8W1/6rD7X2z3YjW0hIgFhuRxh67TWbyo3pZwc/qVbIPZc5+0YT bfPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+33Nr6gIzIhUPCwLsBvRZhZAyU1ywCj1cKlsVdoDYyo=; fh=FIFGVIYXk9KJtQPgL9lL2Fk0MJdNDskMwQ9IfapQKgw=; b=HuhqqRVu3qjNbjYx88wJCdjVMKs6HnG/u1SyeNsBYybyjgiMsTMw+7uVQs8Zy037zd jgzHfbuW3FsdNTeye0kkR0sqa37wmJQpwLY0/GRhZ8X8bvfE/ft8rgPM4s6XdVnSJGIM Xqqb0iQWZsNWYUfAUus8KMxU/UsK/6wNhTlhjyxMEP6+qC6PmIQsZ22ozYUnpw2lY8AZ HY22qL+AXFO0Y/SeMMq5kEaQjxew8OO1LdgxcAE4qoLOWWuEX1vlOEaz0XwolQCCZ3Ep jo3DTP104ulBzI+QKr4Qvu2WhLFYHR1paflrpSQaBTMb8/A9h/iq7xfPPTgJXouvJhjk 2azw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ftUd12mj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Chris Wulff , Marek Vasut Subject: [PATCH 04/24] accel: Include missing 'exec/cpu_ldst.h' header Date: Mon, 11 Dec 2023 22:19:41 +0100 Message-ID: <20231211212003.21686-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Theses files call cpu_ldl_code() which is declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/translator.c | 1 + target/hexagon/translate.c | 1 + target/microblaze/cpu.c | 1 + target/microblaze/translate.c | 1 + target/nios2/translate.c | 1 + 5 files changed, 5 insertions(+) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 38c34009a5..5b019a0852 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "exec/exec-all.h" #include "exec/translator.h" +#include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-target.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 666c061180..744dc4fc3f 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,6 +23,7 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..91d7cd9061 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,6 +28,7 @@ #include "qemu/module.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/gdbstub.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..1c9a364c2b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..a74eb6909f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" From patchwork Mon Dec 11 21:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752535 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548603wrs; Mon, 11 Dec 2023 13:26:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQPIwlwWXAKoTOWmgEFcJu5F1Uia50uBIuViIBYuH8xAK4PvOR0MoLJ8051sCPVMT/Fexb X-Received: by 2002:a25:e805:0:b0:db5:4b76:56de with SMTP id k5-20020a25e805000000b00db54b7656demr2787885ybd.2.1702330003033; Mon, 11 Dec 2023 13:26:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330003; cv=none; d=google.com; s=arc-20160816; b=nFh2+OunTV03djEkbmdh7ARbOz4MpKez0/8gMyn6aJJRT6dMo8J4gArizpFpdCLmt1 rDUD1DBT0MCDdYYNzCQSp76RCRXLXL54OzNFCXC8EhiaH4Z26kXLDz9QEoCp9qWpME+S yrB3vZmnM9vRQFXzznE9gDpkMKAGpCRNd/zBBJ+ajYAQAjTOxGJ9K2tkPOyLrQbLvM3g 7pqR0+rkjBrHE4HdhR2qKZgvxXgJpKgITfz9tfbrXz40K57YeEx9fL4jVB0diGYEhb8X tcMh+qaJnKjhbVVylv2fibeiKb3Gdnmhg4kioUUCNsUM8MIFbbks7kf/H9Rg+xAwmQX5 UXBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Hdtduscqdl7lWoQvL5DT94RvR1c94dCnz5Zm14mzbGM=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=BGtEYMumDRiFakTdAxxRtmVYcpZdPU3Rv+kkgIndaIOG4KWmYuSqC/BHWyLHhl6aHG DaqGyMOIZSdBMA9wiWH9VHrGniF2rf3qN2dYVRz4TCXuhihJlOeSGR7DP91R8Ncwf4aH eF8dtyrflhsGKSkrP7rLLybWS3LfD65huXpXXcmF53Wlz5Efh0Rbr0WqZGW20P3v4PY1 BX69yYdXnfkKo3KxVp/5yVBdYCsInNhsrDMXAIEd6wvT3IUzEYgn/ImNnKDPP5V5U4/Z 8TnLmHdeQL09ftQe4lKXWjw54is04P31ObKwO7dYenHtTaYbWNHwHr3Hsppr05cqk4cQ 2URg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HvI+Lbt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:20:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 05/24] semihosting/uaccess: Avoid including 'cpu.h' Date: Mon, 11 Dec 2023 22:19:42 +0100 Message-ID: <20231211212003.21686-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "semihosting/uaccess.h" only requires declarations from "exec/cpu-defs.h". Avoid including the huge "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/semihosting/uaccess.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 3963eafc3e..6c8835fbcb 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -14,7 +14,7 @@ #error Cannot include semihosting/uaccess.h from user emulation #endif -#include "cpu.h" +#include "exec/cpu-defs.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ From patchwork Mon Dec 11 21:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752527 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1546549wrs; Mon, 11 Dec 2023 13:21:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfpfp+M9lCuT36x7nLikHWvlQ2eeMFBus/IPAPdUhxPNkQaNxn6IRvXfcUzVxTiR441CWG X-Received: by 2002:a05:6214:5149:b0:67e:b878:8e60 with SMTP id kh9-20020a056214514900b0067eb8788e60mr2705062qvb.69.1702329706389; Mon, 11 Dec 2023 13:21:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329706; cv=none; d=google.com; s=arc-20160816; b=xcjW/rW8qPU5DGNr/AqsaamyUbyDsy6qyS2eqhUm1DSK2LGHjPoKq3Hsh8M+IvC2Xv XVAYGMYJZ5KsVkwjEdQj8yDSCqk6Zff6MBCYGAdZtCghJINGJEBVtZNkUdv+MuM65JHn fjjJXJdQhhECWTAW9y1fLpeEfWO3jjwsytxi0noKWfgADbKqtmgFr4LmnWv3qrqLxnc6 GzMuw1gMedfGn/WPC9MsFCLa193VYvpJOqayylKjUACydx5AoJ+N4PjEeGhk8UVkro2i 1fCVQJH2BQFF4hg4zm8RBhPdJEQZ9OS7bGxpnuG4XXV3uIQ1J2a2ncgy+273nR9o6+05 Hicw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=y/4S5uEaEhG14FzKfAgbneY+HkdmgvAL2IyWQ5CT/QM=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=Wo/VRq0cJ93zqsI0NVJcqGE+gqebS1Ad0dc6ZwYdyJo3xVEGJqUh4widj+Ydb56gc+ F5KyKtZ8wkqcanTYVcYewUSc1b/c/HajKVzi3HM6tHOojRqPwZ3myOFv3z0F6Dui22mS /UwCWPr4G5hOPrf1211AwK7lr88NKAuSGKxHY3IoCggGB9Bb51a6VAYtrK/iJ8Nm8UZC 09FVQ6MDbCS46hErQkP0VCfxV+lA5SZkHHl1xE+o/OtmtoE7fkWzU+0VsM6vJkW8SQyc UfXS1XnN1C9A5CtyAsTmqcYYDhwh1vKBBUzp/LEGNZEGbsfDty4pM/mo+ejUHp6mPcWA uB9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wWmbQxsT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:21:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 06/24] semihosting/guestfd: Remove unused 'semihosting/uaccess.h' header Date: Mon, 11 Dec 2023 22:19:43 +0100 Message-ID: <20231211212003.21686-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Nothing in guestfd.c requires "semihosting/uaccess.h". Signed-off-by: Philippe Mathieu-Daudé --- semihosting/guestfd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c index 955c2efbd0..fd7e609790 100644 --- a/semihosting/guestfd.c +++ b/semihosting/guestfd.c @@ -15,7 +15,6 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else -#include "semihosting/uaccess.h" #include CONFIG_DEVICES #endif From patchwork Mon Dec 11 21:19:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752539 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548812wrs; Mon, 11 Dec 2023 13:27:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IFBCdJB7/e4eQkc9nFx2ZkC4P+1eS8l6EtxEcQYSwwtDaInqlyStxFrpPyaqA5TfXtVeXOj X-Received: by 2002:a05:622a:cd:b0:425:4043:8d3b with SMTP id p13-20020a05622a00cd00b0042540438d3bmr3868650qtw.86.1702330033070; Mon, 11 Dec 2023 13:27:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330033; cv=none; d=google.com; s=arc-20160816; b=JiCjJcPrnOa18AP3OCbCurStJ+YQAnyAQwSbnmizsujd7CzpDSchMVwllYvnYwc9BS WmFRLtph311BCguN+nWnIj/eLBPHH+c8m858W/L9xOG135GoeTslvnaz5SuFZDJFW22v lGK0GeOHL9usmCac/Pl0AznZC/2EfQ2RtRUyi+dvrpE+oN37FxgdBRO8/jSjDYVQUU9u bPPo9W1wVkkrpmjUOZLs39qV+Eg3pok1eU1y5Wh9oE7dViNTqgkMt4NSrD9Lo/h0gKlI IoNpw8sdPOjcoJmspW2dYjlu3tgqalIQsaT9CKf44O07kE43q9TM+orM51bdXeamYVb8 qVBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WbDQbeYc3MqbJhEQi67twemcgBt5US82mKEOXjqMt3c=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=DRsYoT8Bgwh5yeqMOxdLcfksfCzz8tG/AuUYHQmMWqHN1aGl5ifhXU4oBxCwZLhNZe 1l+DnwllqAwahkDKeI+lgtn1ay+leSX5LuEDCuonYj807EVPeXUWRvCGDeyAm99l4D+0 qaZb4lSvWs7Tj8RBm7LGw7f82zm7FUtx0J8tGE/NGkUx1lttD0Peuv4ZDlG6tuyTRnBo ix15fbX6oLg+6Lg0uD/o9NUkLf44iBfSrk1V2ihqFF2YCwDJnFJhauwdJkywokStDNjv HZgQp75gyC+tQOZDxjCriRFiuf8MHs+AfvX52ki+JrwKq9vT9J5a16mPpnYmFZZYNSHU 6jVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bu83fq66; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:21:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 07/24] host/load-extract: Include missing 'qemu/atomic.h' and 'qemu/int128.h' Date: Mon, 11 Dec 2023 22:19:44 +0100 Message-ID: <20231211212003.21686-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org int128_make128(), int128_getlo() and int128_urshift() are declared in "qemu/int128.h". qatomic_read__nocheck() is declared in "qemu/atomic.h". Signed-off-by: Philippe Mathieu-Daudé --- host/include/generic/host/load-extract-al16-al8.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/host/include/generic/host/load-extract-al16-al8.h b/host/include/generic/host/load-extract-al16-al8.h index d95556130f..6b47339b57 100644 --- a/host/include/generic/host/load-extract-al16-al8.h +++ b/host/include/generic/host/load-extract-al16-al8.h @@ -8,6 +8,9 @@ #ifndef HOST_LOAD_EXTRACT_AL16_AL8_H #define HOST_LOAD_EXTRACT_AL16_AL8_H +#include "qemu/atomic.h" +#include "qemu/int128.h" + /** * load_atom_extract_al16_or_al8: * @pv: host address From patchwork Mon Dec 11 21:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752528 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1546621wrs; Mon, 11 Dec 2023 13:21:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IFtDRvqp7fT2OcWeSLBAHKV4vCBPOadLHDtjh9wQfqG2HnoM1w3V+keJ7HK3dLqKVo3Z5Wv X-Received: by 2002:a05:6808:11c8:b0:3ba:3c4:2630 with SMTP id p8-20020a05680811c800b003ba03c42630mr3664110oiv.113.1702329717497; Mon, 11 Dec 2023 13:21:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329717; cv=none; d=google.com; s=arc-20160816; b=SOrX6u5wTEwPUt3UOrU+vjLOZVFMcCUe4lU/zoeX6Z4KmSSUxrzFqpDVKW1wdPD5Lp 3p6WCaZhiMV3B1YPwG3P2j10RqjS3tW+Lu9YRRCzmhH/feGlxzVQZG9WaPR3B6RDTHDJ TPWp/P0hA8m9cjRfERddVgXYc6gbwcsX234KBpqp8G+qD6igO2yr+xn/uoyjQ1QK+gp7 Vjn9T+A5mD2i/J7rnqiySo8c1O/gGKl81i2iy7lOHpbiJr4cuD13nddTxUurApEyqZDu taGLEncOxmcNQ1lhGfhquXaJeHLReOaQCyZkXXU1PU4r0VQ/TebP4IFXSzVcyx7U9NH7 PENQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=H2oQOL9llbvUksV5SG5fmsPenlEBFW6soeYnm+vf0wBT2Ucc3ABUXMzXtsSItOPxjx DWUB+8xgVQ0Ag665Pn37eRdhI7UTOC7krstHlz1E96foiceVVPKynVvD3X02UBLMwW5O 0IhmHpsA+s/OB0eRgTICb0OVXsJdW+ZQH0bcErJsGFsEUtkvt4QvIYe31ssTHXRyNPqd E77qDbieLsWXGvd766BnjsHIuMlTUBMoMO2j5+YYbnkV4MHQthmBZt+tjlAso4CERs9+ E3dz3RzXxizuEQeYID5WysSVSbcXQpQILMA65JoQCZjWQjktv4PdXKH71qE7Rri5eufn dTWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TFOOUYjN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:21:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 08/24] host/atomic128: Include missing 'qemu/atomic.h' header Date: Mon, 11 Dec 2023 22:19:45 +0100 Message-ID: <20231211212003.21686-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(), qatomic_set__nocheck() are defined in "qemu/atomic.h". Include it in order to avoid: In file included from include/exec/helper-proto.h:10: In file included from include/exec/helper-proto-common.h:10: In file included from include/qemu/atomic128.h:61: In file included from host/include/aarch64/host/atomic128-cas.h:16: host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i); ^ Signed-off-by: Philippe Mathieu-Daudé --- host/include/generic/host/atomic128-cas.h | 2 ++ host/include/generic/host/atomic128-ldst.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h index 6b40cc2271..4824f14659 100644 --- a/host/include/generic/host/atomic128-cas.h +++ b/host/include/generic/host/atomic128-cas.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_CAS_H #define HOST_ATOMIC128_CAS_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) static inline Int128 ATTRIBUTE_ATOMIC128_OPT atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h index 691e6a8531..12e4aca2da 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_LDST_H #define HOST_ATOMIC128_LDST_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) # define HAVE_ATOMIC128_RO 1 # define HAVE_ATOMIC128_RW 1 From patchwork Mon Dec 11 21:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752540 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548845wrs; Mon, 11 Dec 2023 13:27:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeyg90/GftCpBbGan6xFYiqi32Fqu+ODH0mfbbqckpBB9VrHh1d/wElY8gkDNV7uv96xMT X-Received: by 2002:a05:622a:1207:b0:425:9c55:1c48 with SMTP id y7-20020a05622a120700b004259c551c48mr7190187qtx.130.1702330037338; Mon, 11 Dec 2023 13:27:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330037; cv=none; d=google.com; s=arc-20160816; b=MArPb/4zryP1KJFN00mbF7Knv0i2TV2PFjIV9j347R8Cpz6R0DmJXAZcUPq8zYs4ik BXCMds97gXErGBV18pvp/AWPzm6ZyblWe2ytIqiqWb8Ycv69IzcDevPa7bHTiEKR7d3V HTQlN0XkxsvQRdzq+mX/bZdBRLh/XaN75YZhAjF5eCZYlu5Uf5m/XghyzgOrUAsCDhR8 1fV0652ZNFg9BkrzGFw3RYrsMnCg+IHDvFlqPVA5zDynBSMZJwEM7YK/z9aFC0Adpb91 2KSahYfGobR2n0Y5qGFNKA90UdX9jEvcl8RQuFmEmOnZyQbjWQVWLAWcl68Pp2EzEmzO lVYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=r9l5OJKRIKjrnTI1L+t9VvIOzVTPo5liJg25JIXeLpU=; fh=F2M01OhdvobOoOOc8NxVc0+1MEpzFU083WsjyBqzS9Q=; b=abZV9RXmU6F3ZixngJKb2qeRMHPD+QjYcYhZScpAYTxmdqnbEDf8fqqeGZpLI2v0fL NbdJ8PbiHZlnzX5wGr0foyesV2AQ6/QitYO5+4b20rJVPDsmipymwONNsZ4UJ+M8Piuj HD3D3homRDXYHiO//BBs3XGUZhi1g61rJm1Vcx4FsBCREdojruo1yGcCi1KQalaWcUVO 5LC2BYiSxWaTInD1b9unUHE57af7TqIcBPU+ekk97PzdTDOiYqqWA0KUmQlELrwfIcLU vMKkXPmLEIT4pOf5LpxUwcFgAZhrYlqI3G83xRJfetStXtfeegXyNdimK3qmFhb2rvk8 ZJFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U1LPWX30; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:21:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , David Gibson , Harsh Prateek Bora Subject: [PATCH 09/24] hw/ppc/spapr_hcall: Remove unused 'exec/exec-all.h' included header Date: Mon, 11 Dec 2023 22:19:46 +0100 Message-ID: <20231211212003.21686-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin --- hw/ppc/spapr_hcall.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 522a2396c7..fcefd1d1c7 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -8,7 +8,6 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "exec/tb-flush.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" From patchwork Mon Dec 11 21:19:47 2023 Content-Type: text/plain; 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Mon, 11 Dec 2023 13:21:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PATCH 10/24] hw/misc/mips_itu: Remove unnecessary 'exec/exec-all.h' header Date: Mon, 11 Dec 2023 22:19:47 +0100 Message-ID: <20231211212003.21686-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org mips_itu.c only requires declarations from "hw/core/cpu.h" and "cpu.h". Avoid including the huge "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/mips_itu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 5a83ccc4e8..37aea0e737 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -22,9 +22,10 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" -#include "exec/exec-all.h" +#include "hw/core/cpu.h" #include "hw/misc/mips_itu.h" #include "hw/qdev-properties.h" +#include "target/mips/cpu.h" #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8) /* Initialize as 4kB area to fit all 32 cells with default 128B grain. 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Mon, 11 Dec 2023 13:21:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Christian Borntraeger , Halil Pasic , Eric Farman Subject: [PATCH 11/24] hw/s390x/ipl: Remove unused 'exec/exec-all.h' included header Date: Mon, 11 Dec 2023 22:19:48 +0100 Message-ID: <20231211212003.21686-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; 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Mon, 11 Dec 2023 13:21:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 12/24] target/i386: Include missing 'exec/exec-all.h' header Date: Mon, 11 Dec 2023 22:19:49 +0100 Message-ID: <20231211212003.21686-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The XRSTOR instruction ends calling tlb_flush(), declared in "exec/exec-all.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4430d3d380..3bb018fbae 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" +#include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" From patchwork Mon Dec 11 21:19:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752529 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1546981wrs; Mon, 11 Dec 2023 13:22:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IHGcX03UG4+XiUUOI4Is8IaZSdELNz1TR6FJ2Vf2NQA/BvWXEbaSUxhtIaNfo/ZkxZT6A6U X-Received: by 2002:a05:620a:cc2:b0:77e:fba3:759d with SMTP id b2-20020a05620a0cc200b0077efba3759dmr5046040qkj.149.1702329769149; Mon, 11 Dec 2023 13:22:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329769; cv=none; d=google.com; s=arc-20160816; b=07vJWKhj+Q5QMs3m+0CABJFH+84IBCQ/p6NfA1NUKvnLhifmj4fK7YLSFqAVLRGi8u 7dskjpwgt13/1fdIlzInRs8I+tSpn1MY7Ow6jftetxAB6aCVQF0GoH1mkl+9F3lS3s32 YnwLVE1RRR6Bp3jIstmZeSMpahCWYg0VUYB51i22OyiYA85LIgVjMKzHgJLt/D5EZMU0 j1+VtWi/oVqutyUAtJ/NriBpwkMJM2XeSAtvh4m29eGgd9wXDbCjryqVDO6QuzPGKQdS tiIjvexqwEdQ93fZPWAstw54gdtIt43pRFJtyCsUM78MY84KzyPUTPC7jo1KfFwnSPGc OfjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Sxk2B1Wo2pXRo42/SYBVVIycoetyzxarj96J9gTlCqc=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=XM1i9uUF0CJyUkRF+y1pr+5NeKtCmcFj3+PNUzcmm7KLc3yZzpeJNjOSlGY2EPGdU1 gz1cLhrGUf4s9IYgbDJ+X5Fiq1QE69NrO4WDAzaclOaUnTP6ebsQfWbnQyoSvAqoP9Ia ysJlo+1rK1gkvYUdhzb3Q7Yt0AkdZsnYUcVkpeiNPdAzH56syOcutS6BoVC7j5HJnOQd Xy3ZOCzPmq3KLhN5AtSn8suwGp6UgprKbQzatU4ds43/arTcJberNtbaP2orpGvJ8jti 5WOGYioNTCoA100A+/9LPNJK4vpiqcM0zvGdCn34oRZQP4XdHbiCFnAW8pJokYJ3NQxq KdPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PSIdCiEy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:21:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 13/24] accel/tcg: Include missing 'hw/core/cpu.h' header Date: Mon, 11 Dec 2023 22:19:50 +0100 Message-ID: <20231211212003.21686-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org tcg_cpu_init_cflags() accesses CPUState fields, so requires "hw/core/cpu.h" to get its structure definition. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/tcg-accel-ops.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 1b57290682..58806e2d7f 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -37,6 +37,8 @@ #include "exec/tb-flush.h" #include "exec/gdbstub.h" +#include "hw/core/cpu.h" + #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" #include "tcg-accel-ops-rr.h" From patchwork Mon Dec 11 21:19:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752538 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548799wrs; Mon, 11 Dec 2023 13:27:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IEoKF6F/71uDQxxrkVbarp1NZvJK5ZLzKr2ntBvz4EZLjZbFZy5dpOsss/Ej5ynOWbMi5YH X-Received: by 2002:a05:622a:1985:b0:423:89b4:b798 with SMTP id u5-20020a05622a198500b0042389b4b798mr7726187qtc.14.1702330031384; Mon, 11 Dec 2023 13:27:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330031; cv=none; d=google.com; s=arc-20160816; b=z15Oh0LB+S2ibLqAeoY3Rqd23H/Qd/gS45iU3vNC27U6ygRlwYRmQDIOa2lC3yu+uH V8JX1kUmrzpOJLkSxZ6DU4w9Y0YsoE1GvWxOSmMPqGt5U+qzs7vEiDeiUCrMZENgrRtX pgmyiHnfNMdsmYGoQIGa3i0aPdjUF1FaL7UMyvxUwDKX1omFhFG2NrQbRKKs2Dprymla QYr/jrOHLpD16jDZaKu9grBZjDdr49QojbG6QYamcpzHr8JCX9rNcwdp+VkOSo+eiP8O +fP0hQSkvSx3sKtKwUexgGCtnrTRKmfihiBbHpIc3vVBwoIYa6ty+dFnyoAYAS7tnrEs rfvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=U3EU22bNfiIc1b+ZyOtnWaIQVzLfNzz6gZyDB25Dnbs=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=yTVtVjyhoQD0C2QieuduJEpX7sqBNqnaUr0TGM1dXoLEZi7IT8l8oCmlcSTuupXrKN 5bILKdUgXmQIcdZqS2cqlz6mnWkOj6RGoOTfiTLlgGGQlaLDnKBBlrp01+AD4B31jKTK y/NR+xstPqLCez8KU8k5Yvcktl0O54XSEhT42GWm+6+PoUSqFXBpxR+zX3JIezReUTqc tXMgVbeEMkNiQC3OhStNEBGQjVP4QXr36OvAnPFALkFK4XOahXYUemcP8nGFWds+xV68 KHn45PlmSdfeluYWdK3dkL6ZYYhrIjuuopvSkAjdJCn9SWco/7gcVdmOEe4yTu1m7z2y 8Xug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y3wkVg3X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:22:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 14/24] gdbstub: Include missing 'hw/core/cpu.h' header Date: Mon, 11 Dec 2023 22:19:51 +0100 Message-ID: <20231211212003.21686-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Functions such gdb_get_cpu_pid() dereference CPUState so require the structure declaration from "hw/core/cpu.h": static uint32_t gdb_get_cpu_pid(CPUState *cpu) { ... return cpu->cluster_index + 1; } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh --- gdbstub/gdbstub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 46d752bbc2..034a4ac211 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -37,6 +37,7 @@ #include "hw/cpu/cluster.h" #include "hw/boards.h" #endif +#include "hw/core/cpu.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" From patchwork Mon Dec 11 21:19:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752547 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549778wrs; Mon, 11 Dec 2023 13:29:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IF9XuuQShM6BOHG696gAMwXrkcew4XpazbBunEwNjm7sIO6sVyFuRvXGQ0pwkG34sTAvhE7 X-Received: by 2002:a05:6808:3846:b0:3ba:c12:3e89 with SMTP id ej6-20020a056808384600b003ba0c123e89mr2859605oib.106.1702330173357; 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Mon, 11 Dec 2023 13:22:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 15/24] exec/cpu-all: Remove unused headers Date: Mon, 11 Dec 2023 22:19:52 +0100 Message-ID: <20231211212003.21686-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Nothing is required from the "qemu/thread.h" and "hw/core/cpu.h" headers. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9a7b5737d3..b1e293a08f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,8 +22,6 @@ #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" -#include "qemu/thread.h" -#include "hw/core/cpu.h" #include "qemu/rcu.h" /* some important defines: From patchwork Mon Dec 11 21:19:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752544 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549275wrs; Mon, 11 Dec 2023 13:28:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IE3q1itn0NHnYJ3BnI3GQmRCZEwxj6F16WRsWBNN0DCNrf87Gire6Xbd30OKrSG0F07h2DG X-Received: by 2002:a05:622a:1a15:b0:425:8959:8acb with SMTP id f21-20020a05622a1a1500b0042589598acbmr6809382qtb.43.1702330098745; Mon, 11 Dec 2023 13:28:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330098; cv=none; d=google.com; s=arc-20160816; b=lJcXMIEGEoJf5bqxL8Gp6Yx/3KvO6Kvc8Lu+rR/h9zSPT+JJsy2hE5m2ChNmqkxKaK 3G/PPYrUMACNGfCD/Tm3DY+Ref3emdG7HuIcO367rMyxWGeHtQlCuhBiL62N9QQsq46a RMW9VdN2Uok6LmsrSwHHitT+bMBnze9HhJAsAA3Y3/LOUMSzG5nXvuTcvefaPaG6FZig tQd3HtVu97ZmSnKmkC1D7zLr69cS5BvVVNXABoAxt8U6o9/0QPSa7de7DZoUMM6TtSEX zSyFCXz3JYgRtqcGp7+b8YVouz3Ie8/wWHK8655hXoWS2NdxP/MCu5ZCDyr7nDjJxMwd J4OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=31p8j5Jt1hoDV9F+fYTdM7YWxOI6Tic5VBGPVB9TKlo=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=c5xdkTAP6Prim2dm4CdypR3wuy9PN/xtVg0a8Bpg1ONEJnVnvznNqO8VsB/oQjlhoz MnLfP2anuU3LZtlNL3VVXqTqfGd+05EIQUwi1QVkomHeRu1qJmDjOw8IiA+xbo0v4+Oo nh/4sP9fWgiN8JOe6ManrbrDFmitlN2IDRGeB2n47DjdPtikhQz3oLBibuHhk3BZ2xPz TWrWYPHY/3c1rAAqjKQaK2Oxpdg5b4KowC7qODnHC32cuiCqSRt+YMAnisV8i6Mfi/fp 2HKC54ikTZ/ersKVehlCmrybCgrAsaPo/hun2Trm2U6/JQ9kvS2/Ai43bt0+mxOuamFe uQHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WH1TVbEr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:22:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 16/24] exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion Date: Mon, 11 Dec 2023 22:19:53 +0100 Message-ID: <20231211212003.21686-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/cpu-all.h" doesn't need definitions from "qemu/rcu.h", however "exec/ram_addr.h" does. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/exec/ram_addr.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b1e293a08f..2d568ae4f0 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,7 +22,6 @@ #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" -#include "qemu/rcu.h" /* some important defines: * diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 90676093f5..aab7d6c57c 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -25,6 +25,7 @@ #include "sysemu/tcg.h" #include "exec/ramlist.h" #include "exec/ramblock.h" +#include "qemu/rcu.h" extern uint64_t total_dirty_pages; From patchwork Mon Dec 11 21:19:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752532 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1547439wrs; Mon, 11 Dec 2023 13:23:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IGR7sMqwR6opb+8gM+JmwxTTtL9IRqCSXsQ/6Bwot9K6NJjpsd/SoHpqBGl5/zpns1W3RcR X-Received: by 2002:a05:6808:3c99:b0:3b8:4164:5fe0 with SMTP id gs25-20020a0568083c9900b003b841645fe0mr6368045oib.37.1702329829749; Mon, 11 Dec 2023 13:23:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702329829; cv=none; d=google.com; s=arc-20160816; b=bJa+c6pvb0uM8LLsRh0KOMdc45c9ai2gSagozDhzyqktSNsELIZoFcNoepr+Ly/iH7 461wAZRSo8mWQAMX8C0zAoe+CYZMT36xoJ7MbpWTT9JGu48I6EECBHn4jCoeqL0tXrUH Y/QCfGXGI2r0U/D/Rn9y51qjH/mslZ3cyUMWPAHTw77DUtjqnns5C+KdZy9dfhpQHQ6G VOQhDKmS2TOozecpSOUBFzWMD074EEVAfJjBczhE9cuVKhkUKfi/2qO77/0mDcxwRWNF T5f2+KmXRYKhUIfQvB0TEyhtFpI6p9dRJBq4pZCRGlaAKwfwK8916P57PaWzH//Y5d6m iJ6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jCN6XEpRfBzl6QRBVexJQczvz29R6MzglzJSIvh3kCU=; fh=nNxGOtwFJbFbIeD7JuqhPtCnPp6jwl4EO+WBprDXaus=; b=uL26jauAdm0cJcSaEHTp7DtR3dFADzckmETk/7JccEnZW28UGcrr66Xn0YeLtGv+hg CkJREf7kfDfhTfklo1BJoOMgCPb/p5j03v5XMyzt/iv6V1IXDM9SEC9vWehIjumyKNOw GYltN76gK08oyG4cCujOEMo+PYNlWLIcCNdgHmkKtfBu3X32iJ/NF/+88x8mcTNffL5a Ld9mgLx0kZ9+v72MBtKXVP65j9MU42CVCKTml1GBnmFDBDtVrwEcz0Af7PV9x5NGEbj2 pthfydLqoR7CcnvvtdHIax4d0vJSea9Yf8NJtq+CH89SVIvKBCuCVi+aEwVmOXu7R+HI ML+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j0sybf8R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:22:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH 17/24] target/ppc/excp_helper: Avoid 'abi_ptr' in system emulation Date: Mon, 11 Dec 2023 22:19:54 +0100 Message-ID: <20231211212003.21686-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 'abi_ptr' is a user specific type. The system emulation equivalent is 'target_ulong'. Use it in ppc_ldl_code() to emphasis this is not an user emulation function. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a42743a3e0..3d7c9bbf1a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -142,7 +142,7 @@ static inline bool insn_need_byteswap(CPUArchState *env) return !!(env->msr & ((target_ulong)1 << MSR_LE)); } -static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) +static uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr) { uint32_t insn = cpu_ldl_code(env, addr); From patchwork Mon Dec 11 21:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752536 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548636wrs; Mon, 11 Dec 2023 13:26:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxp5wuSVOPnK9/Hi1dTWMIXAkqa0vuiAjPPf0eH8oCTQRjDrZ15yiYYwVL0d6szCOn9TL3 X-Received: by 2002:a05:620a:a87:b0:77e:fba3:9cee with SMTP id v7-20020a05620a0a8700b0077efba39ceemr6124434qkg.82.1702330008992; Mon, 11 Dec 2023 13:26:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330008; cv=none; d=google.com; s=arc-20160816; b=cXifTZst6nJO3Kva+wwWaakqntrpF1FyCfK/TYYe3MHytleRwK/S+CLSSAknRV/F7r rj4n8zehwsfbK05fbHif6F9TTLkUOKOnCBWFGGxEkUHrN1Bbq83yXaQ2w17WQEAWMg91 FsjVI0C9VJz7GV+2QFw7Wtg1IGbd9u++MsQKNujEXhNrWGk5/S70uYy1Dex+mTGKwg7s 7lo/NhEz9r2OeNdh7Ih1WjC7yW9aDX4eG+aVgedkR3GIDD5E7LlHd//Y18r6rSoJajVB pc5H3+ebVyQVGfQXaS7NcKhHkFhRw9auphQz4L4/qgcV4Hu6+ZCeA7LVmbIha6VTnKnR 7Wdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rDPDUy3GuLtVTYcoiToi/C6HdVw4jRlY7C7+srVSuzU=; fh=B0OEDADjyZZ394IF34p+Sju0laY+Le2V70wZ4wNEC7c=; b=VE/x/oqMX+BAbJwAWPxT4Rc4anB1KorOVBZCEWdtjv8F8VrLfQEz5qc/L1P5Nzg7At uxYBCHrWSfVU2Zj65n/oTGwbYz1Ky+x/fy4ldB4Gu/qQRI2yCdQD3zKNsV8LXHkVekJr nCNhVRrY4t7yZEpoe7ZCBtRp5exEGCwrL5zu+3cqKzTR7JTjQtIt0xzKP8iLmHq36kE5 0hs4hxyDja8zXGZPFsf2UajzU1jDQmu44DyoJvmttsKzf7AdpaXmbJ4PVD2Fxj3y4inI uE56sgSHPshUMXNw8sNbE7y5Tmbsd1sTMDqxdg3mN5lL/pnKORjA3sKwsK/SqBtH94n3 MQqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dpuAsGXv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:22:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Riku Voipio Subject: [PATCH 18/24] accel/tcg: Un-inline retaddr helpers to 'user-retaddr.h' Date: Mon, 11 Dec 2023 22:19:55 +0100 Message-ID: <20231211212003.21686-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org set_helper_retaddr() is only used in accel/tcg/user-exec.c. clear_helper_retaddr() is only used in accel/tcg/user-exec.c and accel/tcg/user-exec.c. No need to expose their definitions to all user-emulation files including "exec/cpu_ldst.h", move them to a new "user-retaddr.h" header (restricted to accel/tcg/). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/user-retaddr.h | 28 ++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 28 ++-------------------------- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/user-exec.c | 1 + 4 files changed, 34 insertions(+), 26 deletions(-) create mode 100644 accel/tcg/user-retaddr.h diff --git a/accel/tcg/user-retaddr.h b/accel/tcg/user-retaddr.h new file mode 100644 index 0000000000..e0f57e1994 --- /dev/null +++ b/accel/tcg/user-retaddr.h @@ -0,0 +1,28 @@ +#ifndef ACCEL_TCG_USER_RETADDR_H +#define ACCEL_TCG_USER_RETADDR_H + +#include "qemu/atomic.h" + +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr = ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr = 0; +} + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6061e33ac9..25e7239cc5 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -300,31 +300,7 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, abi_ptr addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); -#if defined(CONFIG_USER_ONLY) - -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr = ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr = 0; -} - -#else +#if !defined(CONFIG_USER_ONLY) #include "tcg/oversized-guest.h" @@ -376,7 +352,7 @@ static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; } -#endif /* defined(CONFIG_USER_ONLY) */ +#endif /* !defined(CONFIG_USER_ONLY) */ #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c938eb96f8..e591992d0c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -44,6 +44,9 @@ #include "tb-context.h" #include "internal-common.h" #include "internal-target.h" +#if defined(CONFIG_USER_ONLY) +#include "user-retaddr.h" +#endif /* -icount align implementation. */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 68b252cb8e..2575f0842f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -31,6 +31,7 @@ #include "tcg/tcg-ldst.h" #include "internal-common.h" #include "internal-target.h" +#include "user-retaddr.h" __thread uintptr_t helper_retaddr; From patchwork Mon Dec 11 21:19:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752548 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549813wrs; 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Mon, 11 Dec 2023 13:22:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 19/24] exec/user: Do not include 'cpu.h' in 'abitypes.h' Date: Mon, 11 Dec 2023 22:19:56 +0100 Message-ID: <20231211212003.21686-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org First, "exec/user/abitypes.h" is missing the following includes (they are included by "cpu.h"): - "exec/target_long.h" - "exec/cpu-all.h" - "exec/tswap.h" Second, it only requires the definitions from "cpu-param.h", not the huge "cpu.h". In order to avoid "cpu.h", pick the minimum required headers. Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/user/abitypes.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h index 6178453d94..1a8cd1ac74 100644 --- a/include/exec/user/abitypes.h +++ b/include/exec/user/abitypes.h @@ -1,7 +1,14 @@ #ifndef EXEC_USER_ABITYPES_H #define EXEC_USER_ABITYPES_H -#include "cpu.h" +#ifndef CONFIG_USER_ONLY +#error Cannot include this header from system emulation +#endif + +#include "cpu-param.h" +#include "exec/target_long.h" +#include "exec/cpu-all.h" +#include "exec/tswap.h" #ifdef TARGET_ABI32 #define TARGET_ABI_BITS 32 From patchwork Mon Dec 11 21:19:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752542 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549087wrs; Mon, 11 Dec 2023 13:27:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IHL/li4FdqvQK470wyFEXko1BFOwlopfcVfnjM1C6H6IrTZEoT7XHmNP24lXAa7kch38ljy X-Received: by 2002:a05:620a:c0a:b0:77e:fba3:9d23 with SMTP id l10-20020a05620a0c0a00b0077efba39d23mr4750903qki.135.1702330070617; Mon, 11 Dec 2023 13:27:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330070; cv=none; d=google.com; s=arc-20160816; b=DaAggUK5NUfwtp4o7cGxU7+1EsVGorj53OR+z5ol4FIinnkJQEMhNYvadhbCtL/2dh FEuJTXK1VDBFgKi1RCPEqFIwTpT0SQfJuoBcR6kPuw64D3fNQqWGmLQATOuTAYet5jkt CPhYOPT+ceai4V9vo5i80qjFOYjC5eVwSKO3Pe8bozZsSzJiTlZBmOcAwJAuNFuWqn9o zLClgSM/kDwl3Vg/eJedqh0RIs4Qxi06cSoS86cAeYRbzX/uWS2Bidp2z0Ew/n5Hc9jC aEsFWk1dN45IJ1uFQ5pDiPS31lMiI62x+L5vHKfKt73DwSQKejTzHKpr5xCiIqyQjOkC yWhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t6uthcvrcMhZYh7TDKG7c2NiXaXu0mJGOW4mt+82VSg=; fh=6uA3yvXeN55FEhLQ+7xhayEyGzy+Y3z2qOYV5oRrcR8=; b=tvRWMsSJJggpB3PWkRAMTzehoXax8dnI85aT6thj0K1BpreGKY2oU3/+mkoRhtx0P0 rAMfztBgFYy00oGbbe8+LnQAqii7MYSslVW/Ma+o05uq89aFTXbTWl1DSEAIVpZ0In78 U6AXi+OwZzXGGPlUANMP0LUalT+UKb9rspyjP+U+y9iDsDElUCwYL1/EXaNA0b6kBD74 ASeEOtx4Gv0buWiO1VEdqnsnoy01bcFO9/xzZhBZ1DBKodko6ALMrFBZsmiAGb50l5tv NOL2XvbJFh2DbvBSG9++1Flv597teroUzKjxddRefr2uLYnSba+niltkfseQsjIMBAla W5Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bPZHzTPr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Mon, 11 Dec 2023 13:22:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 20/24] exec: Declare abi_ptr type in its own 'tcg/abi_ptr.h' header Date: Mon, 11 Dec 2023 22:19:57 +0100 Message-ID: <20231211212003.21686-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The abi_ptr type is declared in "exec/cpu_ldst.h" with all the load/store helpers. Some source files requiring abi_ptr type don't need the load/store helpers. In order to simplify, create a new "tcg/abi_ptr.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 17 +++-------------- include/exec/exec-all.h | 1 + include/exec/translator.h | 5 ++++- include/tcg/abi_ptr.h | 32 ++++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 1 + 5 files changed, 41 insertions(+), 15 deletions(-) create mode 100644 include/tcg/abi_ptr.h diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 25e7239cc5..c69f02b699 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -65,18 +65,9 @@ #include "exec/memopidx.h" #include "qemu/int128.h" #include "cpu.h" +#include "tcg/abi_ptr.h" #if defined(CONFIG_USER_ONLY) -/* sparc32plus has 64bit long but 32bit space address - * this can make bad result with g2h() and h2g() - */ -#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 -typedef uint32_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%x" -#else -typedef uint64_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%"PRIx64 -#endif #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) @@ -120,10 +111,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) assert(h2g_valid(x)); \ h2g_nocheck(x); \ }) -#else -typedef target_ulong abi_ptr; -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx -#endif + +#endif /* CONFIG_USER_ONLY */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index df3d93a2e2..6a634c0889 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -22,6 +22,7 @@ #include "cpu.h" #if defined(CONFIG_USER_ONLY) +#include "tcg/abi_ptr.h" #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" diff --git a/include/exec/translator.h b/include/exec/translator.h index 6d3f59d095..16d2449292 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -19,7 +19,10 @@ */ #include "qemu/bswap.h" -#include "exec/cpu_ldst.h" /* for abi_ptr */ +#include "exec/cpu-common.h" +#include "exec/cpu-defs.h" +#include "cpu.h" +#include "tcg/abi_ptr.h" /** * gen_intermediate_code diff --git a/include/tcg/abi_ptr.h b/include/tcg/abi_ptr.h new file mode 100644 index 0000000000..415e31cabb --- /dev/null +++ b/include/tcg/abi_ptr.h @@ -0,0 +1,32 @@ +/* + * TCG abi_ptr type + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TCG_ABI_PTR_H +#define TCG_ABI_PTR_H + +#include "cpu-param.h" + +#if defined(CONFIG_USER_ONLY) +/* sparc32plus has 64bit long but 32bit space address + * this can make bad result with g2h() and h2g() + */ +#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 +typedef uint32_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%x" +#else +typedef uint64_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%"PRIx64 +#endif + +#else /* !CONFIG_USER_ONLY */ + +#include "exec/target_long.h" + +typedef target_ulong abi_ptr; +#define TARGET_ABI_FMT_ptr TARGET_FMT_lx + +#endif /* !CONFIG_USER_ONLY */ + +#endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index db3f93fda9..c4500d3261 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,6 +41,7 @@ #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif +#include "tcg/abi_ptr.h" #include "tcg/tcg-ldst.h" #include "tcg/oversized-guest.h" From patchwork Mon Dec 11 21:19:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752549 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549844wrs; Mon, 11 Dec 2023 13:29:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFb8w4m/61z/3vzK6ixpLex9zRwwZLmlcfQpWFjGqmYViD2ubBBNTKR5ouMvQExNKHvqMO3 X-Received: by 2002:a05:620a:2482:b0:77d:c413:d29a with SMTP id i2-20020a05620a248200b0077dc413d29amr7221463qkn.1.1702330182151; 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Mon, 11 Dec 2023 13:22:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 21/24] exec/cpu_ldst: Avoid including 'cpu.h' Date: Mon, 11 Dec 2023 22:19:58 +0100 Message-ID: <20231211212003.21686-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/cpu_ldst.h" doesn't need to huge "cpu.h" header, but simply: - exec/cpu-defs.h - exec/tlb-common.h - exec/user/abitypes.h - exec/user/guest-base.h Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu_ldst.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c69f02b699..a115553ee8 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -64,11 +64,15 @@ #include "exec/memopidx.h" #include "qemu/int128.h" -#include "cpu.h" +#include "exec/cpu-defs.h" +#include "exec/tlb-common.h" #include "tcg/abi_ptr.h" #if defined(CONFIG_USER_ONLY) +#include "exec/user/abitypes.h" +#include "exec/user/guest-base.h" + #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) { From patchwork Mon Dec 11 21:19:59 2023 Content-Type: text/plain; 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Mon, 11 Dec 2023 13:23:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Kyle Evans , Laurent Vivier Subject: [PATCH 22/24] exec/cpu-all: Restrict inclusion of 'exec/user/guest-base.h' Date: Mon, 11 Dec 2023 22:19:59 +0100 Message-ID: <20231211212003.21686-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Declare 'have_guest_base' in "exec/user/guest-base.h". Very few files require this header, so explicitly include it there instead of "exec/cpu-all.h" which is used in many source files. Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 3 --- include/exec/user/guest-base.h | 6 ++++++ bsd-user/main.c | 1 + linux-user/elfload.c | 1 + linux-user/main.c | 1 + 5 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 2d568ae4f0..5b75d04ff6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -74,9 +74,6 @@ #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" -#include "exec/user/guest-base.h" - -extern bool have_guest_base; /* * If non-zero, the guest virtual address space is a contiguous subset diff --git a/include/exec/user/guest-base.h b/include/exec/user/guest-base.h index afe2ab7fbb..cf40151360 100644 --- a/include/exec/user/guest-base.h +++ b/include/exec/user/guest-base.h @@ -7,6 +7,12 @@ #ifndef EXEC_USER_GUEST_BASE_H #define EXEC_USER_GUEST_BASE_H +#ifndef CONFIG_USER_ONLY +#error Cannot include this header from system emulation +#endif + extern uintptr_t guest_base; +extern bool have_guest_base; + #endif diff --git a/bsd-user/main.c b/bsd-user/main.c index e6014f517e..c331d727e1 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -36,6 +36,7 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "exec/exec-all.h" +#include "exec/user/guest-base.h" #include "tcg/startup.h" #include "qemu/timer.h" #include "qemu/envlist.h" diff --git a/linux-user/elfload.c b/linux-user/elfload.c index cf9e74468b..f9e9ac1760 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -6,6 +6,7 @@ #include #include "qemu.h" +#include "exec/user/guest-base.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/main.c b/linux-user/main.c index 0cdaf30d34..84691d707b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -38,6 +38,7 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "qemu/plugin.h" +#include "exec/user/guest-base.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "gdbstub/user.h" From patchwork Mon Dec 11 21:20:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752545 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1549325wrs; Mon, 11 Dec 2023 13:28:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IEowB6/JWlon1dkOsVERTLOEPQ78J6redVgT9BS+YCJMiXChbbJ86PLKxYjQMoNYQvjaRMW X-Received: by 2002:a05:620a:27d4:b0:77d:88eb:d722 with SMTP id i20-20020a05620a27d400b0077d88ebd722mr3816641qkp.35.1702330108542; Mon, 11 Dec 2023 13:28:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702330108; cv=none; d=google.com; s=arc-20160816; b=IoubEPLBkoIpd6VthYF1SuoxnKLjGNxYHFpI5BaF/xJ698h6uTVEJQxNopp5ZCDNai Sso+OgV/I5j/Z3evfjaIVL3N9SVrIXt8Yb99cT4FKX1WIfmbUp7Kr+JJScRqlq9DS6Z/ VofAPvAfpQvF4PeIGQa71zGc8fBgw8eC/zojNxa1OGi0WNJy3Ld3JBFjFqnvBP//9eal GmsORBEOAtEHh9zIrReRdXE/bJy0FKdiurEePVMp8p9K5VLbzmyoN101foTPcpEX5mzQ Ay42ZLf6MNihQLA5deYVAG+RtvRO7T8USAGjdQwhn8XZE514RbCmBmgzWBp0nrTQLpkL Dk2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TrH87JADUqY5Kw0eD6wsc0cK28jLqdwv6cP8Q5jpsTk=; fh=QZsDY/y7xmlR7tggqcgDezPeL60p/bHdDZUOhZaRiBU=; b=KSfjdoU+TnTU5Ld+eATLkEj0Y2cFNVTyO6Cjrv//NKKHqitzhIgp6fi45KtHh5tVLG ppounthGIOOHYdtzPw9YM5heDahXKMDdWZrJ+k5CPCgoTvmcLcW+HAxZjMpV+goaYBgT JTJc2ViGOCnUHcXLURlVhEX+kegtD2G+tlF/6r4FU7RRzP7UZ34VoPv2wEvsSBw24rYK FulEH1I4JMgJ9r6Ke9nLZRtKY5oOp6WyNCufdm/4g2uw7JRbC8yxa4Ho1vuCpi9/jOcy 1cqTg7RvJ8QFq2pIea2VPeBibdSadFy/IyaEoVHUPDKErdVvf9NU5ibPcAjetbq2ECN/ s7ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zhh7DdkY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Laurent Vivier , Michael Rolnik , Song Gao , Huacai Chen , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Yoshinori Sato , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PATCH 23/24] exec/cpu-all: Extract page-protection definitions to page-prot-common.h Date: Mon, 11 Dec 2023 22:20:00 +0100 Message-ID: <20231211212003.21686-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=philmd@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-prot-common.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|BITS|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin (ppc) --- bsd-user/bsd-mem.h | 1 + bsd-user/qemu.h | 1 + include/exec/cpu-all.h | 35 +------------------------ include/exec/page-prot-common.h | 38 ++++++++++++++++++++++++++++ include/semihosting/uaccess.h | 1 + target/arm/cpu.h | 1 + target/ppc/internal.h | 1 + target/ppc/mmu-radix64.h | 2 ++ accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/user-exec.c | 1 + bsd-user/mmap.c | 1 + bsd-user/signal.c | 1 + cpu-target.c | 1 + hw/ppc/ppc440_bamboo.c | 1 + hw/ppc/sam460ex.c | 1 + hw/ppc/virtex_ml507.c | 1 + linux-user/arm/cpu_loop.c | 1 + linux-user/elfload.c | 1 + linux-user/mmap.c | 1 + linux-user/nios2/cpu_loop.c | 1 + linux-user/signal.c | 1 + linux-user/syscall.c | 1 + system/physmem.c | 1 + target/alpha/helper.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/m_helper.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/avr/helper.c | 1 + target/cris/mmu.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/translate.c | 1 + target/i386/tcg/sysemu/excp_helper.c | 1 + target/loongarch/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/mips/sysemu/physaddr.c | 1 + target/mips/tcg/sysemu/tlb_helper.c | 1 + target/nios2/helper.c | 1 + target/nios2/mmu.c | 1 + target/openrisc/mmu.c | 1 + target/ppc/mmu-hash32.c | 1 + target/ppc/mmu-hash64.c | 1 + target/ppc/mmu-radix64.c | 1 + target/ppc/mmu_common.c | 1 + target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/pmp.c | 1 + target/riscv/vector_helper.c | 1 + target/rx/cpu.c | 1 + target/s390x/mmu_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/sh4/helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/op_helper.c | 1 + 60 files changed, 98 insertions(+), 34 deletions(-) create mode 100644 include/exec/page-prot-common.h diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index 21d9bab889..f95472bcab 100644 --- a/bsd-user/bsd-mem.h +++ b/bsd-user/bsd-mem.h @@ -56,6 +56,7 @@ #include #include "qemu-bsd.h" +#include "exec/page-prot-common.h" extern struct bsd_shm_regions bsd_shm_regions[]; extern abi_ulong target_brk; diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index dc842fffa7..1e38d2cb66 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -36,6 +36,7 @@ extern char **environ; #include "target_os_signal.h" #include "target.h" #include "exec/gdbstub.h" +#include "exec/page-prot-common.h" #include "qemu/clang-tsa.h" #include "qemu-os.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5b75d04ff6..881288a4de 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -19,6 +19,7 @@ #ifndef CPU_ALL_H #define CPU_ALL_H +#include "exec/page-prot-common.h" #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" @@ -165,40 +166,6 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying code) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleared. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0100 -#endif -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - -/* - * For linux-user, indicates that the page is mapped with the same semantics - * in both guest and host. - */ -#define PAGE_PASSTHROUGH 0x0800 - #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/include/exec/page-prot-common.h b/include/exec/page-prot-common.h new file mode 100644 index 0000000000..a38157e8b9 --- /dev/null +++ b/include/exec/page-prot-common.h @@ -0,0 +1,38 @@ +#ifndef EXEC_PAGE_PROT_COMMON_H +#define EXEC_PAGE_PROT_COMMON_H + +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying code) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) +/* FIXME: Code that sets/uses this is broken and needs to go away. */ +#define PAGE_RESERVED 0x0100 +#endif +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semantics + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + +#endif diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 6c8835fbcb..02783cca33 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -15,6 +15,7 @@ #endif #include "exec/cpu-defs.h" +#include "exec/page-prot-common.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea5c8660dc..c14012e07d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/page-prot-common.h" #include "qapi/qapi-types-common.h" #ifdef TARGET_AARCH64 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 5b20ecbd33..6bcfbcbed8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -19,6 +19,7 @@ #define PPC_INTERNAL_H #include "hw/registerfields.h" +#include "exec/page-prot-common.h" /* PM instructions */ typedef enum { diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 4c768aa5cc..1a3fd8f65b 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/page-prot-common.h" + /* Radix Quadrants */ #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF #define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c4500d3261..db154fe5ff 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -21,6 +21,7 @@ #include "qemu/main-loop.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index da39a43bd8..717e31e602 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/log.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "sysemu/tcg.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2575f0842f..5ce602b8d6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "qemu/rcu.h" #include "exec/cpu_ldst.h" #include "exec/translate-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 3ef11b2807..deb384605e 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" +#include "exec/page-prot-common.h" #include "qemu.h" diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..faf2062123 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu.h" +#include "exec/page-prot-common.h" #include "gdbstub/user.h" #include "signal-common.h" #include "trace.h" diff --git a/cpu-target.c b/cpu-target.c index 997ca2e846..d1953ec037 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "exec/target_page.h" +#include "exec/page-prot-common.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index a189942de4..45a215be6d 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -15,6 +15,7 @@ #include "qemu/units.h" #include "qemu/datadir.h" #include "qemu/error-report.h" +#include "exec/page-prot-common.h" #include "net/net.h" #include "hw/pci/pci.h" #include "hw/boards.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 1e615b8d35..ffe467fb16 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -21,6 +21,7 @@ #include "kvm_ppc.h" #include "sysemu/device_tree.h" #include "sysemu/block-backend.h" +#include "exec/page-prot-common.h" #include "hw/loader.h" #include "elf.h" #include "exec/memory.h" diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index d02f330650..e2da13c064 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/datadir.h" #include "qemu/units.h" +#include "exec/page-prot-common.h" #include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b404117ff3..0d05daea91 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "exec/page-prot-common.h" #include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f9e9ac1760..11c45ab293 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -7,6 +7,7 @@ #include "qemu.h" #include "exec/user/guest-base.h" +#include "exec/page-prot-common.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 96c9433e27..d37803fc8c 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -20,6 +20,7 @@ #include #include "trace.h" #include "exec/log.h" +#include "exec/page-prot-common.h" #include "qemu.h" #include "user-internals.h" #include "user-mmap.h" diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index da77ede76b..03434abe3b 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -22,6 +22,7 @@ #include "user-internals.h" #include "cpu_loop-common.h" #include "signal-common.h" +#include "exec/page-prot-common.h" void cpu_loop(CPUNios2State *env) { diff --git a/linux-user/signal.c b/linux-user/signal.c index b35d1e512f..50cba136db 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "gdbstub/user.h" +#include "exec/page-prot-common.h" #include "hw/core/tcg-cpu-ops.h" #include diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e384e14248..3d2467d7c8 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -25,6 +25,7 @@ #include "qemu/plugin.h" #include "tcg/startup.h" #include "target_mman.h" +#include "exec/page-prot-common.h" #include #include #include diff --git a/system/physmem.c b/system/physmem.c index 4bdb3d0592..0bea47b5d2 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -31,6 +31,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/target_page.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..ea7a769644 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1762b058ae..5eca492db4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -11,6 +11,7 @@ #include "qemu/range.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a26adb75aa..1198b32929 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -16,6 +16,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ffb8ea1c34..47f512e6c6 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f006d152cc..7713b7a4d4 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..62758b00ed 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b574ec6e5b..dee485419d 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "mmu.h" #ifdef DEBUG diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 08abd1a9f9..0d78e273f6 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..7e3867e4aa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 5b86f439ad..a3bf3b7292 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "tcg/helper-tcg.h" typedef struct TranslateParams { diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index 449043c68b..7f0e413e1e 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -13,6 +13,7 @@ #include "internals.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "cpu-csr.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68..7a69c4a28d 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "gdbstub/helpers.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..e4ce57560d 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/host-utils.h" #include "exec/log.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..c0b0844f71 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" static unsigned int tlb_decode_size(unsigned int f) { diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..7ac51c6019 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "../internal.h" static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 4ede904800..d0cb46bd1b 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bb3b09e5a7..b64caa11f6 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index d9b690b78e..da7f20cc07 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "mmu.h" #include "exec/helper-proto.h" #include "trace/trace-target_nios2.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 603c26715e..6ca7cc023e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3976416840..da446632c9 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "internal.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d645c0bb94..1633a0e5d0 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -21,6 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 5823e039e6..13f5ed7fb7 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6ca5d12207..83a91a92ea 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f87d35379a..6368dceb16 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7e23b34f4..565e6614d9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "internals.h" #include "pmu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 162e88a90a..59f4c3d481 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "trace.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..968bff34f2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9cc9d9d15e..6cc3173a1e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index fbb2f1b4d4..0b2240e39a 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -24,6 +24,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "trace.h" #include "hw/hw.h" #include "hw/s390x/storage-keys.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 84103251b9..2a8ee4df6b 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "hw/core/tcg-cpu-ops.h" #include "qemu/int128.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..c9f41d1e2e 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..078e25e363 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..e723868148 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/qemu-print.h" #include "trace.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7e5da3cb23..e736630a79 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,6 +20,7 @@ #include "hw/registerfields.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 12552a3347..d7611f1168 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 496754ba57..a9048ad6ac 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -28,6 +28,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/page-prot-common.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "qemu/atomic.h" From patchwork Mon Dec 11 21:20:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 752537 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1548769wrs; Mon, 11 Dec 2023 13:27:09 -0800 (PST) X-Google-Smtp-Source: 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Mon, 11 Dec 2023 13:23:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , Peter Xu , Liu Zhiwei , Peter Maydell , Mark Cave-Ayland , Eduardo Habkost , qemu-arm@nongnu.org, Paolo Bonzini , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-riscv@nongnu.org, David Hildenbrand , Warner Losh , Claudio Fontana , Brian Cain , Daniel Henrique Barboza , Richard Henderson , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao Subject: [PATCH 24/24] target: Restrict 'sysemu/reset.h' to system emulation Date: Mon, 11 Dec 2023 22:20:01 +0100 Message-ID: <20231211212003.21686-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211212003.21686-1-philmd@linaro.org> References: <20231211212003.21686-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org vCPU "reset" is only possible with system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Song Gao --- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index dfb96217ad..17b6962d43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,7 +24,6 @@ #include "qemu/hw-version.h" #include "cpu.h" #include "tcg/helper-tcg.h" -#include "sysemu/reset.h" #include "sysemu/hvf.h" #include "hvf/hvf-i386.h" #include "kvm/kvm_i386.h" @@ -37,6 +36,7 @@ #include "hw/qdev-properties.h" #include "hw/i386/topology.h" #ifndef CONFIG_USER_ONLY +#include "sysemu/reset.h" #include "qapi/qapi-commands-machine-target.h" #include "exec/address-spaces.h" #include "hw/boards.h" diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fc075952e6..b26187dfde 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -17,7 +17,9 @@ #include "internals.h" #include "fpu/softfloat-helpers.h" #include "cpu-csr.h" +#ifndef CONFIG_USER_ONLY #include "sysemu/reset.h" +#endif #include "tcg/tcg.h" #include "vec.h"