From patchwork Tue Jan 2 05:17:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759721 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F262106 for ; Tue, 2 Jan 2024 05:17:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YNpYQWr7" Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2ccc6e509c8so53400241fa.0 for ; Mon, 01 Jan 2024 21:17:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704172649; x=1704777449; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fPwf5mMASUhFtnDK4+mUIJwZeVNmPGTZR6zF8QblZ8o=; b=YNpYQWr7IL4hOaU5yxVIdTPptESp3yMTxaK1uYWg1wJSu5BEE1mJtZsd6lXDa+iv2v IKQHp0HCfXeQUlJhYnM50nTrCcFT38EzFI/brB9yF+O4qOZXNSIVatlePpf7J0FC2OD2 s/01+OVVyFxmX2pA7P66A3i/wAQ9VbHKhd0AbwoHccFKr+z0HxypFi4BktPVd11jvv6t aIPwG3ebXiUup//ETMRwN6w8jtPUPWl/wvoZij/W0ZCquk1dmWjE2MydfDoJZI5isBRd BqxlZ8hSnsDypNZ6RZiDX7K4/E6zBLBw7H3ES952yPgAa50Qk4me77PHrnAF7WIOSPQw JDpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704172649; x=1704777449; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fPwf5mMASUhFtnDK4+mUIJwZeVNmPGTZR6zF8QblZ8o=; b=ljizRkTP8xxIXi7oUfPkjcKpDSyQLhBlaJ1KTHVe8P7Nd+YOGHe+xCyvc3wLWNiC0d 3PLNWM9UVA8RuRDRqTMoWMrkUo5GUuYQKl0gZSvBDZxSzUt+ILG8LW6nnO0U6/yaWZij LzYt1p6fsCO5fXon3zwVUCG2Dkf1fU+Bj09prlXvddMg0DqFnNvEZpuQiLzZLbMJ+knl lpHYgplSfDMDYzQsvyEj3nuF6/EEdnzmVdl8HJvd5DyVEdSXgGrX+zE6ukLbezE8kud/ ZlbC+m/PLP3JxNgNx6+hI7CzJPF0qTFUBbBxvlEPLekSUXPW5F64LTUv0u13murkQcpu xKcQ== X-Gm-Message-State: AOJu0YxTNnV2NlxkPbE6BjA8fOrsN7lAbQm2QPOp3JAk9YA+Pl71eL+5 rmIHcjPREGg4/jREUN/DFzlQglgoWSeTbqo1cAzrw4X232+mOQ== X-Google-Smtp-Source: AGHT+IGP2a3jv25ft1O7cKwbk2WYAreFkcKjV4s03h932dx8uphgz5a1GimK4cicrDURdjPTCu0j4g== X-Received: by 2002:a05:6512:10ca:b0:50e:6a65:fa97 with SMTP id k10-20020a05651210ca00b0050e6a65fa97mr11257535lfg.33.1704172648329; Mon, 01 Jan 2024 21:17:28 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:27 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:21 +0200 Subject: [PATCH v7 01/22] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-1-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rob Herring X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5475; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Rrl8DtWc9AmZbJUOzG7UFbQ4ctK1eNIS/E5EO9aSnJA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xjUAq+5V4Wav7GyfrgtpfPAnAoRabcrZfXm 1D3yp5HU/mJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcYwAKCRCLPIo+Aiko 1a3kB/9eOTG4L/XtFSEHGCYu7J6fxIb05v6BMr0xre4ItctmDeO9R1WBnT9F7qvXCpIGwCc2z1S IJGstmETrCzba+dbZMYXpnmaX5xlfapylIGM7jGVtxWCcAKIGDezf7nBE20vGQS0P+aTOqyzfsr SQTbJIj+1wixzh3rjKiIbSH8xQ+B2uoQxJVkiYsYJZ5lBxyjTr/VfqEBnWW99PIs3efwMlJhnDt ASOJCYhgftnzq3vZvDVHI5JvhGNEdNIBwgknSRX3oVqVHTK+DNfgcFMs3bj2wPQ0wWC31KGAqP/ mqpkCs0j4aL0s+/HVgf8Nxh5ZG6tHkvOFUk9B6+ElqfgamZ/ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. The regulator property is retained as is. It will be changed in the later patches. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ---------------------- .../soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++--- 2 files changed, 20 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 64% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..84b3f01d590c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,25 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: @@ -34,8 +41,15 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + type: boolean + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible From patchwork Tue Jan 2 05:17:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759450 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4751B23AD for ; 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Mon, 01 Jan 2024 21:17:29 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:28 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:22 +0200 Subject: [PATCH v7 02/22] dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-2-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1624; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=6seBHQpdQthfiGxSf/xd1qZ7pEbCXNhrQ7ROvS0olF0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xjy3ovISs7HIkTtLCBZJAdKtskDPCJ378hp fmmCa9oojuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcYwAKCRCLPIo+Aiko 1ShDB/49KRDWmMLGG76SIc7wmOFsbA8X2E7Wx2ZIb4SXpJzhOsRh0moBeNCw91cLTkfBHkvu6LG aG3rDRZNJj7IReL6f2Q6jiGROWjI3A+9TpbclpJv8wnPI4LOWhCoSfEI8ymOqWaiy90bbAFbu3K Yy/uFFH+z/y2BdxE6BE+xKcgCnjQmEOOAucPTUdARy9Vu1DFZLAeB+KD32fRMNsGTeholAxV/kE 2TR5LY1fSGsYcc8y2ycN7Ubypw0Y9KVt/SKgc+PCoJvq/15//QHW0XTq+SrKToNJnP03S3WkbLL PRV78B8sQpFpPZnm4RmPQGxdrDmYUrgxRJPrPVVXAc9jA5CF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Define compatible strings for SAW2 units present on MSM8960, IPQ4019 and IPQ8064. There is no need to include SAW version into the compat string, so just use the SoC and SAW2 kind. Also add missing L2 SAW2 compatibles for MSM8974 and APQ8084, they follow the existing CPU SAW2 strings. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..2178fea37b8c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -25,6 +25,9 @@ properties: compatible: items: - enum: + - qcom,ipq4019-saw2-cpu + - qcom,ipq4019-saw2-l2 + - qcom,ipq8064-saw2-cpu - qcom,sdm660-gold-saw2-v4.1-l2 - qcom,sdm660-silver-saw2-v4.1-l2 - qcom,msm8998-gold-saw2-v4.1-l2 @@ -33,10 +36,13 @@ properties: - qcom,msm8916-saw2-v3.0-cpu - qcom,msm8939-saw2-v3.0-cpu - qcom,msm8226-saw2-v2.1-cpu + - qcom,msm8960-saw2-cpu - qcom,msm8974-saw2-v2.1-cpu + - qcom,msm8974-saw2-v2.1-l2 - qcom,msm8976-gold-saw2-v2.3-l2 - qcom,msm8976-silver-saw2-v2.3-l2 - qcom,apq8084-saw2-v2.1-cpu + - qcom,apq8084-saw2-v2.1-l2 - qcom,apq8064-saw2-v1.1-cpu - const: qcom,saw2 From patchwork Tue Jan 2 05:17:23 2024 Content-Type: text/plain; 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Mon, 01 Jan 2024 21:17:29 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:29 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:23 +0200 Subject: [PATCH v7 03/22] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-3-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rob Herring X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 2178fea37b8c..f9306f2a6e99 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -53,7 +53,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -102,4 +102,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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The CPUidle driver doesn't use them at all. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 20 ++++++++++++++++++++ include/soc/qcom/spm.h | 23 +---------------------- 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2f0b1bfe7658..b15435f7cb0d 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -36,6 +36,26 @@ enum spm_reg { SPM_REG_NR, }; +#define MAX_PMIC_DATA 2 +#define MAX_SEQ_DATA 64 + +struct spm_reg_data { + const u16 *reg_offset; + u32 spm_cfg; + u32 spm_dly; + u32 pmic_dly; + u32 pmic_data[MAX_PMIC_DATA]; + u32 avs_ctl; + u32 avs_limit; + u8 seq[MAX_SEQ_DATA]; + u8 start_index[PM_SLEEP_MODE_NR]; +}; + +struct spm_driver_data { + void __iomem *reg_base; + const struct spm_reg_data *reg_data; +}; + static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = { [SPM_REG_AVS_CTL] = 0x904, [SPM_REG_AVS_LIMIT] = 0x908, diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..5b263c685812 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -7,11 +7,6 @@ #ifndef __SPM_H__ #define __SPM_H__ -#include - -#define MAX_PMIC_DATA 2 -#define MAX_SEQ_DATA 64 - enum pm_sleep_mode { PM_SLEEP_MODE_STBY, PM_SLEEP_MODE_RET, @@ -20,23 +15,7 @@ enum pm_sleep_mode { PM_SLEEP_MODE_NR, }; -struct spm_reg_data { - const u16 *reg_offset; - u32 spm_cfg; - u32 spm_dly; - u32 pmic_dly; - u32 pmic_data[MAX_PMIC_DATA]; - u32 avs_ctl; - u32 avs_limit; - u8 seq[MAX_SEQ_DATA]; - u8 start_index[PM_SLEEP_MODE_NR]; -}; - -struct spm_driver_data { - void __iomem *reg_base; - const struct spm_reg_data *reg_data; -}; - +struct spm_driver_data; void spm_set_low_power_mode(struct spm_driver_data *drv, enum pm_sleep_mode mode); From patchwork Tue Jan 2 05:17:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759448 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6770C15D5 for ; Tue, 2 Jan 2024 05:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jan 2024 21:17:31 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:30 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:25 +0200 Subject: [PATCH v7 05/22] soc: qcom: spm: add support for voltage regulator Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-5-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9725; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=kw0nF1B4E0+psReswT0aVUw4ujS4UEg+s5VY+LVJvIk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xjVWklIoGiqKnan1HprwEDufSvyZVRuNKZU Wb4faY02TmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcYwAKCRCLPIo+Aiko 1eEvB/0aB4h/5PfR0W89IB8U3whoCkFWnzqvMyZeamHa5Q1bZZ/TfEC83V/fFiVpe4P1lMWD7pS SRBvmUWNvDOBjAkF1kVEV0BPVHobDbvcHaPwaiwaLw7wEB8Ex6Ce184S9hpQXd6sbRpF3hJrGol iZt2B5mSQXPywabwxyc2tpzDhu+NU4BB4Re7+AQ7ESnmqR5FZr5dGerf4HSvuTEdEXV5p+d8Q42 t8eYwv0D3tEkvR3E9PgEI2fMs5yGDlh3+jzutmuWMz6Xo32b6hmC0YiGsa3Ph8ubhJRJQc93Bmc YSH6DZrzzU4OzzJExUtk4XGqoJSPhzsZKvUMisyx+Nv79rlC X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov Acked-by: Konrad Dybcio --- drivers/soc/qcom/spm.c | 234 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 229 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index b15435f7cb0d..5eefaec72a13 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -6,20 +6,40 @@ * SAW power controller driver */ -#include +#include +#include #include #include +#include +#include +#include #include -#include #include -#include #include +#include +#include + +#include + #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +/* These registers might be specific to SPM 1.1 */ +#define SPM_VCTL_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0) +#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16) + +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17) +#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -29,10 +49,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -49,11 +71,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = { @@ -189,6 +220,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -196,7 +231,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -207,6 +247,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -258,6 +302,185 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vctl, data0, data1, avs_ctl, sts; + unsigned int vlevel, volt_sel; + bool avs_enabled; + + volt_sel = drv->volt_sel; + vlevel = volt_sel | 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); + data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = volt_sel; + unsigned int min_avs = max(max_avs, 4U) - 4; + + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, voltage setting is not supported */ + + return -EOPNOTSUPP; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + ret = spm_get_cpu(dev); + if (ret < 0) + return ret; + + drv->reg_cpu = ret; + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -308,6 +531,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -335,7 +559,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { From patchwork Tue Jan 2 05:17:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759720 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 002612574 for ; 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Mon, 01 Jan 2024 21:17:31 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:31 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:26 +0200 Subject: [PATCH v7 06/22] ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-6-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This is is to distinguish the SAW2 units related to L2 cache and the CPU cores. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 2b1f9d0fb510..8d630db4005b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -650,7 +650,7 @@ saw3: power-controller@f90b9000 { }; saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; }; From patchwork Tue Jan 2 05:17:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759447 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C7B446BC for ; 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This is is to distinguish the SAW2 units related to L2 cache and the CPU cores. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index b1413983787c..16ee0baac27c 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -347,7 +347,7 @@ apcs: syscon@f9011000 { }; saw_l2: power-controller@f9012000 { - compatible = "qcom,saw2"; + compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; }; From patchwork Tue Jan 2 05:17:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759719 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37FD9569C for ; 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Mon, 01 Jan 2024 21:17:33 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:32 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:28 +0200 Subject: [PATCH v7 08/22] ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-8-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1001; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=E/5jXH5aENk4VUb+Qa3GlUcJJdi0cLtkCh52Lv9dMs8=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+rkOSnFPMc2m8iuvN348aWWbeRyn39fenW/unwWLjyp4 9VVPyO5k9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQAT6bVm/x8yNT+PKy3c95yy d7vM/QPCcb5hU99Z1waJLTet68oyFNsvskvuWnr57keOrFnpLv1dzJPVg+v33ayY+2NrQzNjppj cP15r5lyNdY3JW16vv7myYdH2P882rYhdMoXRoPeHjZaD3ysvj5+LtSd1RZTN5Z0695LgjoLJzh vu+XALPORX7fQS7Qh49G3e081pVxW+hNVM8+avllbZ+PzE3QsbHnOfsbhy90hsxovIu54fk/fP/ hK3WfdXrfSqdXfEjZextUp71Eg6J/lObuTRuJf97pmY9n9NhhvG6SoCQdkci970CqnueCDwha1I oDigPynS7PaijZ8Kn7DGL3adxrPwcylLDYP9rXthrl+LAQ== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is no such thing as a generic 'SAW2' device. Use device-specific compatible strings to describe the SAW2 devices. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index f420740e068e..5099a161f7f9 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -221,13 +221,13 @@ acc1: clock-controller@2098000 { }; saw0: regulator@2089000 { - compatible = "qcom,saw2"; + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; saw1: regulator@2099000 { - compatible = "qcom,saw2"; + compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; From patchwork Tue Jan 2 05:17:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759446 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E555079E5 for ; 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Mon, 01 Jan 2024 21:17:33 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:33 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:29 +0200 Subject: [PATCH v7 09/22] ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-9-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1572; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=0zO90aeFdkE8V44pIeboxfUKrEZ0QGnGFIHf5D/o3yg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xk5sN46hSvE/lzgH0D6s2dqO9OuyCt4hb2R 2JgR8xpncuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZAAKCRCLPIo+Aiko 1W3+B/9QrS5lGfRNIR/A46/9xhKZoFDnsPLRJUN/dnt+LVDHKY9T06DQO3wp6JhZAXCYfkuWFd2 jor+S/IXAN76wG5fyNVTo/GUTBDW65BrrbTkSOtQCWqiDSUwGb0R1MCB2ZX+1/AcK35Fvg3hWoA tKdnDvglsf4gBYK4VhPGjxmBynvCkua3lM36MVU4uR9v6ob3zCLELsHv1qZ/Zs96xclsVyX1ERY yQOJB8P+J4aAZDD0u4sD4o+9WbaylTP5RAee4LrLj9fSXFiW8f7FZVP6f9RU9QQc02EQhUXhh/m cR8ud2ZMJYnirNn8znSrk3QGrP9xs687mAxFc1TeFot2zQ3f X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is no such thing as a generic 'SAW2' device. Use device-specific compatible strings to describe the SAW2 devices. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f989bd741cd1..948c6fd91f62 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -351,31 +351,31 @@ acc3: power-manager@b0b8000 { }; saw0: regulator@b089000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw1: regulator@b099000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw2: regulator@b0a9000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw3: regulator@b0b9000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; regulator; }; saw_l2: regulator@b012000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; reg = <0xb012000 0x1000>; regulator; }; From patchwork Tue Jan 2 05:17:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759718 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D2A5CA6F for ; Tue, 2 Jan 2024 05:17:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UjixGlLR" Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-50e7b273352so5724807e87.1 for ; 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a=openpgp-sha256; l=1060; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=EgrF1ouyUBfwhdgqqoi+Ov9zEE1VZZvsISi69jo6W4c=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xk/kKmNMQp15abahT3pMp/OORIApd5NX4BQ HvlpA5qQa6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZAAKCRCLPIo+Aiko 1W+bB/95XyxFyqVBxx06uIFR+z28eC9BDFgPkBA1XEg6Kd+/FZiOKpeJh5WuapsPBrc+5B5PP+I DZa7fXO5qPFD16shTUdC500pK7wUbZUIcFvyS5uBOj/+zV9zHRNe1TjDQx0z+9FnFmxiGKT8U3u 2nsO/PsePnOqP2FTVZKfGjyK2qX2PWB/oMMAQGOb/IgpRmetdPEsWHFnkmNVxi+M4fbfrwZitKt m2jiaU5ZkeGBRtnKdIawcezj9iU+uN8848mcbAAbM7P5FrQjRPrNQqI2v/9u8fKZeztYkZEc/bl eJfF9zI/oJ6KWJ3bJFCd4jjQLTBWmAz/uLioeVDZjJOSlaL4 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A There is no such thing as a generic 'SAW2' device. Use device-specific compatible strings to describe the SAW2 devices. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6a7f4dd0f775..0621853c24dd 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -587,7 +587,7 @@ acc0: clock-controller@2088000 { }; saw0: regulator@2089000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; @@ -602,7 +602,7 @@ acc1: clock-controller@2098000 { }; saw1: regulator@2099000 { - compatible = "qcom,saw2"; + compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; From patchwork Tue Jan 2 05:17:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759717 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6C6E46BC for ; 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Mon, 01 Jan 2024 21:17:34 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:34 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:31 +0200 Subject: [PATCH v7 11/22] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-11-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 3faf57035d54..3066ee49daa7 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -365,25 +365,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Tue Jan 2 05:17:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759444 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99C38DF5E for ; Tue, 2 Jan 2024 05:17:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="k65YIjL7" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-50e741123acso6925005e87.0 for ; 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Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8d630db4005b..6fdf300ef65d 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -629,27 +629,27 @@ frame@f9028000 { }; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; - saw_l2: power-controller@f9012000 { + saw_l2: power-manager@f9012000 { compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; From patchwork Tue Jan 2 05:17:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759716 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37B44EAE5 for ; Tue, 2 Jan 2024 05:17:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jan 2024 21:17:36 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:35 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:33 +0200 Subject: [PATCH v7 13/22] ARM: dts: qcom: msm8960: rename SAW nodes to power-manager Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-13-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1136; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZrJulsqUXOM07uJN9CBFq3F4bZViSrScM3/fZ3K6RFQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xl1qhaSVFkPemyNXciQqfqnv5wQiMjHINtL ixMbndfFQyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZQAKCRCLPIo+Aiko 1RhSCACRGn7IY0ALZTteCxXCN1z14qVfEaOo5EaASS14U6XgcqeyGsUiHLU0hdeTRoy2+O85Ieq 5b5hIPkVnj48LhTQNlRGtCARd3CfVBmHkGLy+w14ajHUYzweiduaGZU3KDdW+j0hSsG6BT2t8aH idlpIXFvd1lAHjGg/qriP0G7+fBTn/FZ13EtTPceX9yBCwIcVpRu8Eeu2B6gWS0gBA8PWGjmEqK IDQ585V3K1ETQUFB0HxZGO1oHPZzqlwtnrKfA3a3ho8+jF/ri2GduARsRjjptiUEWCcq21o0EZ+ rh/GS3EnBQHjz75y8N1LmQ618dT+avSaW7Q3c/ws29+xB6bg X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 device is not a regulator. It is a frontend to the PMIC, which handles voltage control, automatic voltage scaling and low-power states, Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 5099a161f7f9..84c3d3ac63b9 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -220,13 +220,13 @@ acc1: clock-controller@2098000 { #clock-cells = <0>; }; - saw0: regulator@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: regulator@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Tue Jan 2 05:17:34 2024 Content-Type: text/plain; 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Mon, 01 Jan 2024 21:17:36 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:36 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:34 +0200 Subject: [PATCH v7 14/22] ARM: dts: qcom: msm8974: rename SAW nodes to power-manager Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-14-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 16ee0baac27c..e2008a8b89e1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -346,7 +346,7 @@ apcs: syscon@f9011000 { reg = <0xf9011000 0x1000>; }; - saw_l2: power-controller@f9012000 { + saw_l2: power-manager@f9012000 { compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; @@ -424,7 +424,7 @@ acc0: power-manager@f9088000 { reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - saw0: power-controller@f9089000 { + saw0: power-manager@f9089000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; }; @@ -434,7 +434,7 @@ acc1: power-manager@f9098000 { reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - saw1: power-controller@f9099000 { + saw1: power-manager@f9099000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; }; @@ -444,7 +444,7 @@ acc2: power-manager@f90a8000 { reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - saw2: power-controller@f90a9000 { + saw2: power-manager@f90a9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; }; @@ -454,7 +454,7 @@ acc3: power-manager@f90b8000 { reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - saw3: power-controller@f90b9000 { + saw3: power-manager@f90b9000 { compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; }; From patchwork Tue Jan 2 05:17:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759715 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74707FBEB for ; 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Mon, 01 Jan 2024 21:17:37 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:37 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:35 +0200 Subject: [PATCH v7 15/22] ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-15-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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It is a frontend to the PMIC, which handles voltage control, automatic voltage scaling and low-power states, Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 948c6fd91f62..cc94942db468 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -350,31 +350,31 @@ acc3: power-manager@b0b8000 { reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; - saw0: regulator@b089000 { + saw0: power-manager@b089000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; regulator; }; - saw1: regulator@b099000 { + saw1: power-manager@b099000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; regulator; }; - saw2: regulator@b0a9000 { + saw2: power-manager@b0a9000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; regulator; }; - saw3: regulator@b0b9000 { + saw3: power-manager@b0b9000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; regulator; }; - saw_l2: regulator@b012000 { + saw_l2: power-manager@b012000 { compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; reg = <0xb012000 0x1000>; regulator; From patchwork Tue Jan 2 05:17:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759442 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19405FC1D for ; Tue, 2 Jan 2024 05:17:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jan 2024 21:17:38 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:37 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:36 +0200 Subject: [PATCH v7 16/22] ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-16-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1213; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=2cuZin9s0YRpL0zAWyoOjhE4ZNwfyDKxmXZtrb98axM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xl8J3AZsVN1vvBTmM1EVxCy2x8IWoCjCNAn jwCeVzpC0+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZQAKCRCLPIo+Aiko 1ahoCACKzGQAg4bSRNN/jdXwpx83VTbHBy3YIX+VOZalqgZ47vR5ikBK2ZnnOxCcxzi0vQtra8q 6QdtFXyFFm2oRV1kGndXRoN8UPJvLGbVzgIfnH+Vbs9kmTqpfr7NgVm9RNZmpkCUsTL7QulMgqi 6emliMdIa9BCmWCTAJiDT+5/7BPVepZM+NrPxY3935u3bJFy1QRR9YSRCajUDgq365husUzOMBY /sas0WGLzB+m4CnOPwiLK0go41ctmfGMl3v/8ullG3JGxrYaWwSvEpiGZx6t02zUMCgZ+Ud+utj z9VaPfsVpKbSO9IE4bIdgUR4Wy6Yo0G9m5t51cAx1+KK+sUR X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 device is not a regulator. It is a frontend to the PMIC, which handles voltage control, automatic voltage scaling and low-power states, Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,saw2.yaml Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 0621853c24dd..4b35b1fd4b58 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -586,7 +586,7 @@ acc0: clock-controller@2088000 { #clock-cells = <0>; }; - saw0: regulator@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; @@ -601,7 +601,7 @@ acc1: clock-controller@2098000 { #clock-cells = <0>; }; - saw1: regulator@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Tue Jan 2 05:17:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759714 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B138B10FC for ; Tue, 2 Jan 2024 05:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sihXvgsw" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-50e80d14404so4778503e87.1 for ; Mon, 01 Jan 2024 21:17:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Mon, 01 Jan 2024 21:17:38 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:38 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:37 +0200 Subject: [PATCH v7 17/22] ARM: dts: qcom: apq8064: declare SAW2 regulators Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-17-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1968; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=HGYqjIJyAD2GI/gXSq7W4K6RgkmqlA4A/at5d+w6bVs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xlXn3k4uN5ZQvh0l66H+bmn4ilr4RrDKOz4 AyYZ1y77reJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZQAKCRCLPIo+Aiko 1VAuB/0VEiepNlkGn/4TrJBSQmLhw8eSqmdu8d1tuWQ9s8d/IOP/DyFfaeEaKSfE0QE4M5reTF2 /8BT2UygBIRTKzBzQ+9AWaRzIA697H8grZ1tPDBeof3wuwj2DH+kzYUmaTwaET09XunitZz++Ws Xn477PbbjoxeasqJKZdcAgfJKN5kwQ6uLWTNKa/VPWzaPj0b1sq7BvzBpPLTre8nnbK4QQ6xq1m fdyfgvpG0UL4aNw4mI/WEK4H2ja0qo0JLfEau/blDsheQzu9tWkgthobcsUtiF+cx4BBuGuyVZC TNp7FWzSRAoPMVVi+J8MmbZjtQWJs8GW/mKXHx4n8D1sBGyM X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 3066ee49daa7..d1cbd2248558 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -368,25 +368,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Tue Jan 2 05:17:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759441 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 682F0125CA for ; Tue, 2 Jan 2024 05:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 01 Jan 2024 21:17:39 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:39 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:38 +0200 Subject: [PATCH v7 18/22] ARM: dts: qcom: msm8960: declare SAW2 regulators Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-18-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1323; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=xv2z1mRLciwpFcRbJRoxzOojlPfXpF0Q42hsn36SmXU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xmoyNfziZAKt/pWZxSQU8cGTJKv+aT+OaC0 CdICTZnPzKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZgAKCRCLPIo+Aiko 1cRUCACFC6N9EFQ7FYhRYtRRbIMtgsi1JK5KlJ/1rQdqkae16orOmJy9evmJAc91hSmBI2K+gYm +NgMUJdJ7xqboZbTaE+IGLr0YOPCwMFX9/rUDsVbZPb5vuPoeruMe8X0UTZ0UWq/NAy/CbF/JyR UsPOJ9nXRNA+1Z/RJkWJYalE0Qz7HgQ6Eh42jEM8YG5hgQbFUCP4gT7gwzhd5S04Elc+7aoOmgj ymF21jhbm6ZJ2X+uQMuBv/dssVbgZPxX33JkInNZf+vPAgsnDllQcmNhMTsiAyNiO03iup9OJWU HZz8/nL+33KLnckA1SjW5wC89au6bf1Q3iDKs7b+T5d3wbX5 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 84c3d3ac63b9..e02e56a43fd5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -223,13 +223,21 @@ acc1: clock-controller@2098000 { saw0: power-manager@2089000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Tue Jan 2 05:17:39 2024 Content-Type: text/plain; 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Mon, 01 Jan 2024 21:17:39 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:39 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:39 +0200 Subject: [PATCH v7 19/22] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-19-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 6fdf300ef65d..8204e64d9a97 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -652,7 +652,6 @@ saw3: power-manager@f90b9000 { saw_l2: power-manager@f9012000 { compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Tue Jan 2 05:17:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759440 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93F94110F for ; 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Mon, 01 Jan 2024 21:17:40 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:40 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:40 +0200 Subject: [PATCH v7 20/22] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-20-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index e2008a8b89e1..ec27260fe3d4 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -349,7 +349,6 @@ apcs: syscon@f9011000 { saw_l2: power-manager@f9012000 { compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; watchdog@f9017000 { From patchwork Tue Jan 2 05:17:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759712 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD9014AB2 for ; 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Mon, 01 Jan 2024 21:17:41 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id r25-20020ac252b9000000b0050e810689e5sm2081827lfm.33.2024.01.01.21.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jan 2024 21:17:40 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 02 Jan 2024 07:17:41 +0200 Subject: [PATCH v7 21/22] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-saw2-spm-regulator-v7-21-0472ec237f49@linaro.org> References: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> In-Reply-To: <20240102-saw2-spm-regulator-v7-0-0472ec237f49@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Andy Gross Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1632; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=NHhNf/ks6Y5CfOcj/nzqbisPorNP1bm9u5EEDmQhloM=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xmk2Ip6BztQ7L7+lgG1xICkrxo2Dxk9xn7r yGMgMYcppqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZgAKCRCLPIo+Aiko 1RHCB/4iosCin7n5la+ISCOixVQ14KFOEkZujUbw7iqXglROBsfa46X6bOnFkOp99zQ1SPXk+yW UvQ9CsmEidY9DElDWvxBhMkHJ2LGQ7/sjGa3MXMh+BVIkARSkI7zHmd3+S5mpxuLQ/oiP6ev+OJ SWEdefGCs4j9N0e2Ur8Kt35nvhH9f6fMW1sd9YzC2QHs3MHdv3Aifr5w6Npj0aKQPkqJzPhiw6n 9hr83rtuxp8w6Tx2WqQDki3mv3Rl230HFkHGKOMmGsFNJ5DjCPpaFosykUN1I+gHP9lzhYxO4x+ 8c+fXlv3B8OHMH9Q1+stQVnkZwXEbB0aQAtLG9bqiQUS+Ec2 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index cc94942db468..bcc7ceb648ff 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -353,31 +353,26 @@ acc3: power-manager@b0b8000 { saw0: power-manager@b089000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw1: power-manager@b099000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw2: power-manager@b0a9000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw3: power-manager@b0b9000 { compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw_l2: power-manager@b012000 { compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { From patchwork Tue Jan 2 05:17:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 759439 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB4114F83 for ; Tue, 2 Jan 2024 05:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sEzUY8rC" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-50e70b0b869so7304490e87.2 for ; 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a=openpgp-sha256; l=1234; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=YpeawRcLYR7ZI5q4HIcJ9e0JzMmiL7QMmrYvpwUTlT4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlk5xme/VAvuNw1xhSCUPMgP9oj/zqqecQbieKP 1t/8scUZbeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZZOcZgAKCRCLPIo+Aiko 1U4nB/kBMKPAQEDflvTBkWlR0RBvC0//as913ErvRA0/FL1iYlwKM6yYcKO91fVsngq6qWUBm/b yFKMa480fvrZu0f/1CHBWRYGC8FxG3JeRSRmompdJsJCLkSff8R19x54VaqXmymu1SzC+cqLtBS xDtPcAngwbzMLWEV+L1HinNyPgaNQ8Wznaz7Kv++ZFMDEpHS0K7qYN/aJwvAW+b6S8PrDzyfHux HYTPHW0kW1F0XTREy8zwL1WYus9+7exJYpt9fA6GYSaByr6NnIVzEEJu5oIOKM/f3z8u5z+FRA4 4CBhJUJhtQaAl4alKXGqnV/YF3LEdA5KwLlwvcHMM812FGJ0 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 4b35b1fd4b58..eb0eb2af6041 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 { saw0: power-manager@2089000 { compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 { saw1: power-manager@2099000 { compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 {