From patchwork Tue Sep 10 11:45:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 173514 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp5677998ilq; Tue, 10 Sep 2019 04:45:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwklqQ6kMHtqHFpBTFFMDML2pwkup7SzsBM7TBtIs7dVUN4TkzPLBQZW7FYxNuxGYvot1zq X-Received: by 2002:a50:fd95:: with SMTP id o21mr29676650edt.6.1568115945906; Tue, 10 Sep 2019 04:45:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568115945; cv=none; d=google.com; s=arc-20160816; b=xsv2yCPmFjb/b4+a5yAhwjqt/NjC8j6gWnNUFrmEl1ivQmIBZ5lACjfaHo2N00gKg2 I3zB7tDKC1SGyOZTfjjqejLz+DeR64Cf3bVqA/Brr4bFziW38yhA+H3PEoZ1zVazz15G haEKRr4fwtv4cZDDF4LGCfA4O8vWkEHiz/oDfVDYcxb04woWqB4Hkg+kOmcQqkCYE6nd uGbKjARcTAujUm3qXo9QXMo7ToTap8I9tPsZYwCCOaCmEC9LSd4xYN1BWSh3/7DH2lwS 8OrFjhGq5uc/sWijmw5Szk2p6oXDMvJZLlfurI2bI6TzHJ8/OJXPZxBiYWGljPxm8lWp j/uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oj1t9aK27h7kYmeJtRxpc+tY35M83uRPBJm+zMEvkzs=; b=vIm4zQZkKHbd+KHFs0/O8UE9FPezZUe2R66RdK8m/bVQyyt+tte1ReKu6kCl7aGXbq TfyFwQQsXv0hHtvMqdy9/gQE+jRZFX9ZcTP2sAqymdkzm0+lWH72INQ4c3R63wPMXzIO wc8FgkwWUD6gnNbwB2+0DlKEMQ58tLios2jOIIJh5Im+2dtXJWnEpOP5VGB8KR6FO8Zq 7A3tCHIbVq3zB9UyGwMDGQHVjjk9WqenwD1UE1r8IK4ighR+oBywjJPlmzjMST/7tWvX 5AU+xbFOOdcHHWn6vmdIaPVSFY0eO0fydIidWTHy0YuGD5N9+aPChHSeSPzwbk8oSjNy +BNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xhY4es2s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b11si10852735edx.222.2019.09.10.04.45.45; Tue, 10 Sep 2019 04:45:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xhY4es2s; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731500AbfIJLpn (ORCPT + 27 others); Tue, 10 Sep 2019 07:45:43 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41574 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731389AbfIJLpl (ORCPT ); Tue, 10 Sep 2019 07:45:41 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8ABjZYh130303; Tue, 10 Sep 2019 06:45:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568115935; bh=oj1t9aK27h7kYmeJtRxpc+tY35M83uRPBJm+zMEvkzs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xhY4es2sP9GJEKK2AZdZWSswZpwAbOEtHXfbgHYhxJTNGP+2JYkfypnvXd0Fq/84S NOyG7vS/LyLrz0oGoYMz6GoiMzxP2JK70ozW3zwkGKjlrswpv7d/W6WcGSy3UnDagR Q9X0OxRLBe+coZNZwDjIn2meeg4r5im5Dcuf24Uo= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8ABjZNr005985 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 10 Sep 2019 06:45:35 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 10 Sep 2019 06:45:32 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 10 Sep 2019 06:45:32 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8ABjRpJ119821; Tue, 10 Sep 2019 06:45:30 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v2 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array Date: Tue, 10 Sep 2019 14:45:57 +0300 Message-ID: <20190910114559.22810-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190910114559.22810-1-peter.ujfalusi@ti.com> References: <20190910114559.22810-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make the dma-channel-mask to be usable for controllers with more than 32 channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/dma-common.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/dma-common.yaml b/Documentation/devicetree/bindings/dma/dma-common.yaml index ed0a49a6f020..41460946be64 100644 --- a/Documentation/devicetree/bindings/dma/dma-common.yaml +++ b/Documentation/devicetree/bindings/dma/dma-common.yaml @@ -25,11 +25,19 @@ properties: Used to provide DMA controller specific information. dma-channel-mask: - $ref: /schemas/types.yaml#definitions/uint32 description: Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems = 1 + maxItems = 255 # Should be enough + - description: Mask of channels 0-31 + - description: Mask of channels 32-63 + ... + - description: Mask of chnanels X-(X+31) dma-channels: $ref: /schemas/types.yaml#definitions/uint32 From patchwork Tue Sep 10 11:45:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 173512 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp5677985ilq; Tue, 10 Sep 2019 04:45:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqzO2XbNNtX4hHWbE/Z6s0u8yzqsRjCpyIzUceAM/B9ZbxLxrynZUoJj2WEIP/esYU7Ic0Yz X-Received: by 2002:a05:6402:1e2:: with SMTP id i2mr30831393edy.56.1568115944990; Tue, 10 Sep 2019 04:45:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568115944; cv=none; d=google.com; s=arc-20160816; b=K/ven4Il+rioPhVY3IC6EKUq82xhQJLN3tEII7Fr2rnSPtYT/U97eBwm/OjmpWT3ZV f+xmZRYfxsjs6EOlFEZYUGMxCmQ06Qi/QBOLzUVUJnogXDhrdN9yX99ubrsEWjskVFPW eqUFGAW6N4ZMFnly6vlst3B3tUsU7AmP/MtFu6pE6D4/I6VOcAYHbkjhuQQJW9d+Oa4h 9pS1JehsVcRVfxVbZpwN5u2Dq9S3efEZBOfQlrUOWMXRhngWgoso0Sh6bQMwM3AO2dBa 90o2LIYGPpCfnnqMx6682ALEjrXe3ZBnEfIoxBNf/eW7Hzibw1UvMcaBXTpfALrbPneX tPVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ng9Cs8sOz+sU2Y/eAwCWJ2zVQwHbGtllOEtnh+KMP8E=; b=weR2pVUxLtQ116uefVlcCt1eq0PXITaJUIsalMnwWFq+XrGqOUv9aiBjqZhzcQwdAT pQH7B2osROQHAvCBKeQjOmylBByDWqqA20dNzzxvUlvEuZ5c8LGbj7Asf6s1IoKQZfNH 8T4FuFMhxos1kawSxRF5VQoq7KwY/VpGxWxqzfVAh2bOsOEahOvixUOkHFEbrAz1jMN9 XhLVhJtQgJSI7ofVfmpd6k8/9YNGnsLxk0khyRwM9k6FncOwPNCspJtw44h75B5UhSm1 hPZuKFb42zMNx5uyZ7Ppd20UCeVU6yDABmYhoD3GWbk36vir8KJfo7aQGmWIRSIhTqbJ qwpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Hl4soldC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b11si10852735edx.222.2019.09.10.04.45.44; Tue, 10 Sep 2019 04:45:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Hl4soldC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731384AbfIJLpk (ORCPT + 27 others); Tue, 10 Sep 2019 07:45:40 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:60760 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731205AbfIJLpj (ORCPT ); Tue, 10 Sep 2019 07:45:39 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8ABja1F081894; Tue, 10 Sep 2019 06:45:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1568115936; bh=ng9Cs8sOz+sU2Y/eAwCWJ2zVQwHbGtllOEtnh+KMP8E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Hl4soldCIUdr7LpYsNjwiTN44fRJxaGS0iPeQ8WWfppgPrV8LBU8zrp17Ay0OUof4 ftfMBmaBuO6xXEqeSZn1wbC7N/zcz5HcSW6GTa4bB1whaeCeB+TxTc4vBt2vwl7sip 2412jhCm8O2hvVMlRaoRJ4DF6cHUZksjHpi60GOk= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8ABjaRC088283 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 10 Sep 2019 06:45:36 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 10 Sep 2019 06:45:34 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 10 Sep 2019 06:45:34 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8ABjRpK119821; Tue, 10 Sep 2019 06:45:32 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v2 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA Date: Tue, 10 Sep 2019 14:45:58 +0300 Message-ID: <20190910114559.22810-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190910114559.22810-1-peter.ujfalusi@ti.com> References: <20190910114559.22810-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similarly to paRAM slots, channels can be used by other cores. The common dma-channel-mask property can be used for specifying the available channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/ti-edma.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 4bbc94d829c8..3c7736246354 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -42,6 +42,9 @@ Optional properties: - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by the driver, they are allocated to be used by for example the DSP. See example. +- dma-channel-mask: Mask of usable channels, see + Documentation/devicetree/bindings/dma/dma-common.yaml + ------------------------------------------------------------------------------ eDMA3 Transfer Controller @@ -91,6 +94,9 @@ edma: edma@49000000 { ti,edma-memcpy-channels = <20 21>; /* The following PaRAM slots are reserved: 35-44 and 100-109 */ ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + dma-channel-mask = <0xffffffff>, /* Channel 0-31 */ + <0xffffe007>; /* Channel 32-63 */ }; edma_tptc0: tptc@49800000 { From patchwork Tue Sep 10 11:45:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 173513 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp5677989ilq; Tue, 10 Sep 2019 04:45:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqwHYn+f6kdpuaKydLCoxIwTb9IWcgzwf87KAeAOBtgSaxF7PVdxkxkxtpRd+X64MvS6xJ/3 X-Received: by 2002:a50:ab0f:: with SMTP id s15mr16716564edc.119.1568115945432; Tue, 10 Sep 2019 04:45:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568115945; cv=none; d=google.com; s=arc-20160816; b=iBDo1rtXt/vnAofmYRCc6t3cKsM9AFaX+LE6Gzz6cKeSzkVn0r58O/mhjSMmQEPrDK Xg8WScXj3gnX+1vxTxMe8j+0adygXCPuxXeBZsY2NVHIrFIgi2zAZCngkzniJ6LMMYi7 rsXqBqaUacx8Rvfe/pphFzywU1evJlm+XVLDVXmcqb6p4eKb5Db0DHSALX/7u47k16oW SAE9t0MGPZCNFYKWe72iZRIGoPn3R977ggAdt54++XrLBf0J2DbtvV/DWOU6CtAd1Evs 2dR4nO4BT+pMsCFhj8t6Q3TBzL625zeVuSWEdtDVSxjPgJM023kafQomHEg1/6t/D1eX kCSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Xv9IdSYQH2Wyjdje4PEB2rgCyL+w8guQKyTJ3UYqNXA=; b=lbaHcIAKh8Zz4Gf5mmLh5fmFkb56d/cGiXevBHF5x7YdMaXohr5KDRxHAw8sNeHDWL c5oY9iYIFbTIPLdm91UHBHlV5BcsT/vo7yZBfmCwQaLhGFOKLEj34F3meiIOMET716xy LFhlzAzsPhtidCVn7NnCb+gpDvT1ySSVH90dwHUlLRVChnq1gJxzXOPuEEZE3q3jLGTA M4kvTuhdQhRP7aBKu7AOxfWCjia74U0OFAmiKONCJhxxCeZtoYm/GSLK+eh+rEWci7ES 8bowPsRvSMVcxKYeZzemfqg+LJ6o9D6eJuUdDoz1bqDPrsMevPXY4UvEkIRLHFM0paKc goCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gTpX58Gg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Handle the generic dma-channel-mask property to mark channels in a bitmap which can not be used by Linux and convert the legacy rsv_chans if it is provided by platform_data. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 59 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 6 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index ba7c4f07fcd6..03c9c6296006 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -260,6 +260,13 @@ struct edma_cc { */ unsigned long *slot_inuse; + /* + * For tracking reserved channels used by DSP. + * If the bit is cleared, the channel is allocated to be used by DSP + * and Linux must not touch it. + */ + unsigned long *channels_mask; + struct dma_device dma_slave; struct dma_device *dma_memcpy; struct edma_chan *slave_chans; @@ -716,6 +723,12 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (!test_bit(echan->ch_num, ecc->channels_mask)) { + dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", + echan->ch_num); + return -EINVAL; + } + /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), EDMA_CHANNEL_BIT(channel)); @@ -2250,7 +2263,7 @@ static int edma_probe(struct platform_device *pdev) struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; int i, off; - const s16 (*rsv_slots)[2]; + const s16 (*reserved)[2]; const s16 (*xbar_chans)[2]; int irq; char *irq_name; @@ -2331,15 +2344,32 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slot_inuse) return -ENOMEM; + ecc->channels_mask = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->channels_mask) + return -ENOMEM; + + /* Mark all channels available initially */ + bitmap_fill(ecc->channels_mask, ecc->num_channels); + ecc->default_queue = info->default_queue; if (info->rsv) { /* Set the reserved slots in inuse list */ - rsv_slots = info->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) - bitmap_set(ecc->slot_inuse, rsv_slots[i][0], - rsv_slots[i][1]); + reserved = info->rsv->rsv_slots; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_set(ecc->slot_inuse, reserved[i][0], + reserved[i][1]); + } + + /* Clear channels not usable for Linux */ + reserved = info->rsv->rsv_chans; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_clear(ecc->channels_mask, reserved[i][0], + reserved[i][1]); } } @@ -2399,6 +2429,7 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->legacy_mode) { int lowest_priority = 0; + unsigned int array_max; struct of_phandle_args tc_args; ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, @@ -2420,6 +2451,18 @@ static int edma_probe(struct platform_device *pdev) info->default_queue = i; } } + + /* See if we have optional dma-channel-mask array */ + array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); + ret = of_property_read_variable_u32_array(node, + "dma-channel-mask", + (u32 *)ecc->channels_mask, + 1, array_max); + if (ret > 0 && ret != array_max) + dev_warn(dev, "dma-channel-mask is not complete.\n"); + else if (ret == -EOVERFLOW || ret == -ENODATA) + dev_warn(dev, + "dma-channel-mask is out of range or empty\n"); } /* Event queue priority mapping */ @@ -2437,6 +2480,10 @@ static int edma_probe(struct platform_device *pdev) edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { + /* Do not touch reserved channels */ + if (!test_bit(i, ecc->channels_mask)) + continue; + /* Assign all channels to the default queue */ edma_assign_channel_eventq(&ecc->slave_chans[i], info->default_queue);