From patchwork Thu Feb 8 06:28:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 770981 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5937967E62; Thu, 8 Feb 2024 06:28:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707373740; cv=none; b=ALJhg82e9C4lSWQDFeHgDgHRWATQOV1giaZkc30IdP3FU5+ik8gmWR+44bA9fbCpRhj7KRDFAhI9YKEPNRWd4j7cDyUt+H5ugCQeBOwCc04XlzoloUQa9Gxgpzt8cw934WFTkkeX9+pAXSiYx4zGE7RDSdLBM9tBcXHoINf8UqQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707373740; c=relaxed/simple; bh=Xil7KBhIZOzMZcPF+/CBDhaBElAT0dkrT7nmq8pUTWI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j4fMJERy4Mm5y6NMHg1TJyRZPoCJAETcz2UtgrEnZQziD0PnyNbsdgM+zPwssS3gNsIUfBUegx8hsZc8nLnXKOB8SfYtaZuaEgXBlYT6OvbLpBho6UEuw0sjesHykUyb7vgI6Ck1kMVRrW61F4/bB5pYM+Fr/wfKiSp+Z89cK4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=d1m24PZc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="d1m24PZc" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4185VNId026580; Thu, 8 Feb 2024 06:28:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=2b57wkokE3uxhgK5j61N gNqEG8fmYeTiAROVX9XuB9Y=; b=d1m24PZco7KBV2yWPKT32bEBnVvb2nUSBe8M Dj7CNzgKkbhFkZXFJpuUI30qm4C50VirgLXgadL1rrippvrEdGQ38FDb7geVTMqs Kz9st3ARQu1C5YmQtsxre8NRPkcUguMotxSknmqMo/GFATUDeWzUL3FetnyFnGpw GIA/XsM30Jyl7dVzSZ/+OQ0SU4RgzNOjc/gSKS5jRwQc0HPCW8IeAHCBEA5aSR/C U3mhtCMwUYexnpbFbaiw0SZzOCQgp3oIsHC+YJiZ9psEOCvTLxQg7QAvsX+gjSM0 KoIXgVA1G2LSumYdMq9Jhr+jcYkgWvrASJgl+3YQMBD35bE4qg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w46r82g1q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Feb 2024 06:28:55 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4186Ssft029666 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Feb 2024 06:28:54 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 22:28:51 -0800 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Conor Dooley" , Krzysztof Kozlowski CC: , , , Taniya Das Subject: [PATCH 1/5] bindings: clock: qcom: Add "qcom, adsp-skip-pll" property Date: Thu, 8 Feb 2024 11:58:32 +0530 Message-ID: <20240208062836.19767-2-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240208062836.19767-1-quic_tdas@quicinc.com> References: <20240208062836.19767-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9wpJHi6ZVlLwQwMnjqNB-TsH5qRfvJ4t X-Proofpoint-ORIG-GUID: 9wpJHi6ZVlLwQwMnjqNB-TsH5qRfvJ4t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_01,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 spamscore=0 mlxscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402080032 When remoteproc is used to boot the LPASS the ADSP PLL should not be configured from the high level OS. Thus add support for property to avoid configuring the LPASS PLL. Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml index deee5423d66e..358eb4a1cffd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -49,6 +49,11 @@ properties: peripheral loader. type: boolean + qcom,adsp-skip-pll: + description: + Indicates if the LPASS PLL configuration is to be skipped. + type: boolean + required: - compatible - reg From patchwork Thu Feb 8 06:28:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 770980 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 221C767E6A; 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Thu, 08 Feb 2024 06:29:03 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4186T265029652 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Feb 2024 06:29:02 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 22:28:58 -0800 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Conor Dooley" , Krzysztof Kozlowski CC: , , , Taniya Das Subject: [PATCH 3/5] clk: qcom: sc7280: Update the transition delay for GDSC Date: Thu, 8 Feb 2024 11:58:34 +0530 Message-ID: <20240208062836.19767-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240208062836.19767-1-quic_tdas@quicinc.com> References: <20240208062836.19767-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: NG7MmiA_e_NuSLjMFAaVfpqHmdb4ErBS X-Proofpoint-GUID: NG7MmiA_e_NuSLjMFAaVfpqHmdb4ErBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_01,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 mlxscore=0 suspectscore=0 phishscore=0 malwarescore=0 bulkscore=0 mlxlogscore=711 priorityscore=1501 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402080032 The GDSC default values are being updated and they can cause issues in the GDSC FSM state. While at it also update the force mem core for UFS ICE clock. Fixes: fae7617bb142 ("clk: qcom: Add video clock controller driver for SC7280") Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Fixes: 3e0f01d6c7e7 ("clk: qcom: Add graphics clock controller driver for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/camcc-sc7280.c | 19 +++++++++++++++++++ drivers/clk/qcom/gcc-sc7280.c | 13 +++++++++++++ drivers/clk/qcom/gpucc-sc7280.c | 7 +++++++ drivers/clk/qcom/videocc-sc7280.c | 7 +++++++ 4 files changed, 46 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index 49f046ea857c..4849b0e8c846 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2247,6 +2248,9 @@ static struct clk_branch cam_cc_sleep_clk = { static struct gdsc cam_cc_titan_top_gdsc = { .gdscr = 0xc194, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_titan_top_gdsc", }, @@ -2256,6 +2260,9 @@ static struct gdsc cam_cc_titan_top_gdsc = { static struct gdsc cam_cc_bps_gdsc = { .gdscr = 0x7004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_bps_gdsc", }, @@ -2265,6 +2272,9 @@ static struct gdsc cam_cc_bps_gdsc = { static struct gdsc cam_cc_ife_0_gdsc = { .gdscr = 0xa004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_0_gdsc", }, @@ -2274,6 +2284,9 @@ static struct gdsc cam_cc_ife_0_gdsc = { static struct gdsc cam_cc_ife_1_gdsc = { .gdscr = 0xb004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_1_gdsc", }, @@ -2283,6 +2296,9 @@ static struct gdsc cam_cc_ife_1_gdsc = { static struct gdsc cam_cc_ife_2_gdsc = { .gdscr = 0xb070, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_2_gdsc", }, @@ -2292,6 +2308,9 @@ static struct gdsc cam_cc_ife_2_gdsc = { static struct gdsc cam_cc_ipe_0_gdsc = { .gdscr = 0x8004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ipe_0_gdsc", }, diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 2b661df5de26..5f3bfb6f4fbb 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3094,6 +3095,9 @@ static struct clk_branch gcc_wpss_rscp_clk = { static struct gdsc gcc_pcie_0_gdsc = { .gdscr = 0x6b004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_pcie_0_gdsc", }, @@ -3112,6 +3116,9 @@ static struct gdsc gcc_pcie_1_gdsc = { static struct gdsc gcc_ufs_phy_gdsc = { .gdscr = 0x77004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_ufs_phy_gdsc", }, @@ -3121,6 +3128,9 @@ static struct gdsc gcc_ufs_phy_gdsc = { static struct gdsc gcc_usb30_prim_gdsc = { .gdscr = 0xf004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_usb30_prim_gdsc", }, @@ -3467,6 +3477,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 1490cd45a654..0eea4cf7954d 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -379,6 +380,9 @@ static struct clk_branch gpu_cc_sleep_clk = { static struct gdsc cx_gdsc = { .gdscr = 0x106c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .gds_hw_ctrl = 0x1540, .pd = { .name = "cx_gdsc", @@ -389,6 +393,9 @@ static struct gdsc cx_gdsc = { static struct gdsc gx_gdsc = { .gdscr = 0x100c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .clamp_io_ctrl = 0x1508, .pd = { .name = "gx_gdsc", diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c index 615695d82319..b07895c459e8 100644 --- a/drivers/clk/qcom/videocc-sc7280.c +++ b/drivers/clk/qcom/videocc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -232,6 +233,9 @@ static struct clk_branch video_cc_venus_ahb_clk = { static struct gdsc mvs0_gdsc = { .gdscr = 0x3004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvs0_gdsc", }, @@ -241,6 +245,9 @@ static struct gdsc mvs0_gdsc = { static struct gdsc mvsc_gdsc = { .gdscr = 0x2004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvsc_gdsc", }, From patchwork Thu Feb 8 06:28:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 770979 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0706567E61; Thu, 8 Feb 2024 06:29:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 08 Feb 2024 06:29:10 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4186T9Mk012386 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Feb 2024 06:29:09 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 7 Feb 2024 22:29:06 -0800 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Conor Dooley" , Krzysztof Kozlowski CC: , , , Taniya Das Subject: [PATCH 5/5] arm64: dts: qcom: Update protected clocks list for qcm6490 variants Date: Thu, 8 Feb 2024 11:58:36 +0530 Message-ID: <20240208062836.19767-6-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240208062836.19767-1-quic_tdas@quicinc.com> References: <20240208062836.19767-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4wvxeMOOnOshP2AgLngQpAFrDsu7Rbvi X-Proofpoint-ORIG-GUID: 4wvxeMOOnOshP2AgLngQpAFrDsu7Rbvi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_01,2024-02-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=838 spamscore=0 mlxscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402080032 Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards thus require them to be marked protected. Also disable the LPASS nodes which are not to be used. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- 2 files changed, 102 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 03e97e27d16d..425e4b87490b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -415,6 +415,58 @@ }; }; +&gcc { + protected-clocks = ,, + , , + , , + , , + , , + , , + ,, + , , + , + , , + , , + , , + , , + , , + , , + , , + , , + , ; +}; + +&lpasscc { + status = "disabled"; +}; + +&lpass_audiocc { + qcom,adsp-skip-pll; + protected-clocks = , + , , + , , + , , + , , + , , + , + , + , , + ; + /delete-property/ power-domains; +}; + +&lpass_aon { + status = "disabled"; +}; + +&lpass_core { + status = "disabled"; +}; + +&lpass_hm { + status = "disabled"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85f6..1398b84634c3 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -413,6 +413,54 @@ }; }; +&gcc { + protected-clocks = , , + ,, + , , + , + , , + , , + , , + , , + , , + , , + , , + , , + , ; +}; + +&lpasscc { + status = "disabled"; +}; + +&lpass_audiocc { + qcom,adsp-skip-pll; + protected-clocks = , + , , + , , + , , + , , + , , + , + , + , , + ; + /delete-property/ power-domains; +}; + +&lpass_aon { + status = "disabled"; +}; + +&lpass_core { + status = "disabled"; +}; + +&lpass_hm { + status = "disabled"; +}; + + &qupv3_id_0 { status = "okay"; };