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Fri, 16 Feb 2024 03:03:55 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r2-20020a05600c35c200b004123b049f86sm1993174wmq.37.2024.02.16.03.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 03:03:55 -0800 (PST) From: Neil Armstrong Date: Fri, 16 Feb 2024 12:03:49 +0100 Subject: [PATCH v3 2/7] dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-topic-sm8650-gpu-v3-2-eb1f4b86d8d3@linaro.org> References: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> In-Reply-To: <20240216-topic-sm8650-gpu-v3-0-eb1f4b86d8d3@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The if condition for the SM8[45]50 GPU SMMU is too large, add the other compatible strings to the condition to only allow the clocks for the GPU SMMU nodes. Fixes: 4fff78dc2490 ("dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU") Suggested-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index a4042ae24770..38c48131e6e7 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -484,7 +484,12 @@ allOf: - if: properties: compatible: - const: qcom,sm8450-smmu-500 + items: + - const: qcom,sm8450-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: properties: clock-names: @@ -508,7 +513,11 @@ allOf: - if: properties: compatible: - const: qcom,sm8550-smmu-500 + items: + - const: qcom,sm8550-smmu-500 + - const: qcom,adreno-smmu + - const: qcom,smmu-500 + - const: arm,mmu-500 then: properties: clock-names: From patchwork Fri Feb 16 11:03:51 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Sync missing regs for A750 clock gating control related registers from Mesa a6xx.xml.h generated file. Those registers were added in the !27576 merge request [1]. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576 Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..58877464692a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1725,6 +1725,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +1941,19 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff From patchwork Fri Feb 16 11:03:53 2024 Content-Type: text/plain; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62e6ae93a9a8..27dcef27b6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2589,6 +2589,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +2724,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";