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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:04:53 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 1/7] ARM: dts: samsung: exynos3250: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:43 +0000 Message-ID: <20240216140449.2564625-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos3250.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 a 64 byte FIFO depth. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/samsung/exynos3250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos3250.dtsi b/arch/arm/boot/dts/samsung/exynos3250.dtsi index 3f1015edab43..b6c3826a9424 100644 --- a/arch/arm/boot/dts/samsung/exynos3250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos3250.dtsi @@ -826,6 +826,7 @@ spi_0: spi@13920000 { samsung,spi-src-clk = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; status = "disabled"; }; @@ -842,6 +843,7 @@ spi_1: spi@13930000 { samsung,spi-src-clk = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; status = "disabled"; }; From patchwork Fri Feb 16 14:04:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 773898 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1198A12C526 for ; Fri, 16 Feb 2024 14:04:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092299; cv=none; b=JCUkci5g+xt3EE8AW+9ic85rAWM8gEvuPHmjCy2OSH0afdsQGO2kTgtNCNBedeRE5MRiuoPs7naRpw0bfTCOKlwoQ+899pBHaojzW9uv6RP8bQGX9+ZaS/N+wAAVvjR1u+Ve/zpOtuB6fKZJYgqw00RvgsEzZ4w9sU959Q27avA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092299; c=relaxed/simple; bh=nQr8Kfcz6Jo4+i8KVH+YbRUWCwWoQLLr3kZy2y0plho=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fobxF9GV2wPtFW5+tE4EWBdvePw5+GvSdInWiYLAzXrV8uqZBbTXhuvUbMfdCsOMIFt3BQy7FNACVrcZkfOOkomsx6LLGY83Damq5I5W03wvoW4vN0HyseOySzJ1efArQ0aflwuSlzAoRRi2IgCRCNxFGTf+fffJUTMvelNXJR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nAZPG2or; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nAZPG2or" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-5120ecfd75cso2842392e87.0 for ; Fri, 16 Feb 2024 06:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708092296; x=1708697096; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IoKD5bRktYBx1n+y/s9dpLnkNcyEHfZAqtDf6Pd57R0=; b=nAZPG2or9gQRV2dZuVvrUVLr/aZEnbfcNljngqh1KUjspTOK3Bl6CWKDBYZo2LKIdI PDkRGb6S/iMRf9Tyq66pPompFh17jRtuX7kETVuDZ35BKOON6N9c02wKLnDzyKxSYpVX Gal424JH2t0g2XMImrG4kdMlgwEXAkis7yeddpwtMIIBL8DR7/iH3QRW8/rCHWwhFMos WxXS+lwnktsEjQQvI51OUip6DzCRsJzNhHqSmlTqUpnf7nWxCD+nZIa5jliexYnTxBBi AnCjDCd0ZHlFDswlJPNbeSvYbkPBIyCA0ZvRL0mwwq4QD4wVCujsyfegcIMJhnXOXKBW ZbMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708092296; x=1708697096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IoKD5bRktYBx1n+y/s9dpLnkNcyEHfZAqtDf6Pd57R0=; b=mg9F0Zd3vQI85AFj5sIJajevy9HVBWQQ/k3tK/Jk5v53tZdhOAyu6UooryYPihKZid mmK4/81LbKEZsXjrvqbWabuxFdNeZKcW75nclDqpvaoEma7jbIrFHZZNqo6/1Sz95bK2 cuenqvTaLtN8RvOC0DsFGPTn1Y3gSQNEV6niXzc3QkrV8HF2S2wez439O1Qxtze4qH9A U3jpI8K9KGNlDPNiIb6ORQ38HTfqVIvnr0G0JnhH7grOWDDE1ukxalNSxwCnveutYGdf ThOdJF3OjZk99A93v/ITbjNnMSWzXYKeW0WHb1ps8vFD+lCiNOKM7eB+Xv2K/jrHzOKD DsPQ== X-Forwarded-Encrypted: i=1; AJvYcCWOQpEfO7/UuPEiAX7im2O/EfsySYMmS/mN+rdiWDdv1vKqYflv2+tHxEtBXKWnU6MAGqqwHF5eOGc2NArNzmpk5ozFfuwmVGKotTplcxFbz8Q= X-Gm-Message-State: AOJu0YxYaAJtv2/HRbOSQ0s7rSVgbooxKlqcUTt2n218/3oCS7C0ewS4 aQE5PCf6k6B9m2u8BGhEIPP/WorWxM4pKlVYHB5p2pAk8qTVRrEQcMDYB4sv9dsNDXpdirFB6oF Q/HM= X-Google-Smtp-Source: AGHT+IE9vX1AKj2JOn/B8o/haeJFU2gEt8ObeXnpMNVVvEAqUlLvLNixeuJWM0nROcdwy3mX/SWqsg== X-Received: by 2002:a05:6512:2253:b0:512:999e:671b with SMTP id i19-20020a056512225300b00512999e671bmr808593lfu.54.1708092295996; Fri, 16 Feb 2024 06:04:55 -0800 (PST) Received: from ta2.c.googlers.com.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:04:55 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 2/7] ARM: dts: samsung: exynos4: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:44 +0000 Message-ID: <20240216140449.2564625-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos4.dtsi defines the following SPI aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/samsung/exynos4.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi index 7f981b5c0d64..ed47d0ce04e1 100644 --- a/arch/arm/boot/dts/samsung/exynos4.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4.dtsi @@ -621,6 +621,7 @@ spi_0: spi@13920000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; status = "disabled"; }; @@ -636,6 +637,7 @@ spi_1: spi@13930000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; status = "disabled"; }; @@ -651,6 +653,7 @@ spi_2: spi@13940000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; + fifo-depth = <64>; status = "disabled"; }; From patchwork Fri Feb 16 14:04:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 773607 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A55312CD98 for ; Fri, 16 Feb 2024 14:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092301; cv=none; b=XPD38s2C0YHdZVDkJBbCliCtsrRzODex5RMfFj1T7cUQjOrTEd51L292EfQS0JRYoa86LvgAdEH4YyMVjXvcYrr+0dw+NV2MOQWFm+P+qFFti+vVHMEIn3VuckUgwnKT3Rta0x1aXZE0q4N5KgOZKxaoaO2DLsAexKEVT56Z12o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092301; c=relaxed/simple; bh=+4hpMqvo2MaSV4b7Jg+jh1kB57aNCVnu3p9sey7n17U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nC9JDTpmWEF7kZw5+n7Flgj4OGOy2Ue6le56UBGBJyJ9o0cU1IGwK9r1VRi3+Cvx7ZXmV37l5j0Oqk0XLoYJ/jrs9KFWxCwJQyfOHjXomE3fPV1uc2gTRST8zGmpbtw09Ca9CfUkY/qlwzudycgRJhzbPM4Vu9s17Dt+tXmMBPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hFKwSnqL; arc=none smtp.client-ip=209.85.208.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hFKwSnqL" Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-2d0a4e8444dso7596111fa.2 for ; Fri, 16 Feb 2024 06:04:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708092297; x=1708697097; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0Zx9+5BqwaAzaN+5Db7Ws66Fn8aez1AAIMWd7GQ05DA=; b=hFKwSnqLmXqQTdpYBPsQdOEWUrzONHDWt4keqbkASzd0muwDJ8vyTolaAyrztEnnSG f3KGRc3xkUofEtfFw1CUgoxrhQb3Aw1iRcagvvIGiL5AZ6RGcxmq4hUGVeEkHthZjMmK VSIdg78rXb5549cBo4AYqnGfbSSRzNTjwCdCdCKl9041E9veb3u/r7Pa/SnpxU5hJqdD ehz6nqPxvmAjkPuE6jmRorVscVb7sr/LZnBlu/ENRJoOC6yJC0U/E+hNBigAP1xgtYt9 J3rNJtKN8JqYK7MT48B91h98TIwee/HxIk8fS93Nw6ryVy34SkX09eI7hYlbuykPYqE9 aDRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708092297; x=1708697097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0Zx9+5BqwaAzaN+5Db7Ws66Fn8aez1AAIMWd7GQ05DA=; b=sbBdbuAxW8yFMtYMyJ2tz1XgEU0IGEuQqeErq0t5UZqlNyeZ8oxKTl/mNKxgjEbDYR tSm7lAEjUn7NKrN/Jt5XO2AKh2sZQgZUxAoYZ6lun07J+RNju6Ecfzt/Ud894NOAL9j5 CT36SKAUEWr+hgspqvw7p2P8cTspsA8XApw95OsWt8lL2/dTogtxmcm9OYwFxLwSn/4q 4HjK/f2EGGz0sQuhlPOzYArAhUgF5UT+3HW59kvUTdjc3IJP7EB4lwuRII9JXWLCX+HF h2vzpStuhZfMJVP0RtlhF98ilKsrk0VYB+uqQMglm0xfz8jvQ+jye6Pte5WC+0UR0k4b qF0g== X-Forwarded-Encrypted: i=1; AJvYcCU3TgLJlcBTHxRP99y84AKS0bg8F1TVEPmK4vWNyJ0SNhIJtmQazkwPjNCGplBsKn5kUPR7ZkkPMZMFydObFm+O1arNvUzjDIlaVFyIEbdjrNg= X-Gm-Message-State: AOJu0Yxfac9JO2v5UtzhYvA8fRa9XBVtge2xcVpk0slKCCuXCfx4Jt1M EboEhRmk4AicpIcUTSrFDJftBFWQwmyKQLKkfHbPCNMsBEDOMf94NgSMALi/zMY= X-Google-Smtp-Source: AGHT+IE0EGbYQbv4l1lKRbqg12eixWC4l3SC8S7Jp79dW2xoIxVUBLK5AuANr1RWkebpsL9mNE5ikA== X-Received: by 2002:a2e:a684:0:b0:2d1:107b:3ba1 with SMTP id q4-20020a2ea684000000b002d1107b3ba1mr3441338lje.10.1708092297388; Fri, 16 Feb 2024 06:04:57 -0800 (PST) Received: from ta2.c.googlers.com.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:04:56 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 3/7] ARM: dts: samsung: exynos5250: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:45 +0000 Message-ID: <20240216140449.2564625-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos5250.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/samsung/exynos5250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi index 99c84bebf25a..b9e7c4938818 100644 --- a/arch/arm/boot/dts/samsung/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -511,6 +511,7 @@ spi_0: spi@12d20000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; }; spi_1: spi@12d30000 { @@ -526,6 +527,7 @@ spi_1: spi@12d30000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; }; spi_2: spi@12d40000 { @@ -541,6 +543,7 @@ spi_2: spi@12d40000 { clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; + fifo-depth = <64>; }; mmc_0: mmc@12200000 { From patchwork Fri Feb 16 14:04:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 773897 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C2F012CDBD for ; Fri, 16 Feb 2024 14:05:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092302; cv=none; b=B//8Dy/Y+8eMQnpvyZSDxM53iRfFR7RT9fucfsB56RP/PGJweArEmiHMhEhre1pxdHXcP3gl5zphaNCTkcuVsR9YhaSPfywZe3OoD0R7XJXnVx5C61Y6k9Mwqf652KDlqXYV7dtHzGNB3ewv4rfDd6i4zb3PHLW8wbyIUUxexxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092302; c=relaxed/simple; bh=GrK2q7DlbtQY1WTzK5R2HznL/kcWzqoRab2apDhvAwg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sdvXJwPf3CbexGmqh1PgGAqH452IF1rjdoXCooNUihu+WmgqUQ55Ye+4guJ8kvc73Y1gVTva7dQ3M1dP0ABjAhM5x1Y4+FQ7z6rtXU60LZv514Gb1CHZ675pvP9W7zjAyXEg3I1d5fW9CtqOultFcQ+w1PJAkNmA5tsR+x31wMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=F5kRviix; arc=none smtp.client-ip=209.85.208.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="F5kRviix" Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2d204e102a9so26007161fa.0 for ; Fri, 16 Feb 2024 06:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708092298; x=1708697098; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AJ7Tgql1DL0Frghi7Oag5F57dXBGRkIPbGxxgHm6Hxc=; b=F5kRviixUT2g4dXXaYzE5Qi4U7r2Fs9lIXFAJhsNm4wJtRp4l8gNFAt5guF2WeizA7 DIiL33iiWT0KoO3XAhvBPhgDaDS07TTHZHoWo6mdpo7Ikw6AKyf1DfNEwOBcyUKzKfd3 5SwIoUMli8IPxsh4YENSCJ5bswBmMNKv4xyGPz/FDCqU90wPDbrEYp4sLtRWxW/eE6RK ZzSiIzbQiL5GE9xo7+Avlf88zpNcNWXo9206uScGpAg/uAi116AgpXHII9EyLMHX6gxo VN0dAyDM/iINvkQoypyfXgHOGlN4FInoUujg69cklkU51sV4QExPm4Cm2npOD8PJKEWP dR9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708092298; x=1708697098; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJ7Tgql1DL0Frghi7Oag5F57dXBGRkIPbGxxgHm6Hxc=; b=Ky+FC+mrXiLSwsW8UXsOI6JrhyG52jHIN3srz5u4H/1yQxJBe6nAikORP/ZUWiAzjj +yeRfPfYfNJ4ObBbm73fw+93bQJEUjWLYX+34vY6Ndw4jN8xyaTHbdkarBXjacC+fGt8 2ViMnDIVvaVnKqGN3o8WWee0GbC2TjE+dtRRqrIlMcrlAsdwOUz2LpfQkK6CBQ3NaIeC N3ZjygbhHH6eUJQTNv7ahYwG1+mzK8bKJvBbVynVrlrT3oxb+5N5yIF447p4B6S63BBP YqQIc4uPEf8Nu0+iA7tI3KrjYE2RFTkEDrGLnh7OmHe7449SVW7xIzeA8N0jtrAN/T2S 5HLA== X-Forwarded-Encrypted: i=1; AJvYcCVUDDgm10zcEas1lTy4QRHqUtLKgIwlEfzsrMM2BiK8C0cK0ujwhKE4zqVsCPC55+bM546oYIAcutoKdvyJyFYUvXnO10rflvePeaK/vR4VSqg= X-Gm-Message-State: AOJu0Yy7/Ix1TsP1YRTYD3q1C+vkz5ByG+frRsHQeskY8OHQ5Zi7idpD j6KxnWYP8VM+bdbSSFRZ31SQnjvjq49AEaTLb9gGUGs+1XH7ZSb0ae+e+xKrHss= X-Google-Smtp-Source: AGHT+IGa96Bfo9g5nXjjGLG0eTx75/Ggxg2VA+hGJqraejkAQYX30I75/4p3/e+XG2Q57P8TXVx7Bg== X-Received: by 2002:a2e:a686:0:b0:2cd:706a:8ec8 with SMTP id q6-20020a2ea686000000b002cd706a8ec8mr3392254lje.10.1708092298240; Fri, 16 Feb 2024 06:04:58 -0800 (PST) Received: from ta2.c.googlers.com.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:04:57 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 4/7] ARM: dts: samsung: exynos5420: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:46 +0000 Message-ID: <20240216140449.2564625-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos5420.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/samsung/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5420.dtsi b/arch/arm/boot/dts/samsung/exynos5420.dtsi index 25ed90374679..196c6d04675a 100644 --- a/arch/arm/boot/dts/samsung/exynos5420.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5420.dtsi @@ -658,6 +658,7 @@ spi_0: spi@12d20000 { pinctrl-0 = <&spi0_bus>; clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <256>; status = "disabled"; }; @@ -674,6 +675,7 @@ spi_1: spi@12d30000 { pinctrl-0 = <&spi1_bus>; clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <64>; status = "disabled"; }; @@ -690,6 +692,7 @@ spi_2: spi@12d40000 { pinctrl-0 = <&spi2_bus>; clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <64>; status = "disabled"; }; From patchwork Fri Feb 16 14:04:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 773606 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75A7112D762 for ; Fri, 16 Feb 2024 14:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092303; cv=none; b=bC5hzUduokw2iJoqr2b+7I79gG82Pjz5V0Qu6UQsytxahfTq1TmJzLu6iHA8jUcHlAr/mNpM1xKoNxS7E81148df/N4HpS/r5CPVx64fiEKhpBkEG5axAJHLziXTbMx1zFgB9AYRdiG33xy4O7Xt2BBVST+tDWvhTR9rAAWQme8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708092303; c=relaxed/simple; bh=pbz+IkgS7dGub+xGhkr3c/sezMbM4xsciLvnrgZeQc4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SCrAU1C+ZNZiGTHZ+PVmpadZXyGnImb7pxDyT9ZVs/ZxcXeV7M9NiWN8aypl7yZA9/saQYkxGsZRQJe/2D+3ASZMHuNxwDsWXZ+tvvX/yz7UoDkzHHPXwv0Y6z/K7H3q8J6MXUpAxBxaefF/4/ksGW0jRvgZtzs2QgNwIO5fGB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=l1FJGFiP; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="l1FJGFiP" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-410e820a4feso17863685e9.1 for ; Fri, 16 Feb 2024 06:05:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708092300; x=1708697100; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QpbLWzMyYPwodhbzPXYFFQOvyF35F7rYtI5CvxnVpBk=; b=l1FJGFiPX17vy7Z59VSB8TMjXtvlZB3N1hOxhwbu1mtzx4ez9d866aDsF3wymWaP/E AdLS1cOrgD3GfDY3dLxcywAn/5QEuqiziYhO7/SY34DB/Q6KPngDcP4uvr8n+TpaWaZh 3FYZWsdQd0VR8Tp8M/qVP1/lE0PgzdI2EMNYA8UgR0JRmaGpb39lgEFMYXls7QK0ITvM 5lXXobfozRcxUxn6nSarCn6HwqAwmCfzailsKm5nj8vTo6tFeyjJZ3XYxTtIb5SriL5z 6wl/n6toE9Zoaw+aqWEl1ksU8yZbXVdenQ7It7YQSA0soszxhQSvxpPGNAkMOd7IAO5M POLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708092300; x=1708697100; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QpbLWzMyYPwodhbzPXYFFQOvyF35F7rYtI5CvxnVpBk=; b=ScMQzqRgaNmGmTD0bpQ8kXImEmKs7nhBq355w+YxU5gghuzxG7SJyCqcuF95SsZXuC JMAFzscmjpdsb275mWzutHESSXsZniYQ4PL7HC0h/IcqwKsL/wIxIlSmPGN2vYcvZmAM 4zfVWsdCpIWxDsTEEhyd2Xo0n3hzSxRRzSstXpopE/rDCpSoRzWboNzIqihVtBTqkyOF 9h4HU+JnoRc8QpBVw/qi5O/awInpINaE0zeHsKRr4i9etghn5OGDl+wiruEE9SUu+vKX J+Ohc5KnsisD9om8iaF8Dfb1mrI1rQwkMOkfmz2xsgsorXZXghO8k8g63N+kKDc9Sw7k msPA== X-Forwarded-Encrypted: i=1; AJvYcCWJ7lRc6HjD3dhjrvx1Smq7Jc1BW7iB35MGZood7gfjZoSS3yv1JrRhcwhHx9Kv3ybjaSwdbUDHQ3iUxomJH1TMvJtN4NIF8oLmWY220MzMRUk= X-Gm-Message-State: AOJu0YwHGDU1Zfq4vWeERw0XWkFFXJiXbsu3H9nV6wwTaQrTlaU1VN5B 3fbqFJDsTj5QHbpoBMCsuGphMdKTsluFQE76sACT6cuNsAw3ggxwGZJUOaCWito= X-Google-Smtp-Source: AGHT+IHWdUB9E6Xmity8dCJxxH0CAvh8LXlNHW0BGR1UNv3oA+Bl9EEpasEs2AkAdEbHy98zpO3UGg== X-Received: by 2002:a05:600c:1d81:b0:412:107d:cd69 with SMTP id p1-20020a05600c1d8100b00412107dcd69mr4569337wms.1.1708092299870; Fri, 16 Feb 2024 06:04:59 -0800 (PST) Received: from ta2.c.googlers.com.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:04:58 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 5/7] ARM: dts: samsung: exynos5433: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:47 +0000 Message-ID: <20240216140449.2564625-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depthj Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. The FIFO depth were determined based on the SPI aliases that are defined in exynos5433-tm2-common.dtsi: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos5433-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, Thus spi{0, 4} were considered having 256 byte FIFO depths, and spi{1, 2, 3} having 64 byte FIFO depths. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7fbbec04bff0..0b9053b9b2b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1468,6 +1468,7 @@ spi_0: spi@14d20000 { pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; num-cs = <1>; + fifo-depth = <256>; status = "disabled"; }; @@ -1487,6 +1488,7 @@ spi_1: spi@14d30000 { pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1506,6 +1508,7 @@ spi_2: spi@14d40000 { pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1525,6 +1528,7 @@ spi_3: spi@14d50000 { pinctrl-names = "default"; pinctrl-0 = <&spi3_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1544,6 +1548,7 @@ spi_4: spi@14d00000 { pinctrl-names = "default"; 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:05:00 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 6/7] ARM: dts: samsung: exynosautov9: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:48 +0000 Message-ID: <20240216140449.2564625-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. There are no SPI aliases defined, thus the FIFO depth was determined by matching the FIFO depth of the I2C node of the same USI parent. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index c871a2f49fda..0248329da49a 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -435,6 +435,7 @@ spi_0: spi@10300000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -526,6 +527,7 @@ spi_1: spi@10320000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -617,6 +619,7 @@ spi_2: spi@10340000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -708,6 +711,7 @@ spi_3: spi@10360000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -799,6 +803,7 @@ spi_4: spi@10380000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -890,6 +895,7 @@ spi_5: spi@103a0000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -981,6 +987,7 @@ spi_6: spi@10900000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -1072,6 +1079,7 @@ spi_7: spi@10920000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1163,6 +1171,7 @@ spi_8: spi@10940000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1254,6 +1263,7 @@ spi_9: spi@10960000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1345,6 +1355,7 @@ spi_10: spi@10980000 { num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1434,6 +1445,7 @@ spi_11: spi@109a0000 { num-cs = <1>; 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id az5-20020a05600c600500b0040e4733aecbsm2516628wmb.15.2024.02.16.06.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 06:05:00 -0800 (PST) From: Tudor Ambarus To: krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, andre.draszik@linaro.org, peter.griffin@linaro.org, Tudor Ambarus Subject: [PATCH v2 7/7] ARM: dts: samsung: s5pv210: specify the SPI FIFO depth Date: Fri, 16 Feb 2024 14:04:49 +0000 Message-ID: <20240216140449.2564625-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog In-Reply-To: <20240216140449.2564625-1-tudor.ambarus@linaro.org> References: <20240216140449.2564625-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. The SPI nodes defined in s5pv210.dtsi are not enabled in any board file. No SPI aliases are defined, thus choose the FIFO depth using common sense: index 0 of the array for spi0, and index 1 for spi1. No functional change expected. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/samsung/s5pv210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi index ed560c9a3aa1..3eba870db73f 100644 --- a/arch/arm/boot/dts/samsung/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -161,6 +161,7 @@ spi0: spi@e1300000 { pinctrl-0 = <&spi0_bus>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -177,6 +178,7 @@ spi1: spi@e1400000 { pinctrl-0 = <&spi1_bus>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; };