From patchwork Tue Sep 24 08:08:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 174255 Delivered-To: patch@linaro.org Received: by 2002:ac9:19ad:0:0:0:0:0 with SMTP id d45csp3547285oce; Tue, 24 Sep 2019 01:08:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqx60i0+q9vUr4ZS+3VAjXmCyIUvbamaNtnbEfToHpRxj3wAQIANHaOcgit45R8ODIhw3L2d X-Received: by 2002:a50:9fce:: with SMTP id c72mr1341359edf.166.1569312521978; Tue, 24 Sep 2019 01:08:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569312521; cv=none; d=google.com; s=arc-20160816; b=UioRgcCxylBoeJYVopy7OXWcAmiD2lEoAeDaJH1yOsTN+OU5hZYJDMM3rir+SvKHk9 uiV406Ao2dFVPcPgSF1b7KCDFsaVPQFYCW5+SfDtfP6HhUHMR+GuY+UzvFFrud0S+ba/ R8uCslr0t4/NbKQhyz6Ox/kQjc6LpAAand8gVKb0UvlMiSl5frrXpFRb5A7K5araJNnl o5V0RwIPImEfKZO37fQtQdY9ym9iffaBZ5avVIjUABska5a8liJ41Xi5P2oxyg6XzFOt owzJqJ7gnF2TlHbYoWY+oDGO/zmjOg1j6D9X3qTKdpgqmtgLGNohZiuqVCDeTFf4A1kw ooHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Hi1ifQQR9gpdPmRZ1GOZNnhiHESsDUToV+uCj5M5hAM=; b=VM+d6+SJr3wwvcFtbREivJUn3edVD+gk6j0S7+J3gWuZw2p3ckv7F/AHhcz/Ha9DlM rFq5GeRY63bLSUilqvqAUZJ3PDwgfw/sLlD3yx+IduGx/NUVNiyduR+bYfMnfF5Afw3G LfbxD+4it1FWD/mFYUXEcNryMOIX13lF9R9XcfKyFMWv/T9GRdvO2VGt4BuIfsxUvuJC zPu48aQXpdUBesTBSA+INIUziVjGqylXN7heiDgaJI3auPFK2s1RSVhMCTs68MmsB0sW AsXwG4zZfdomWDFlxGhOeO7Im/9BBCI8RH9rhYqTAXAfbjtFJ6nQIhJo8EgJgKPw7Cbp UqYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=NxoJWtHN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e23si535174edq.344.2019.09.24.01.08.41; Tue, 24 Sep 2019 01:08:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=NxoJWtHN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2504068AbfIXIIl (ORCPT + 26 others); Tue, 24 Sep 2019 04:08:41 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:43472 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2436587AbfIXIIj (ORCPT ); Tue, 24 Sep 2019 04:08:39 -0400 Received: by mail-wr1-f68.google.com with SMTP id q17so807620wrx.10; Tue, 24 Sep 2019 01:08:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hi1ifQQR9gpdPmRZ1GOZNnhiHESsDUToV+uCj5M5hAM=; b=NxoJWtHNY256XL25Cim07uB4YuUcEkGp4Xpw7ePOsYhsTGdon2Dr2B5zkiwa92pnlq Tu4yyXG51bdy0iytfp8LPPWkwsz5JJKsj/jEXFlNHO41LxVQoWvf3ytsFG49CkYIjhv3 iEuX1kVXJB7JTZ95HaD+EWnsadj1J3qy0MGnMlfZUSiffmQe5BHG5OFQ9urMZeCC9Ypd pT3PVy/IyhIJ0vqRySbXDYGugnbQE6TEkpccoBGA1tZJfImNe6a+rnKI+qN7+tUT6aqK zm/ZvTwsU8w0qppOnQV9daojHP5xcoj0jl3Ih2+nOJxucLUcKRcR+7U/fIUB1zbaswm1 glgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hi1ifQQR9gpdPmRZ1GOZNnhiHESsDUToV+uCj5M5hAM=; b=D+bgqPnep7h+B9KBkg/PyNAeWaU6naTZV4hgU2FQqEsZOTlv5Cs9EUbHcgkRHTIexh GV+eANFKoOfjCuU/Wo0b4qvmfIbGffr1gMe1ZCG0HZE8z4SMD2IbaxPcnOJ+CmPHMkSX JumMo4Y+DwrogFQPOWffVQHjpDFV10M/OApmZLFnp0ZI3jir0xYrEKkoNANgCUe4/5xu TV94M5FWGICJAKmdbcf+0d/lQN0qb2ewgOfEL49NnRastLF2h/8g8W4YSqbQ2vzfI/5f fwr0mepUCmouhhnV04Zn/4fTwE3PrcViMI4gTvfwBj+WYR65FTko50cSTdarjgQpCNoP Burw== X-Gm-Message-State: APjAAAUBsg5Ych5QjhBrfZPKDSyEQFe87inkNsaNeSFNclPyxdkPxA7A gHwHr+wWpvwIohT4456JqKo= X-Received: by 2002:adf:efcb:: with SMTP id i11mr1255379wrp.69.1569312516938; Tue, 24 Sep 2019 01:08:36 -0700 (PDT) Received: from Red.local ([2a01:cb1d:147:7200:2e56:dcff:fed2:c6d6]) by smtp.googlemail.com with ESMTPSA id u22sm1825256wru.72.2019.09.24.01.08.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Sep 2019 01:08:36 -0700 (PDT) From: Corentin Labbe To: davem@davemloft.net, herbert@gondor.apana.org.au, mripard@kernel.org, wens@csie.org Cc: linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v3 1/2] crypto: sun4i-ss: simplify enable/disable of the device Date: Tue, 24 Sep 2019 10:08:31 +0200 Message-Id: <20190924080832.18694-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190924080832.18694-1-clabbe.montjoie@gmail.com> References: <20190924080832.18694-1-clabbe.montjoie@gmail.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch regroups resource enabling/disabling in dedicated function. This simplify error handling and will permit to support power management. Signed-off-by: Corentin Labbe Acked-by: Maxime Ripard --- drivers/crypto/sunxi-ss/sun4i-ss-core.c | 77 +++++++++++++++---------- 1 file changed, 46 insertions(+), 31 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c index 9aa6fe081a27..6c2db5d83b06 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c @@ -223,6 +223,45 @@ static struct sun4i_ss_alg_template ss_algs[] = { #endif }; +static void sun4i_ss_disable(struct sun4i_ss_ctx *ss) +{ + if (ss->reset) + reset_control_assert(ss->reset); + + clk_disable_unprepare(ss->ssclk); + clk_disable_unprepare(ss->busclk); +} + +static int sun4i_ss_enable(struct sun4i_ss_ctx *ss) +{ + int err; + + err = clk_prepare_enable(ss->busclk); + if (err) { + dev_err(ss->dev, "Cannot prepare_enable busclk\n"); + goto err_enable; + } + + err = clk_prepare_enable(ss->ssclk); + if (err) { + dev_err(ss->dev, "Cannot prepare_enable ssclk\n"); + goto err_enable; + } + + if (ss->reset) { + err = reset_control_deassert(ss->reset); + if (err) { + dev_err(ss->dev, "Cannot deassert reset control\n"); + goto err_enable; + } + } + + return err; +err_enable: + sun4i_ss_disable(ss); + return err; +} + static int sun4i_ss_probe(struct platform_device *pdev) { u32 v; @@ -269,17 +308,9 @@ static int sun4i_ss_probe(struct platform_device *pdev) ss->reset = NULL; } - /* Enable both clocks */ - err = clk_prepare_enable(ss->busclk); - if (err) { - dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); - return err; - } - err = clk_prepare_enable(ss->ssclk); - if (err) { - dev_err(&pdev->dev, "Cannot prepare_enable ssclk\n"); - goto error_ssclk; - } + err = sun4i_ss_enable(ss); + if (err) + goto error_enable; /* * Check that clock have the correct rates given in the datasheet @@ -288,16 +319,7 @@ static int sun4i_ss_probe(struct platform_device *pdev) err = clk_set_rate(ss->ssclk, cr_mod); if (err) { dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n"); - goto error_clk; - } - - /* Deassert reset if we have a reset control */ - if (ss->reset) { - err = reset_control_deassert(ss->reset); - if (err) { - dev_err(&pdev->dev, "Cannot deassert reset control\n"); - goto error_clk; - } + goto error_enable; } /* @@ -387,12 +409,8 @@ static int sun4i_ss_probe(struct platform_device *pdev) break; } } - if (ss->reset) - reset_control_assert(ss->reset); -error_clk: - clk_disable_unprepare(ss->ssclk); -error_ssclk: - clk_disable_unprepare(ss->busclk); +error_enable: + sun4i_ss_disable(ss); return err; } @@ -416,10 +434,7 @@ static int sun4i_ss_remove(struct platform_device *pdev) } writel(0, ss->base + SS_CTL); - if (ss->reset) - reset_control_assert(ss->reset); - clk_disable_unprepare(ss->busclk); - clk_disable_unprepare(ss->ssclk); + sun4i_ss_disable(ss); return 0; } From patchwork Tue Sep 24 08:08:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 174256 Delivered-To: patch@linaro.org Received: by 2002:ac9:19ad:0:0:0:0:0 with SMTP id d45csp3547338oce; Tue, 24 Sep 2019 01:08:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0gN2oeHkTq/tj3voidlHHXIX2pBtQlZnbmdtOHciOfBxQ27MRnpbBjQB1dAYRKMWhZHUs X-Received: by 2002:a50:ee10:: with SMTP id g16mr1276531eds.267.1569312526249; Tue, 24 Sep 2019 01:08:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569312526; cv=none; d=google.com; s=arc-20160816; b=fhcbmj5IDEl3bAIehUWETfPrUKT0xIiz4+Xx22DXuf2xoQKgHQU9FB7slO2Xkmqqj0 m8eozwGfWEXgUd8LpAvxfoVvBjGdXdfC+O+ujnOohuYpUdrdIJV7TE3JlrlZhFVEdKDq SXPKZHSPr1UmhjBUcYf9hesLyrYlZcH+0ucM56syMxkdctWVs5QZRM1tPmP6xjgca8DF LmGLMCOwUF0j+w9FWtiqJOIU9XeTyoAYnS8elF/neUabArgnbC+e7xt8qJI/dndMbU/S D59ByJzOmaO1aj0rbWUTvRIHmJkj8P4v4vlR1tINkzio/5i4e8kdckRYL2vkgvR+mE13 LVpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DwEGlosvlSVMLBK3ol5CDT+bd0+LlPSV0LuoF97/hH8=; b=At0Zpqy/S2XZjBHTu2LZAi8YfcFeDqqxehIHMYrZ3v+n+X3qaQKIsPTAyCBRakNdj1 NUXXhZsI89gEeoMRJPlZ4Tim7KbuHNbtnC3DD0OQgpknBX5sfmfKIGPnRbuW73KIdewr nH4YS99Hfh4iQSWeakITjJBsn42ydVTW3xv2/Ywk3C6lsM5dsnNvzWojHntZzbNC2WTN ndujEKhvRkh2kJkGTf72GbMll2+Dg0jrt9CVi9cS5V2Dga84qk1aWPkJ062pUiFdrclP 5hCmekezpxn8Z5HUCdy1A8uYCXrvfZaxNR7+4vfyxPrVv3/THZAcoQCBnR7fcKzVTDt3 Ma4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BUN+yrWo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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But this is not a problem since arch maintainer want ARCH_SUNXI to depend on PM in the future. Signed-off-by: Corentin Labbe --- drivers/crypto/Kconfig | 1 + drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 10 +++ drivers/crypto/sunxi-ss/sun4i-ss-core.c | 82 ++++++++++++++++++----- drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 12 ++++ drivers/crypto/sunxi-ss/sun4i-ss-prng.c | 9 ++- drivers/crypto/sunxi-ss/sun4i-ss.h | 2 + 6 files changed, 97 insertions(+), 19 deletions(-) -- 2.21.0 Acked-by: Maxime Ripard diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 980b0844918b..ee53660b532c 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -662,6 +662,7 @@ config CRYPTO_DEV_IMGTEC_HASH config CRYPTO_DEV_SUN4I_SS tristate "Support for Allwinner Security System cryptographic accelerator" depends on ARCH_SUNXI && !64BIT + depends on PM select CRYPTO_MD5 select CRYPTO_SHA1 select CRYPTO_AES diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c index fa4b1b47822e..93acec22e42f 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c @@ -480,6 +480,7 @@ int sun4i_ss_cipher_init(struct crypto_tfm *tfm) struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm); struct sun4i_ss_alg_template *algt; const char *name = crypto_tfm_alg_name(tfm); + int err; memset(op, 0, sizeof(struct sun4i_tfm_ctx)); @@ -497,13 +498,22 @@ int sun4i_ss_cipher_init(struct crypto_tfm *tfm) return PTR_ERR(op->fallback_tfm); } + err = pm_runtime_get_sync(op->ss->dev); + if (err < 0) + goto error_pm; + return 0; +error_pm: + crypto_free_sync_skcipher(op->fallback_tfm); + return err; } void sun4i_ss_cipher_exit(struct crypto_tfm *tfm) { struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm); + crypto_free_sync_skcipher(op->fallback_tfm); + pm_runtime_put(op->ss->dev); } /* check and set the AES key, prepare the mode to be used */ diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c b/drivers/crypto/sunxi-ss/sun4i-ss-core.c index 6c2db5d83b06..814cd12149a9 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c @@ -44,7 +44,8 @@ static struct sun4i_ss_alg_template ss_algs[] = { .cra_blocksize = MD5_HMAC_BLOCK_SIZE, .cra_ctxsize = sizeof(struct sun4i_req_ctx), .cra_module = THIS_MODULE, - .cra_init = sun4i_hash_crainit + .cra_init = sun4i_hash_crainit, + .cra_exit = sun4i_hash_craexit, } } } @@ -70,7 +71,8 @@ static struct sun4i_ss_alg_template ss_algs[] = { .cra_blocksize = SHA1_BLOCK_SIZE, .cra_ctxsize = sizeof(struct sun4i_req_ctx), .cra_module = THIS_MODULE, - .cra_init = sun4i_hash_crainit + .cra_init = sun4i_hash_crainit, + .cra_exit = sun4i_hash_craexit, } } } @@ -223,17 +225,26 @@ static struct sun4i_ss_alg_template ss_algs[] = { #endif }; -static void sun4i_ss_disable(struct sun4i_ss_ctx *ss) +/* + * Power management strategy: The device is suspended unless a TFM exists for + * one of the algorithms proposed by this driver. + */ +static int sun4i_ss_pm_suspend(struct device *dev) { + struct sun4i_ss_ctx *ss = dev_get_drvdata(dev); + if (ss->reset) reset_control_assert(ss->reset); clk_disable_unprepare(ss->ssclk); clk_disable_unprepare(ss->busclk); + return 0; } -static int sun4i_ss_enable(struct sun4i_ss_ctx *ss) +static int sun4i_ss_pm_resume(struct device *dev) { + struct sun4i_ss_ctx *ss = dev_get_drvdata(dev); + int err; err = clk_prepare_enable(ss->busclk); @@ -258,10 +269,38 @@ static int sun4i_ss_enable(struct sun4i_ss_ctx *ss) return err; err_enable: - sun4i_ss_disable(ss); + sun4i_ss_pm_suspend(dev); + return err; +} + +const struct dev_pm_ops sun4i_ss_pm_ops = { + SET_RUNTIME_PM_OPS(sun4i_ss_pm_suspend, sun4i_ss_pm_resume, NULL) +}; + +/* + * When power management is enabled, this function enables the PM and set the + * device as suspended + * When power management is disabled, this function just enables the device + */ +static int sun4i_ss_pm_init(struct sun4i_ss_ctx *ss) +{ + int err; + + pm_runtime_use_autosuspend(ss->dev); + pm_runtime_set_autosuspend_delay(ss->dev, 2000); + + err = pm_runtime_set_suspended(ss->dev); + if (err) + return err; + pm_runtime_enable(ss->dev); return err; } +static void sun4i_ss_pm_exit(struct sun4i_ss_ctx *ss) +{ + pm_runtime_disable(ss->dev); +} + static int sun4i_ss_probe(struct platform_device *pdev) { u32 v; @@ -308,10 +347,6 @@ static int sun4i_ss_probe(struct platform_device *pdev) ss->reset = NULL; } - err = sun4i_ss_enable(ss); - if (err) - goto error_enable; - /* * Check that clock have the correct rates given in the datasheet * Try to set the clock to the maximum allowed @@ -319,7 +354,7 @@ static int sun4i_ss_probe(struct platform_device *pdev) err = clk_set_rate(ss->ssclk, cr_mod); if (err) { dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n"); - goto error_enable; + return err; } /* @@ -347,12 +382,26 @@ static int sun4i_ss_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n", cr, cr / 1000000, cr_mod); + ss->dev = &pdev->dev; + platform_set_drvdata(pdev, ss); + + spin_lock_init(&ss->slock); + + err = sun4i_ss_pm_init(ss); + if (err) + return err; + /* * Datasheet named it "Die Bonding ID" * I expect to be a sort of Security System Revision number. * Since the A80 seems to have an other version of SS * this info could be useful */ + + err = pm_runtime_get_sync(ss->dev); + if (err < 0) + goto error_pm; + writel(SS_ENABLED, ss->base + SS_CTL); v = readl(ss->base + SS_CTL); v >>= 16; @@ -360,9 +409,7 @@ static int sun4i_ss_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Die ID %d\n", v); writel(0, ss->base + SS_CTL); - ss->dev = &pdev->dev; - - spin_lock_init(&ss->slock); + pm_runtime_put_sync(ss->dev); for (i = 0; i < ARRAY_SIZE(ss_algs); i++) { ss_algs[i].ss = ss; @@ -392,7 +439,6 @@ static int sun4i_ss_probe(struct platform_device *pdev) break; } } - platform_set_drvdata(pdev, ss); return 0; error_alg: i--; @@ -409,8 +455,8 @@ static int sun4i_ss_probe(struct platform_device *pdev) break; } } -error_enable: - sun4i_ss_disable(ss); +error_pm: + sun4i_ss_pm_exit(ss); return err; } @@ -433,8 +479,7 @@ static int sun4i_ss_remove(struct platform_device *pdev) } } - writel(0, ss->base + SS_CTL); - sun4i_ss_disable(ss); + sun4i_ss_pm_exit(ss); return 0; } @@ -449,6 +494,7 @@ static struct platform_driver sun4i_ss_driver = { .remove = sun4i_ss_remove, .driver = { .name = "sun4i-ss", + .pm = &sun4i_ss_pm_ops, .of_match_table = a20ss_crypto_of_match_table, }, }; diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c index fcffba5ef927..9930c9ce8971 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-hash.c @@ -19,17 +19,29 @@ int sun4i_hash_crainit(struct crypto_tfm *tfm) struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm); struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); struct sun4i_ss_alg_template *algt; + int err; memset(op, 0, sizeof(struct sun4i_tfm_ctx)); algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash); op->ss = algt->ss; + err = pm_runtime_get_sync(op->ss->dev); + if (err < 0) + return err; + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct sun4i_req_ctx)); return 0; } +void sun4i_hash_craexit(struct crypto_tfm *tfm) +{ + struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm); + + pm_runtime_put(op->ss->dev); +} + /* sun4i_hash_init: initialize request context */ int sun4i_hash_init(struct ahash_request *areq) { diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-prng.c b/drivers/crypto/sunxi-ss/sun4i-ss-prng.c index 63d636424161..729aafdbea84 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss-prng.c +++ b/drivers/crypto/sunxi-ss/sun4i-ss-prng.c @@ -17,7 +17,7 @@ int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src, { struct sun4i_ss_alg_template *algt; struct rng_alg *alg = crypto_rng_alg(tfm); - int i; + int i, err; u32 v; u32 *data = (u32 *)dst; const u32 mode = SS_OP_PRNG | SS_PRNG_CONTINUE | SS_ENABLED; @@ -28,6 +28,10 @@ int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src, algt = container_of(alg, struct sun4i_ss_alg_template, alg.rng); ss = algt->ss; + err = pm_runtime_get_sync(ss->dev); + if (err < 0) + return err; + spin_lock_bh(&ss->slock); writel(mode, ss->base + SS_CTL); @@ -52,5 +56,8 @@ int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src, writel(0, ss->base + SS_CTL); spin_unlock_bh(&ss->slock); + + pm_runtime_put(ss->dev); + return 0; } diff --git a/drivers/crypto/sunxi-ss/sun4i-ss.h b/drivers/crypto/sunxi-ss/sun4i-ss.h index 35a27a7145f8..60425ac75d90 100644 --- a/drivers/crypto/sunxi-ss/sun4i-ss.h +++ b/drivers/crypto/sunxi-ss/sun4i-ss.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -177,6 +178,7 @@ struct sun4i_req_ctx { }; int sun4i_hash_crainit(struct crypto_tfm *tfm); +void sun4i_hash_craexit(struct crypto_tfm *tfm); int sun4i_hash_init(struct ahash_request *areq); int sun4i_hash_update(struct ahash_request *areq); int sun4i_hash_final(struct ahash_request *areq);