From patchwork Mon Sep 30 11:40:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174739 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7007715ill; Mon, 30 Sep 2019 04:40:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqywqOk5VAJRUH5GxW4nmt/bah6bieaTVKOmT88ePKsrNlM4CUKxuofTINSpHLftCdo+25iU X-Received: by 2002:a17:906:b6d5:: with SMTP id ec21mr18151025ejb.33.1569843628639; Mon, 30 Sep 2019 04:40:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569843628; cv=none; d=google.com; s=arc-20160816; b=qrE8XR4XqfOoHRP7hnDTuHR0EXud+IIyreXARnPl8LMlRL/8+0zov7ErZZnXZXn/s/ rc5T4mzimpMwpZtRWa7VJrVi04/+cUUhjhKvbyUUezkJkEn3BEmVFJGiWkdCeT8boBw5 S21t1wF/4d43gbeXpfVG+HEOOEiaw1kI0YW8VbKML6+iKIUdqfdJRwJc4zkwPHTDVp8b XtQKSHLSMucYsZaZUHtR++y5uQMAkrsrV7597U5ml3UbPMtWGKO/eRuEb5fadl+a3g6g q8qvF0v1GQfs1bMzPtbUwAcha5caU1Ynkd2xzwH6kzD5EcypKBS9U+eZJ9Ck/O/FeWy+ 2gow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DVgmIFbDsMxJJSm/SVGd9TdiqZgDPzIcalnycvRo6aY=; b=q40uhnBFpn/YxMNqFkIVg3Xh1EKOdvNULkHjwP+IHEgwSIOt2s0MkGx/Eut/V/BSJH qnUzpRuk8o7CFtsn8w2y6aX+tL73lOg10ZNTT6PUrCSCeQr+e5Z4zUuD+tgMyW3mYaWZ sDYPzeZ/jIQA1XvxH3vXvP9wfU2EpnDDASk7LIhIg0hPrF/hdjx0++qm7DxeqLiarAdr etBP+9D1eNtg5N+bJVnljng8b29/rl/Ggy5FSfKiYV2hwdQNz0dCOMt7x5EelT+GzeYX 9CVT9571Fn7pibLnocXkqeXmlkLSTt4WXZ6GMtOFhPg/aczj8zqt48Mmn4rBY6CHgSZL hBBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ADXMXkBU; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t10si6634717edd.447.2019.09.30.04.40.28; Mon, 30 Sep 2019 04:40:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ADXMXkBU; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730204AbfI3Lk1 (ORCPT + 3 others); Mon, 30 Sep 2019 07:40:27 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44456 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730015AbfI3Lk0 (ORCPT ); Mon, 30 Sep 2019 07:40:26 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8UBeDoU012241; Mon, 30 Sep 2019 06:40:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569843613; bh=DVgmIFbDsMxJJSm/SVGd9TdiqZgDPzIcalnycvRo6aY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ADXMXkBUhZuNGUROhkNLF963ciFJGhEV15nNiPoGS2qMGYly/kql68nTvB9V/upTu 1yNn9nxB8G+TXtFWkYzP9RTkt9Yjd0ZvkeeOfUoTDDaZ+3HxKucKu7qadD3Dc2dPFd H2d4csLnxMoxN6cnxBLbaEfadV8PMKlmwz35nZ/4= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8UBeDSQ023753 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 30 Sep 2019 06:40:13 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 30 Sep 2019 06:40:03 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 30 Sep 2019 06:40:03 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8UBe8Xp096764; Mon, 30 Sep 2019 06:40:11 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v4 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array Date: Mon, 30 Sep 2019 14:40:53 +0300 Message-ID: <20190930114055.29315-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190930114055.29315-1-peter.ujfalusi@ti.com> References: <20190930114055.29315-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Make the dma-channel-mask to be usable for controllers with more than 32 channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/dma-common.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/dma-common.yaml b/Documentation/devicetree/bindings/dma/dma-common.yaml index ed0a49a6f020..02a34ba2b49b 100644 --- a/Documentation/devicetree/bindings/dma/dma-common.yaml +++ b/Documentation/devicetree/bindings/dma/dma-common.yaml @@ -25,11 +25,18 @@ properties: Used to provide DMA controller specific information. dma-channel-mask: - $ref: /schemas/types.yaml#definitions/uint32 description: Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB. + The first item in the array is for channels 0-31, the second is for + channels 32-63, etc. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 1 + # Should be enough + maxItems: 255 dma-channels: $ref: /schemas/types.yaml#definitions/uint32 From patchwork Mon Sep 30 11:40:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174737 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7007615ill; Mon, 30 Sep 2019 04:40:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqz4mAjh7Kg143mMN1wHDjTVPZwPukrVdSxBDGZTU9v4raLeiylB5e97OqtzGTEng01xxpwv X-Received: by 2002:a17:906:e0c2:: with SMTP id gl2mr18884326ejb.157.1569843622900; Mon, 30 Sep 2019 04:40:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569843622; cv=none; d=google.com; s=arc-20160816; b=yO2PNa9nIacVphSRqJJlTW1OXAzpyFifIyr1TyUeLIAY5S3Ir/o+pLKJ15KtZOJOQU XFiihHp12A4z6hQ8bmO31Qy1EeORLVXQbVtHmc80TY3yUjTn3/Eu+AuM9ClDLZX5BDcu wNSxoLVOs3Rh5SjVvQ/gr9vzS9knasL8bhcF9zEuiGkbJ4KFvta31rjkj74hZ4QyRVUN Tb/N0uJ7G4vFP8NY9zYWRHbPRuEC6bciG0IaMr+U1Zj5iTiTlGA0xihqsnIwA4tIejra SAFncodJPwIckOwvm9S4J3oa83FCgugCjz8FY5mz1AqhHuj6VEA7ZrQEariFQyQIujUh NE8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vIHWn80kaOCM9NgAhQjVmDfgh8/iX+ipwrUeEHUNAfQ=; b=0vbQisw0Z40B5hJLWZvI1/Q3XhkFJa175T3E1Byz6FOsLxMvXKeUwWwvbLtM3+irbv 4mpE8pj5q9s4IupxB19BEObhDWvxS8uQPhpDb6/UVLqmvxrOyhNO/2j5tsfjPqrgJRG5 kjmKqFN7yNtP3KJircypBzQyVRrOAFV5VyUfsc9VAazytuN6NXzcHtSePbCtpa0KfSA3 5/iJp9fvHXK6WW3u6oP5Aq/KnwgsOjYuUPr0/WzZq7hw9FQPS3b/1+hGcwCMPBM/FjWt r6f4k8m5aSujh6H8Q0InXpi2H06mFzlT/elc1r3u37fg8PZ/9laJCMEp2ro2mQs/AR1q VqXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="O/fWdyYy"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The common dma-channel-mask property can be used for specifying the available channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/ti-edma.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 4bbc94d829c8..0e1398f93aa2 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -42,6 +42,11 @@ Optional properties: - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by the driver, they are allocated to be used by for example the DSP. See example. +- dma-channel-mask: Mask of usable channels. + Single uint32 for EDMA with 32 channels, array of two uint32 for + EDMA with 64 channels. See example and + Documentation/devicetree/bindings/dma/dma-common.yaml + ------------------------------------------------------------------------------ eDMA3 Transfer Controller @@ -91,6 +96,9 @@ edma: edma@49000000 { ti,edma-memcpy-channels = <20 21>; /* The following PaRAM slots are reserved: 35-44 and 100-109 */ ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + dma-channel-mask = <0xffffffff /* Channel 0-31 */ + 0xffffe007>; /* Channel 32-63 */ }; edma_tptc0: tptc@49800000 {