From patchwork Wed Oct 2 12:15:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 174989 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp677939ill; Wed, 2 Oct 2019 05:16:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqxy+J8UGOD7Wn3Vif7Xw12aEXZk2cYpM4PIpfgzSJowb7PEHcY0WqzQdzIb7R2rU1iyZu3+ X-Received: by 2002:a17:906:e0c2:: with SMTP id gl2mr2701642ejb.157.1570018566413; Wed, 02 Oct 2019 05:16:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570018566; cv=none; d=google.com; s=arc-20160816; b=e+Yg6dMlzmaK+kD+sqjVapxES9mQAWT/OlnpjgW6p8MuugDX82KYXNm4WxjeOBx+Qv ptQm9/X0xfj+2WZM1o4jPMokBOTt/RQ0920IDtC4mCbbxBm0kXF/jQynC2gV8eAcCZd1 JnU11ht+cvGE0ZsrIStOVo/t/GZ9Ug3ukoILqxpROi/4kzvabhpvfcJC/YAawglWe/Xc a6AN9+20fDER3ZOa8+y3oL7C9s1PyysMGKJ/6qqlKWLTpDJ5RhldNucpAUQ/IsyTWvaP PvGBCe9kQuEFur5vuAOacHPxxRs7apssMzD00GzbrrVVBVOquE7fXhJXJ4CGK9DGi4yn 2Hcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=ImypWLeaPw/IThbY3ERMJs+WlUwaWz3UPu+vStY0+xg=; b=sLZMCCiEiEjmnHwq/CSVPhHMq3yC8hnl9OjechLTpmi7TuU4BYV3H15FhKz4M+Bv4y ZiadyPKFGqPwoXAI5dfZ/jAduEyQBbRclbWHsKG4ogMmyVVN9N+EVgdL5of8j4gRX87t HY+S1vrSE/WPD+KqQ+Qf2IgS7GqmmKZYDrkAtFwxqfjPCZJk/t9MH/4NrTvC9xrDDNvM s4xF/IPYib+Yo2+fX9kW4jF1Z9loT3tkTB5Q9QGgexdkGUhjpXQ1jFZcioRfECbw5JrU CH6yas3ksYdy2XNPlnky9KN2ChImYTwfQkYifKmXtTteHggxnZrtgRZAIX+dqGM4RXmF o0mQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CPGdgpHC; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l26si11312467edb.258.2019.10.02.05.16.06; Wed, 02 Oct 2019 05:16:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CPGdgpHC; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725766AbfJBMQF (ORCPT + 5 others); Wed, 2 Oct 2019 08:16:05 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:35213 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfJBMQF (ORCPT ); Wed, 2 Oct 2019 08:16:05 -0400 Received: by mail-lf1-f66.google.com with SMTP id w6so12565415lfl.2 for ; Wed, 02 Oct 2019 05:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ImypWLeaPw/IThbY3ERMJs+WlUwaWz3UPu+vStY0+xg=; b=CPGdgpHCbq+lLfgVY/gDSJX9rdNp01d0LUHV1NXeg8xuiuYoynZPKp7MGH02ZbWXfv KbQ15+7lUuDNiBUZ8fRrsHTn9Y3UQkvKSGO/OClC9Uce/Bkm6nccasrIOj/j6vqeqtvW JEoD/HWTR8sE3rWY1de7vHb34aSnSqVhzOfy7kJM5nDJvM2udWPFMbrIhNDxSbT9ivdM iKaC6fI+PW0McZ6fdJANuefGd0lqlRpAmHwzjqbvtK961HkAKImAwYUZYyigPX/pufOP tN+ICf5RYnDsjjazrpi3/m2w0lLodpt/Yf7PxkaDsHmMkDzSqLpNb6iBfn132gc+hE8J 5yHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ImypWLeaPw/IThbY3ERMJs+WlUwaWz3UPu+vStY0+xg=; b=UT82UCTOMpEnq7TO9qS6cf+KxVgLXP9hNwNqBLMwtzZbfPRh8wcHCgzcRhfiwexrRb 111F3mmfJA6T4m6Z/HpM1yWUp1MDa6UGGHepW/ZV8ZxhE5Rh0UR+2/NTnNuLM2Gpheh+ azY3O+kDHmzkn8YXkVWog2d4dAjkD7C9OqpQkXMq55Mi2lDEiJGWGcA1674x9pFufN2b p6QDSyk+csg9+kjijQYMMtGOKhsGesmXxzH6Mdpn20pEPPCUgseI676AUJtx7Zk49bJE LK6NYnlzbrWVwK6U8Im9xu7JsR5zSzXOkl54VOxP7S67SISFKL1xvGOw1FtMycK16LhF QkTw== X-Gm-Message-State: APjAAAVzT7BlS3K2CLd2VubTpyG6XPH9aAOg/YktvkLTOa03kpRrhN9C oRQ6xD7PnoaNvCxcEwXW1JBKultdcD++2A== X-Received: by 2002:ac2:558e:: with SMTP id v14mr2119401lfg.161.1570018562917; Wed, 02 Oct 2019 05:16:02 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id a8sm4725441ljf.47.2019.10.02.05.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 05:16:01 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Miquel Raynal , Gregory CLEMENT , =?utf-8?q?Marek_Beh=C3=BAn?= , Thierry Reding Subject: [PATCH] pinctrl: armada-37xx: Pass irqchip when adding gpiochip Date: Wed, 2 Oct 2019 14:15:50 +0200 Message-Id: <20191002121550.16104-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Miquel Raynal Cc: Gregory CLEMENT Cc: Marek Behún Cc: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 34 ++++++++++++--------- 1 file changed, 19 insertions(+), 15 deletions(-) -- 2.21.0 diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 6462d3ca7ceb..952cf4e87e82 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -722,6 +722,8 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, struct device_node *np = info->dev->of_node; struct gpio_chip *gc = &info->gpio_chip; struct irq_chip *irqchip = &info->irq_chip; + struct gpio_irq_chip *girq = &gc->irq; + struct device *dev = &pdev->dev; struct resource res; int ret = -ENODEV, i, nr_irq_parent; @@ -732,19 +734,21 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, break; } }; - if (ret) + if (ret) { + dev_err(dev, "no gpio-controller child node\n"); return ret; + } nr_irq_parent = of_irq_count(np); spin_lock_init(&info->irq_lock); if (!nr_irq_parent) { - dev_err(&pdev->dev, "Invalid or no IRQ\n"); + dev_err(dev, "invalid or no IRQ\n"); return 0; } if (of_address_to_resource(info->dev->of_node, 1, &res)) { - dev_err(info->dev, "cannot find IO resource\n"); + dev_err(dev, "cannot find IO resource\n"); return -ENOENT; } @@ -759,27 +763,27 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, irqchip->irq_set_type = armada_37xx_irq_set_type; irqchip->irq_startup = armada_37xx_irq_startup; irqchip->name = info->data->name; - ret = gpiochip_irqchip_add(gc, irqchip, 0, - handle_edge_irq, IRQ_TYPE_NONE); - if (ret) { - dev_info(&pdev->dev, "could not add irqchip\n"); - return ret; - } - + girq->chip = irqchip; + girq->parent_handler = armada_37xx_irq_handler; /* * Many interrupts are connected to the parent interrupt * controller. But we do not take advantage of this and use * the chained irq with all of them. */ + girq->num_parents = nr_irq_parent; + girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; for (i = 0; i < nr_irq_parent; i++) { int irq = irq_of_parse_and_map(np, i); if (irq < 0) continue; - - gpiochip_set_chained_irqchip(gc, irqchip, irq, - armada_37xx_irq_handler); + girq->parents[i] = irq; } + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; return 0; } @@ -809,10 +813,10 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, gc->of_node = np; gc->label = info->data->name; - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); + ret = armada_37xx_irqchip_register(pdev, info); if (ret) return ret; - ret = armada_37xx_irqchip_register(pdev, info); + ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret;