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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id e6sm1002856pfl.146.2019.10.02.21.23.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 21:23:01 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Wed, 2 Oct 2019 21:22:48 -0700 Message-Id: <20191003042249.2147767-1-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [OE-core] [PATCH 1/2] musl: Update to latest X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Drop upstream'ed patch Fix libgcc build with musl Detailed ChangeLog [1] [1] https://git.musl-libc.org/cgit/musl/log/?qt=range&q=1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272..2c2477da9a553c0b9b2fa18073a5dcdbe6d395af Signed-off-by: Khem Raj --- ...-for-riscv-floating-point-state-to-_.patch | 67 ------------------- ...and-specifiers-in-the-riscv64-CAS-ro.patch | 55 --------------- .../0001-riscv-Define-sigcontext-again.patch | 48 +++++++++++++ meta/recipes-core/musl/musl_git.bb | 5 +- 4 files changed, 50 insertions(+), 125 deletions(-) delete mode 100644 meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch delete mode 100644 meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch create mode 100644 meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch b/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch deleted file mode 100644 index a9abb18726..0000000000 --- a/meta/recipes-core/musl/musl/0001-Change-container-for-riscv-floating-point-state-to-_.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 52a37610650e7366a398dd07393d3902d2f3faa3 Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Sat, 28 Sep 2019 12:19:57 -0700 -Subject: [PATCH] Change container for riscv floating-point state to __riscv_mc_fp_state - -Match the struct elements with glibc -glibc also uses __riscv_mc prefix, some packages like gdb uses that - -Upstream-Status: Submitted [https://www.openwall.com/lists/musl/2019/09/28/1] -Signed-off-by: Khem Raj ---- - arch/riscv64/bits/signal.h | 18 +++++++++--------- - arch/riscv64/bits/user.h | 2 +- - 2 files changed, 10 insertions(+), 10 deletions(-) - -diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h -index 76d7ad80..aba7ab00 100644 ---- a/arch/riscv64/bits/signal.h -+++ b/arch/riscv64/bits/signal.h -@@ -13,25 +13,25 @@ typedef unsigned long greg_t; - typedef unsigned long gregset_t[32]; - - struct __riscv_mc_f_ext_state { -- unsigned int f[32]; -- unsigned int fcsr; -+ unsigned int __f[32]; -+ unsigned int __fcsr; - }; - - struct __riscv_mc_d_ext_state { -- unsigned long long f[32]; -- unsigned int fcsr; -+ unsigned long long __f[32]; -+ unsigned int __fcsr; - }; - - struct __riscv_mc_q_ext_state { -- unsigned long long f[64] __attribute__((aligned(16))); -- unsigned int fcsr; -+ unsigned long long __f[64] __attribute__((aligned(16))); -+ unsigned int __fcsr; - unsigned int reserved[3]; - }; - - union __riscv_mc_fp_state { -- struct __riscv_mc_f_ext_state f; -- struct __riscv_mc_d_ext_state d; -- struct __riscv_mc_q_ext_state q; -+ struct __riscv_mc_f_ext_state __f; -+ struct __riscv_mc_d_ext_state __d; -+ struct __riscv_mc_q_ext_state __q; - }; - - typedef union __riscv_mc_fp_state fpregset_t; -diff --git a/arch/riscv64/bits/user.h b/arch/riscv64/bits/user.h -index d2e383b2..9918a2fe 100644 ---- a/arch/riscv64/bits/user.h -+++ b/arch/riscv64/bits/user.h -@@ -5,4 +5,4 @@ struct user_fpregs_struct { - - #define ELF_NGREG 32 - typedef unsigned long elf_greg_t, elf_gregset_t[ELF_NGREG]; --typedef struct user_fpregs_struct elf_fpregset_t; -+typedef union __riscv_mc_fp_state elf_fpregset_t; --- -2.23.0 - diff --git a/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch b/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch deleted file mode 100644 index 09b71cb299..0000000000 --- a/meta/recipes-core/musl/musl/0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 59f2954fcaacd9426827c69a729e2647cb9977e5 Mon Sep 17 00:00:00 2001 -From: Palmer Dabbelt -Date: Tue, 24 Sep 2019 20:30:15 -0700 -Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines - -The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect: -there's a backwards branch in the routine, so despite tmp being written -at the end of the assembly fragment it cannot be allocated in one of the -input registers because the input values may be needed for another trip -around the loop. - -For code that follows the guarnteed forward progress requirements, he -backwards branch is rarely taken: SiFive's hardware only fails a store -conditional on execptional cases (ie, instruction cache misses inside -the loop), and until recently a bug in QEMU allowed back-to-back -store conditionals to succeed. The bug has been fixed in the latest -QEMU release, but it turns out that the fix caused this latent bug in -musl to manifest. - -Full disclosure: I haven't actually even compiled musl. I just guessed -this would fix a bug introducted by the new QEMU behavior, Alistair -(CC'd) actually checked it fixes the problem. The rest is just -conjecture. - -Upstream-Status: Submitted -Signed-off-by: Khem Raj ---- - arch/riscv64/atomic_arch.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h -index c9765342..41ad4d04 100644 ---- a/arch/riscv64/atomic_arch.h -+++ b/arch/riscv64/atomic_arch.h -@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s) - " sc.w.aqrl %1, %4, (%2)\n" - " bnez %1, 1b\n" - "1:" -- : "=&r"(old), "=r"(tmp) -+ : "=&r"(old), "=&r"(tmp) - : "r"(p), "r"(t), "r"(s) - : "memory"); - return old; -@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) - " sc.d.aqrl %1, %4, (%2)\n" - " bnez %1, 1b\n" - "1:" -- : "=&r"(old), "=r"(tmp) -+ : "=&r"(old), "=&r"(tmp) - : "r"(p), "r"(t), "r"(s) - : "memory"); - return old; --- -2.23.0 - diff --git a/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch b/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch new file mode 100644 index 0000000000..fcb324e15f --- /dev/null +++ b/meta/recipes-core/musl/musl/0001-riscv-Define-sigcontext-again.patch @@ -0,0 +1,48 @@ +commit a0993f8f0f161423ecdcb754f282ffd2fe47a7b5 +Author: Rich Felker +Date: Wed Oct 2 09:28:03 2019 -0400 + + reintroduce riscv64 struct sigcontext + + commit ab3eb89a8b83353cdaab12ed017a67a7730f90e9 removed it as part of + correcting the mcontext_t definition, but there is still code using + struct sigcontext and expecting the member names present in it, most + notably libgcc_eh. almost all such usage is incorrect, but bring back + struct sigcontext at least for now so as not to introduce regressions. + +Upstream-Status: Pending +Signed-off-by: Khem Raj +diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h +index 03fe48c1..2ff4be30 100644 +--- a/arch/riscv64/bits/signal.h ++++ b/arch/riscv64/bits/signal.h +@@ -6,12 +6,6 @@ + # define SIGSTKSZ 8192 + #endif + +-#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE) +-typedef unsigned long greg_t; +-typedef unsigned long gregset_t[32]; +-typedef union __riscv_mc_fp_state fpregset_t; +-#endif +- + typedef unsigned long __riscv_mc_gp_state[32]; + + struct __riscv_mc_f_ext_state { +@@ -41,6 +35,16 @@ typedef struct mcontext_t { + union __riscv_mc_fp_state __fpregs; + } mcontext_t; + ++#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE) ++typedef unsigned long greg_t; ++typedef unsigned long gregset_t[32]; ++typedef union __riscv_mc_fp_state fpregset_t; ++struct sigcontext { ++ gregset_t gregs; ++ fpregset_t fpregs; ++}; ++#endif ++ + struct sigaltstack { + void *ss_sp; + int ss_flags; diff --git a/meta/recipes-core/musl/musl_git.bb b/meta/recipes-core/musl/musl_git.bb index 13fd17353d..aacff79f7c 100644 --- a/meta/recipes-core/musl/musl_git.bb +++ b/meta/recipes-core/musl/musl_git.bb @@ -4,7 +4,7 @@ require musl.inc inherit linuxloader -SRCREV = "1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272" +SRCREV = "2c2477da9a553c0b9b2fa18073a5dcdbe6d395af" BASEVER = "1.1.23" @@ -15,8 +15,7 @@ PV = "${BASEVER}+git${SRCPV}" SRC_URI = "git://git.musl-libc.org/musl \ file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \ file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \ - file://0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch \ - file://0001-Change-container-for-riscv-floating-point-state-to-_.patch \ + file://0001-riscv-Define-sigcontext-again.patch \ " S = "${WORKDIR}/git" From patchwork Thu Oct 3 04:22:49 2019 Content-Type: text/plain; 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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id e6sm1002856pfl.146.2019.10.02.21.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 21:23:01 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Wed, 2 Oct 2019 21:22:49 -0700 Message-Id: <20191003042249.2147767-2-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191003042249.2147767-1-raj.khem@gmail.com> References: <20191003042249.2147767-1-raj.khem@gmail.com> MIME-Version: 1.0 Subject: [OE-core] [PATCH 2/2] qemu: Add ppc64 to QEMU_TARGETS X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org helps with qemuppc target Signed-off-by: Khem Raj --- meta/recipes-devtools/qemu/qemu.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc index de21d30732..551b49ac0a 100644 --- a/meta/recipes-devtools/qemu/qemu.inc +++ b/meta/recipes-devtools/qemu/qemu.inc @@ -53,7 +53,7 @@ do_install_ptest() { } # QEMU_TARGETS is overridable variable -QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel mips64 mips64el ppc riscv32 riscv64 sh4 x86_64" +QEMU_TARGETS ?= "arm aarch64 i386 mips mipsel mips64 mips64el ppc ppc64 riscv32 riscv64 sh4 x86_64" EXTRA_OECONF = " \ --prefix=${prefix} \