From patchwork Fri Apr 5 08:41:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 786297 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D249F15FA74 for ; Fri, 5 Apr 2024 08:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712306499; cv=none; b=KSbFEDw+eWUhGZtm1B8eYygQ36kBdTC4oXM1Hup+AB7oMXK2ihD8kKqc81upF6V07zqTFG8YUEPqWDXD4sQ2QwTyYwasuaTdtWRftQWlGIJuGPfg2Sk9kDNqS9qonqpc4wWx612fwMZIyCZ0LvX1NE9ll9lvEjCu6EMJYtw6c38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712306499; c=relaxed/simple; bh=LuuIzVsI75M9BD4RB9Xpg8kuNSHIGgEeoiwcYByrbOc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c5LgTRY6AboPUmSMBSrYkXxv84kbo/rB5oy2T2FLOZryXjoXuV3OM25CcCKIMJCTP1EQQhaaMJU8eW5OV+2M5uPJeZp36WNqbNeLm65Zc4inRAi1A7CR1u7N/IXGS6K0WXzRXgXF0qwGbE/Iw+DcS+uhCAzjnkwVffnuqe/dvWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZhC0TEd4; arc=none smtp.client-ip=209.85.208.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZhC0TEd4" Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-2d094bc2244so19634261fa.1 for ; Fri, 05 Apr 2024 01:41:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712306496; x=1712911296; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hrz6dTaTK0KlWdsP16Esc0J5gm77xoC0tsefEzseqJI=; b=ZhC0TEd4+e81u48ovoHh4FgJ4xUAgfsR+mRFhgv6xQtLynN65KWbfiH/HjD5P4nva5 vMyo/ZAX9cfliBEQQmSy6DRLqJefUuLrIZySV8zyQGXopJ6R9FlRmBxqUoyslQEc6mg8 38Jyv2lJRDG/T/mIgy7Blw0+LYXcNlrRe3KfyGiUUmfHKr79288B7jiP75BOZcOqdLO2 w6xgrG8OiMj+EYrTFwAhLv6IEikQip4K7AdZeZWUBzSmtpq8FU2ag1NLotxvIZADXwl0 5LhhGDg8Kg3y9P0l8buLlqO1kqQjMCGqL1X3EKpF34QWin+yqTo6WbkayGPqYmlsYU8B VCVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712306496; x=1712911296; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hrz6dTaTK0KlWdsP16Esc0J5gm77xoC0tsefEzseqJI=; b=O+nAZwOkH5BUHVmBcxzGghUVbPqpQDviqu3JEmtGrH6rbM/DKoBLiKTLA+LCquutZF 6YYjl82DNiPMHIbLNJlXPz1kbGLJHYm0yYUQzIVSoX55IjkB94+Vney9OocOUkWVWUo+ pd3wGu8uZPJXqxtwKIKq4SzWUXrqomBvQs/PpgRdJXyw8sHhRtFkSsyrbz+oT0T6M557 aLcBQs61nqKKSXT+z+36SaZ6d18LuQt0A2JgtNHOUcDFqeeS/uSplSVp2t3PiW8tu2Qe 6EwGLAf+xn7lb0qZVJ8WxvbKTtrRCtFtllkd3bvsHSiHmR+czs1IvStWPvALCG8y4J4t 1qQg== X-Gm-Message-State: AOJu0YxeXlgWWdbXje8repfOOVas6lHn4g+CIu8wZSq0JOs6DlzypLzb jIuvGt8Ykmkpmcq1RrO7tX9DLV4BX/Li0Gn8a4k0EZDOibZDfyCK1kLhtkb/PCU= X-Google-Smtp-Source: AGHT+IHl3jTu+OEG685vV8yMxLBRYabQaLyZqwz5PST4j9X2muXdZOgk98CH4aGQdnIUsU0cCkQKzA== X-Received: by 2002:a2e:9658:0:b0:2d8:68ad:1e87 with SMTP id z24-20020a2e9658000000b002d868ad1e87mr671436ljh.18.1712306496187; Fri, 05 Apr 2024 01:41:36 -0700 (PDT) Received: from [127.0.1.1] (netpanel-87-246-222-101.pol.akademiki.lublin.pl. [87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:35 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:30 +0200 Subject: [PATCH 2/6] soc: qcom: smem: Add pcode/fcode getters Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-2-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Introduce getters for SoC product and feature codes and export them. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/smem.c | 66 +++++++++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 2 ++ 2 files changed, 68 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 7191fa0c087f..e89b4d26877a 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -795,6 +795,72 @@ int qcom_smem_get_soc_id(u32 *id) } EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); +/** + * qcom_smem_get_feature_code() - return the feature code + * @id: On success, we return the feature code here. + * + * Look up the feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_feature_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EINVAL; + + raw_code = __le32_to_cpu(info->feature_code); + + /* Ensure the value makes sense */ + if (raw_code >= SOCINFO_FC_INT_RESERVE) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code); + +/** + * qcom_smem_get_product_code() - return the product code + * @id: On success, we return the product code here. + * + * Look up feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_product_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EINVAL; + + raw_code = __le32_to_cpu(info->pcode); + + /* Ensure the value makes sense */ + if (raw_code >= SOCINFO_FC_INT_RESERVE) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_product_code); + static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { struct smem_header *header; diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index a36a3b9d4929..aef8c9fc6c08 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -13,5 +13,7 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); int qcom_smem_get_soc_id(u32 *id); +int qcom_smem_get_feature_code(u32 *code); +int qcom_smem_get_product_code(u32 *code); #endif From patchwork Fri Apr 5 08:41:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 786296 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5EF815FD0A for ; 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:38 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:32 +0200 Subject: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-4-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 39 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++++++--- 4 files changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4cbdfabbcee5..6776fd80f7a6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2890,13 +2890,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -3056,7 +3058,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c3703a51287b..901ef767e491 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..0e4ff532ac3c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1057,9 +1060,37 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode, pcode; + int ret; + + /* Try reading the speedbin via a nvmem cell first */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + if (!ret && ret != -EINVAL) + return ret; + + ret = qcom_smem_get_feature_code(&fcode); + if (ret) { + dev_err(dev, "Couldn't get feature code from SMEM!\n"); + return ret; + } + + ret = qcom_smem_get_product_code(&pcode); + if (ret) { + dev_err(dev, "Couldn't get product code from SMEM!\n"); + return ret; + } + + /* Don't consider fcode for external feature codes */ + if (fcode <= SOCINFO_FC_EXT_RESERVE) + fcode = SOCINFO_FC_UNKNOWN; + + *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) | + FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode); + + return ret; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 460b399be37b..1770a9e20484 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -81,7 +81,12 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; struct adreno_speedbin { - uint16_t fuse; + /* <= 16-bit for NVMEM fuses, 32b for SOCID values */ + uint32_t fuse; +#define ADRENO_SKU_ID_PCODE GENMASK(31, 16) +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(pcode, fcode) (pcode << 16 | fcode) + uint16_t speedbin; }; @@ -137,7 +142,7 @@ struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info; uint32_t chip_id; - uint16_t speedbin; + uint32_t speedbin; const struct adreno_gpu_funcs *funcs; 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:34 +0200 Subject: [PATCH 6/6] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-6-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5cae8d773cec..2f6842f6a5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2087,48 +2087,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };