From patchwork Tue Oct 8 07:19:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175456 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5334647ill; Tue, 8 Oct 2019 00:19:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjMbCurb05WkSIjVmOi3OKzWAJfVHQL+GH5mczH+zJVEQdE0ynRg4/dnVu9MQweweE6yQf X-Received: by 2002:a50:d49c:: with SMTP id s28mr32742052edi.101.1570519182733; Tue, 08 Oct 2019 00:19:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570519182; cv=none; d=google.com; s=arc-20160816; b=uD7xIw+QU3zunONZmPlEgM/il3p1jQxBy1IRUdWRBlzVWujt7xCEdLsTUm+EtzJsPq YhG4VHrzFov+wLcrtZkv3TgBPCppryuIGndyWBFY1Kw24hqHEv4BxDivrP2Hsq+pjZ/v cR5GBwJZF2u8KFlpieK4BayuB5aFbAW3khEBZMjfVUzVgtXi2eQxS74yp5hMs+prOwvJ m9qTMUjO0UIHKzraN6Cgrr1wSxFdIkWmh1xFi3Wj2gGjVEhf7qibd28AJEMK1XTQVKLD BSHwaH4VAyE+NzNPRQJrgDQ5D/4qaBfHxOjczJjj9RbkjtaJavNOQHmH8sjD9+ULz1JL IS2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5NjhrYu8nXMN27ChfH5ORG8Z1ERJZGAOrQx8/HEKMSw=; b=gwYZInp2bZz5cLTEgO8va8aLeopDCXe8F2OhPAzSIWvNNRL7MwHUEE++pLJqKZzxK8 LjNyrpxJW69JmZ++rDaSMN9CV1MQMRJpTnS+bC6s7cFaCaKo/95RlPGgwK3WPpu2eWcs V0fyJchh8qAYM/ndupF1HD3euf2+QSuL9X9m3zeMGWpM7UoOFDanoD36u+VSM7AmvxTf UNXychrVuZJS9QfPbGZDR6LeCMSUWqMJ0Tj03mTsQvwcLPDr4sgav6Nk0AAHCzool5BM HILzgeB6Qb4ueC6qtmTlBAi2N01ZsOEjTDqLi6CnyB61wpVrwvHV8U1oJc2oXwYD8Wph CDtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=epXn03vZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m24si8494415ejx.286.2019.10.08.00.19.42; Tue, 08 Oct 2019 00:19:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=epXn03vZ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730268AbfJHHTh (ORCPT + 8 others); Tue, 8 Oct 2019 03:19:37 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53616 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730161AbfJHHTg (ORCPT ); Tue, 8 Oct 2019 03:19:36 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x987JOKG046282; Tue, 8 Oct 2019 02:19:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570519164; bh=5NjhrYu8nXMN27ChfH5ORG8Z1ERJZGAOrQx8/HEKMSw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=epXn03vZtIrUhAFDrlLkcQdNbgWcClh/3N7cjFxmBi+HcIj7IY6zpC8WitsTOcdm9 Bw0TIgAeURcnmtX9Ad8u93GKIaKuInORxNw6Jon+Uqi8NObZ405NBEooWlUOd+TPwQ BmjmlmZUJJrmM/6lH7/fv8uw6a+b0z60yFtLMP3g= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x987JOC5046068 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 02:19:24 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 02:19:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 02:19:23 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x987JJj4027770; Tue, 8 Oct 2019 02:19:22 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv7 1/9] dt-bindings: omap: add new binding for PRM instances Date: Tue, 8 Oct 2019 10:19:05 +0300 Message-ID: <20191008071913.28740-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008071913.28740-1-t-kristo@ti.com> References: <20191008071913.28740-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo Reviewed-by: Rob Herring Reviewed-by: Tony Lindgren --- v7: - dropped clocks property from example .../devicetree/bindings/arm/omap/prm-inst.txt | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..dfe7c7789ca7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,29 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must contain one of the following: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" + and additionally must contain: + "ti,omap-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,omap-prm-inst", "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; +}; From patchwork Tue Oct 8 07:19:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175454 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5334621ill; Tue, 8 Oct 2019 00:19:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqzJabR2GjZKIzyagDJa4IQCLCmwuWe+kecU2X+wliwtijALXEpPRzokcjA7VHcSHf3obSVO X-Received: by 2002:a17:906:ecea:: with SMTP id qt10mr27210124ejb.23.1570519181418; Tue, 08 Oct 2019 00:19:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570519181; cv=none; d=google.com; s=arc-20160816; b=jY2zYBgef64MNz93ZYmIYG6LDqf7uDtqcks7W1CK7/7v4n19GiTR9FVpThguuRgrxN RtBIFoUkijOOVrFQ/covGlFwd4UghibPeY7qJFu2zxH+XparZNy3ljYBR422IfnhZVQ0 TBGw0q+8WcPlU4xfeilgtw6cy5QpgpM8g4MK6yMbLplZGcRzsA5Avsm4ZLMMxjHQbzog bMViJNn1LRrthYPsZEgfrbmlXVV+nKYXVN1ln51d0MBy7m62DAFaMKRL+rusWGXD/NcT cJ8Sf1LdttqyDylMX9mi6DfhER0gXTrgIaywEEk8ZQ3H2fSqmqfF+vOPHpOolMqL/CDJ Q/Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ltl4RRb5Ij9ywqniuPIEH/A6XjJFdhz13S9UtX+wEX0=; b=j7ZY/TqPwQbK58GpPBNiR/hAfzmf+b9fKoimvnC+LeyHR2LARcPNiUFlpKQFyDGHzI 8mXSp3jZq4ANuBsAtYxYzNJumQ3vcG84r13M3uwAryAhfTaclQsoW3QF9JGNE+En0elB bV1sV0LWOqkrp9AYyEpY6Q4C9IUoTomSDOo9RpKHVT85Z5xhVAm++TjLEZHSKoXQwRR5 6ipsgjOdhtYOFzTX3ZBXjJgO6Ia8G6UP0p8+nhi9r17cab32kIsolKUC8vjqDbuq3Rf/ A2iwC/TmXX9duvPJI+C3pyCQ8LhhcDrOVGHrtYSq1dxHDDrly/COuabLoNfcYtkFK72v kVpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eyquUaPQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m24si8494415ejx.286.2019.10.08.00.19.41; Tue, 08 Oct 2019 00:19:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eyquUaPQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730249AbfJHHTg (ORCPT + 8 others); Tue, 8 Oct 2019 03:19:36 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53614 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729740AbfJHHTg (ORCPT ); Tue, 8 Oct 2019 03:19:36 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x987JRB7046353; Tue, 8 Oct 2019 02:19:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570519167; bh=ltl4RRb5Ij9ywqniuPIEH/A6XjJFdhz13S9UtX+wEX0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eyquUaPQmKleNFjiRqAKKjifiPDxUUIBiq6ogyMA3bj4ilnyc8iNPeaoQ4LMqrOOt PwjAz6G9JuvJbj0AP7/993VWnORuYeVR0WnSK31SZN8QZbga2gO4pEVc/ZlrPl/LQD /UvBcEiv0MMfTZOic+4QSDMuWj9VE7j6FsFd/qc4= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x987JRqc028753; Tue, 8 Oct 2019 02:19:27 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 02:19:25 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 02:19:23 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x987JJj5027770; Tue, 8 Oct 2019 02:19:24 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv7 2/9] soc: ti: add initial PRM driver with reset control support Date: Tue, 8 Oct 2019 10:19:06 +0300 Message-ID: <20191008071913.28740-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008071913.28740-1-t-kristo@ti.com> References: <20191008071913.28740-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial PRM (Power and Reset Management) driver for TI OMAP class SoCs. Initially this driver only supports reset control, but can be extended to support rest of the functionality, like powerdomain control, PRCM irq support etc. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Kconfig | 1 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/omap_prm.c | 259 ++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/soc/ti/omap_prm.c -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fdb6743760a2..ad08d470a2ca 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K + select ARCH_HAS_RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index b3868d392d4f..788b5cd1e180 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o +obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c new file mode 100644 index 000000000000..ab0b66ad715d --- /dev/null +++ b/drivers/soc/ti/omap_prm.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OMAP2+ PRM driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct omap_rst_map { + s8 rst; + s8 st; +}; + +struct omap_prm_data { + u32 base; + const char *name; + u16 rstctrl; + u16 rstst; + const struct omap_rst_map *rstmap; + u8 flags; +}; + +struct omap_prm { + const struct omap_prm_data *data; + void __iomem *base; +}; + +struct omap_reset_data { + struct reset_controller_dev rcdev; + struct omap_prm *prm; + u32 mask; + spinlock_t lock; +}; + +#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) + +#define OMAP_MAX_RESETS 8 +#define OMAP_RESET_MAX_WAIT 10000 + +#define OMAP_PRM_HAS_RSTCTRL BIT(0) +#define OMAP_PRM_HAS_RSTST BIT(1) + +#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) + +static const struct of_device_id omap_prm_id_table[] = { + { }, +}; + +static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) +{ + if (reset->mask & BIT(id)) + return true; + + return false; +} + +static int omap_reset_get_st_bit(struct omap_reset_data *reset, + unsigned long id) +{ + const struct omap_rst_map *map = reset->prm->data->rstmap; + + while (map->rst >= 0) { + if (map->rst == id) + return map->st; + + map++; + } + + return id; +} + +static int omap_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit = omap_reset_get_st_bit(reset, id); + bool has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + /* Check if we have rstst */ + if (!has_rstst) + return -ENOTSUPP; + + /* Check if hw reset line is asserted */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + if (v & BIT(id)) + return 1; + + /* + * Check reset status, high value means reset sequence has been + * completed successfully so we can return 0 here (reset deasserted) + */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v >>= st_bit; + v &= 1; + + return !v; +} + +static int omap_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + unsigned long flags; + + /* assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v |= 1 << id; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int omap_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit; + bool has_rstst; + unsigned long flags; + + has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + if (has_rstst) { + st_bit = omap_reset_get_st_bit(reset, id); + + /* Clear the reset status by writing 1 to the status bit */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v |= 1 << st_bit; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); + } + + /* de-assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v &= ~(1 << id); + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static const struct reset_control_ops omap_reset_ops = { + .assert = omap_reset_assert, + .deassert = omap_reset_deassert, + .status = omap_reset_status, +}; + +static int omap_prm_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + + if (!_is_valid_reset(reset, reset_spec->args[0])) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int omap_prm_reset_init(struct platform_device *pdev, + struct omap_prm *prm) +{ + struct omap_reset_data *reset; + const struct omap_rst_map *map; + + /* + * Check if we have controllable resets. If either rstctrl is non-zero + * or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register + * for the domain. + */ + if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) + return 0; + + map = prm->data->rstmap; + if (!map) + return -EINVAL; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.ops = &omap_reset_ops; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->rcdev.of_xlate = omap_prm_reset_xlate; + reset->rcdev.of_reset_n_cells = 1; + spin_lock_init(&reset->lock); + + reset->prm = prm; + + while (map->rst >= 0) { + reset->mask |= BIT(map->rst); + map++; + } + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + +static int omap_prm_probe(struct platform_device *pdev) +{ + struct resource *res; + const struct omap_prm_data *data; + struct omap_prm *prm; + const struct of_device_id *match; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + match = of_match_device(omap_prm_id_table, &pdev->dev); + if (!match) + return -ENOTSUPP; + + prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL); + if (!prm) + return -ENOMEM; + + data = match->data; + + while (data->base != res->start) { + if (!data->base) + return -EINVAL; + data++; + } + + prm->data = data; + + prm->base = devm_ioremap_resource(&pdev->dev, res); + if (!prm->base) + return -ENOMEM; + + return omap_prm_reset_init(pdev, prm); +} + +static struct platform_driver omap_prm_driver = { + .probe = omap_prm_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = omap_prm_id_table, + }, +}; +builtin_platform_driver(omap_prm_driver); From patchwork Tue Oct 8 07:19:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175458 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5334670ill; Tue, 8 Oct 2019 00:19:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqx9otOXXY4FziiXhS2W8upGzCL2FCnMivQIKrxeJ7o3hC7QdHqsQJOmOwuGmiw04U83V+Es X-Received: by 2002:a05:6402:290:: with SMTP id l16mr32696143edv.178.1570519184051; Tue, 08 Oct 2019 00:19:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570519184; cv=none; d=google.com; s=arc-20160816; b=b72tTmaXy7xm1v/4/hcQQRhZXIa38XCpSGH/0X+1Jju91QXw9z5zuES9/k+1CAaHta ZOByrGe6jLsDwfdZBwH1QGcdgty186iedATAwilijY55b6kUZH+WqKkTvj01yj0UXK5E fz+OheY1fmYB8Kw/o/UUUL4ORx5HvsjR01ousPDwcQ6EnRaOJcG5DGUVEsGLFyFGI/TQ UkRefXRWq7/l/l2N+CPtDAaTDMh3Lrs/K7Ju3gvOGdz+tIfH5jbblFrBDkRG8w4QbJn3 6ie7VZSqPlRmIfkA7h5vkWImTK6Zbw1ndq8g9gQK7xZs2oWxyNkgohuDOgG8+KvuwQTa VvKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hcftpBMP2gQsYIzIi5S84qh2X88Wcx3kW8vrYbRpjDU=; b=P+ikV7BgHFVeUiym8MKI8GL1eCgDmC1yEmfSZgiGhpClBlykHDStRALqWpEXPeYmAN s/W6RZuCSK1VHiQdQjh0UswonREDIBzs+0Rb2LuqI+LA3AjWAKAT323Mskd9gyvVV27J TxpHKnDOUCelGAVaiApAUxQSLt5vtNt+Pe0rpQy9Gk6/pVoWViwuHzcT6x90JmqToRjj pEF3NkIJoZVxNJAKDSa9qGggYoxRAs5nljawopfXnZXqFUHprz9QfwLi9kVn6QSdstMY 5l+MDa8BogYENUogOrjVFdqoCLhJI2m3zgOVwhhHiOyBqpNa9ovYqJju3dKmqJpS+/FB vsPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dBOMjeqa; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m24si8494415ejx.286.2019.10.08.00.19.43; Tue, 08 Oct 2019 00:19:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dBOMjeqa; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730279AbfJHHTj (ORCPT + 8 others); Tue, 8 Oct 2019 03:19:39 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:34682 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730156AbfJHHTj (ORCPT ); Tue, 8 Oct 2019 03:19:39 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x987JWpU025171; Tue, 8 Oct 2019 02:19:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570519172; bh=hcftpBMP2gQsYIzIi5S84qh2X88Wcx3kW8vrYbRpjDU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dBOMjeqamj4F+QqAso0J2mqxOih8dFs1l/MXj0H4ziMt9uyXIBYi5xUkRHC5SqXrs 8XmzuXUdlWpJNtBRHMXcIkLd93RSDcu/MxQP9lSFNRIPiHFqgvXgTCpB3fOLjicxEM DJSvLQvw21iBQMJ1KzqXYpvTICopbxF7FpQB9foc= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x987JWYN073252 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 02:19:32 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 02:19:29 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 02:19:31 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x987JJj8027770; Tue, 8 Oct 2019 02:19:30 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv7 5/9] soc: ti: omap-prm: add omap4 PRM data Date: Tue, 8 Oct 2019 10:19:09 +0300 Message-ID: <20191008071913.28740-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008071913.28740-1-t-kristo@ti.com> References: <20191008071913.28740-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PRM data for omap4 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 3d9393ff67e3..24b1da3492c0 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -58,7 +58,29 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) +static const struct omap_rst_map rst_map_01[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map rst_map_012[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = 2, .st = 2 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data omap4_prm_data[] = { + { .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 }, + { .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { + { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { }, };