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[209.51.188.17]) by mx.google.com with ESMTPS id k8-20020ae9f108000000b00790fb5459fdsi8723632qkg.686.2024.05.06.04.46.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:46:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=Bym6Utbz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3wnY-0002wy-2z; Mon, 06 May 2024 07:46:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmg-00020j-GH for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:31 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wme-00020u-WD for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=EefT7v8rE+Ga47+Z+jrlLQY0Rn8dnOkk3WD8JQbXUh8=; b=Bym6Utbz9yzPXMJYkK/+VPcqYp CefB2UmBuSYuuTdrAsCN40cRj1QcD9ZtJ8EQ1qUmC8YiLz3kQunxcISWFYbMoFQqku9n6F6dT5HIS GmKFiLFlsC93n3Pw4F+fzkKct16jW7aYQg5Y1UcMBPo3NK/s1jpQbN3gJgdk0wtKdM3zlUT2bAh2W OW8J0GF+ZUf3qFG+UUkz1VgBt75POMUNZX1fjeeR/MXqe3SDBhRkmzg9bdSs8iu+nTB9/zcsO+tqT Lrv3Y4lQjdqACS4veEuoEQOJ/2FDojPrsHEOnTrkO83SOx4vC7zCxYjLaEryNK12y96Yb+8hMHGuD KGFdB45Oiq46B/yvxYpm4yA/qYmZV2myqmvCXkNtphxuA6oHuJj7o2lL5SJrmVA21LnqlDBVcY2U6 iPfD5U7GwyPcz0OizTfEqXgJ7OLK+PShx8Xak6pUUHuCJtUT4rd4qS04rKhdj1Br7ciQaKwswVg1v ghc/svQg8EWBMxzs4Loy6hvcvtKpofbh12FenhonsqERaTzaUIyIA4qmqh3ixztYHx/eZk5arM4SF ifngjUIDcVJF7c4MBrXy/N6tcSQYcihPdh/w0U9yxpkBN5t0Uud0OAwbOoxUxu9YvR5VgB4n+0cxF I/Qer9+HDRDVjVRRF36oFAVtACOi8Yqmul1MPIAXU=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wlW-0005pA-LF; Mon, 06 May 2024 12:44:22 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:45 +0100 Message-Id: <20240506114451.331311-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 06/12] linux-user/sparc: Add more hwcap bits for sparc64 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Supply HWCAP_SPARC_V8PLUS, HWCAP_SPARC_MUL32, HWCAP_SPARC_DIV32, HWCAP_SPARC_POPC, HWCAP_SPARC_FSMULD, HWCAP_SPARC_VIS, HWCAP_SPARC_VIS2. Signed-off-by: Richard Henderson Message-Id: <20240502165528.244004-2-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- linux-user/elfload.c | 48 +++++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f9461d2844..14f08b64a1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -968,24 +968,44 @@ const char *elf_hwcap2_str(uint32_t bit) #endif /* TARGET_ARM */ #ifdef TARGET_SPARC -#ifdef TARGET_SPARC64 -#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \ - | HWCAP_SPARC_MULDIV | HWCAP_SPARC_V9) -#ifndef TARGET_ABI32 -#define elf_check_arch(x) ( (x) == EM_SPARCV9 || (x) == EM_SPARC32PLUS ) +#ifndef TARGET_SPARC64 +# define ELF_CLASS ELFCLASS32 +# define ELF_ARCH EM_SPARC +#elif defined(TARGET_ABI32) +# define ELF_CLASS ELFCLASS32 +# define elf_check_arch(x) ((x) == EM_SPARC32PLUS || (x) == EM_SPARC) #else -#define elf_check_arch(x) ( (x) == EM_SPARC32PLUS || (x) == EM_SPARC ) +# define ELF_CLASS ELFCLASS64 +# define ELF_ARCH EM_SPARCV9 #endif -#define ELF_CLASS ELFCLASS64 -#define ELF_ARCH EM_SPARCV9 -#else -#define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \ - | HWCAP_SPARC_MULDIV) -#define ELF_CLASS ELFCLASS32 -#define ELF_ARCH EM_SPARC -#endif /* TARGET_SPARC64 */ +#include "elf.h" + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + /* There are not many sparc32 hwcap bits -- we have all of them. */ + uint32_t r = HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | + HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV; + +#ifdef TARGET_SPARC64 + CPUSPARCState *env = cpu_env(thread_cpu); + uint32_t features = env->def.features; + + r |= HWCAP_SPARC_V9 | HWCAP_SPARC_V8PLUS; + /* 32x32 multiply and divide are efficient. */ + r |= HWCAP_SPARC_MUL32 | HWCAP_SPARC_DIV32; + /* We don't have an internal feature bit for this. */ + r |= HWCAP_SPARC_POPC; + r |= features & CPU_FEATURE_FSMULD ? HWCAP_SPARC_FSMULD : 0; + r |= features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0; + r |= features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0; +#endif + + return r; +} static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) From patchwork Mon May 6 11:44:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794986 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880076wra; Mon, 6 May 2024 04:47:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVlQD5g1nG5+szOLT5dx8acx0KEjfajuNmPeyz+zh1ge6pLOPloBLpoIY1KYhrZ0CoYzOwG9DoBOLIegx75D7/v X-Google-Smtp-Source: AGHT+IFlk5EOXW8s9S2663ZuclxiSHTqsHmWJFwJT/+qpalVe5/tdpJZbfJdlh8hpuqecsCUNaYA X-Received: by 2002:a05:620a:2551:b0:792:96e9:6a7e with SMTP id s17-20020a05620a255100b0079296e96a7emr3589101qko.4.1714996053571; Mon, 06 May 2024 04:47:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714996053; cv=none; d=google.com; s=arc-20160816; b=xca/HF2FTg4W7RghASRfniyLr1p//+n97dR8/Mrm9JVdAcSCmRUZ0f3HEzT/dKCjFd zzWtpFAGMMHmBJINdIa6jzma03StAg6UezW0KwXcpc2u7dA3UqWKRYrH6DX62Zh6KRHX FFBqk9TpsitaMBgHxnWl/Id/jUtHeXAv2/Ke1t7nOY0bZhb/m0Hf5hB4M1LScrcEmPqI s9RkKtWPCM9lx+LtH1PjUMuZjyk8kPxKOzdbUeRFhPwhdWMdZraXzWWpC/3/PP/vu5fy p9n1H14W2ISEJHldUG7F4dWZMrM99mtWGP21ipkBHM3Rsu44vJ0eFq5UZyVW902I5NR8 D0MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sMhmJO5kyFUJkf58pFSFv2atNJSSrYfDJkwhEX27jSY=; fh=n+s/UmlNdAcpkwZHkfPfDfNjQ/P7HHEaFIgb3Ls+s2Y=; b=DGqhqmb+AHfrQzOpHBNUAr0GSdrEkdcQd4ulB8T0thEcPlvVZqN6+BW1zTqJxi4Vl2 fhKaQtcEIoFl381UnH93rssOBPo0AJRtaBM+54RIhQyl3pW9HUFoVRI0EJoxyqw8TBMR OszYI5UsNkwrVoLkeMk13Lj1IIY49g2fkzZbf3oNx/fH+0w+j5rp9ZcIgdR7NBaZdbde 4BZERAL25mLmz2Cg8ZOQ04WjIgcpa1oyvlPLa/p8/iRzQBcu8q7ALhSYBuVDqs4xWU/2 2g2R6JOF3LbyAu4vyPXgXCyhPRbgZp+bGcx5ywajVS2EBBGw88dektdKMPID+0CSosym vsyA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=nW9k4wvk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q3-20020a05620a024300b00792932d6775si3269643qkn.23.2024.05.06.04.47.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:47:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=nW9k4wvk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3wnd-0002yg-Bt; Mon, 06 May 2024 07:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wml-00028t-3x for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:38 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmj-00023M-9k for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=sMhmJO5kyFUJkf58pFSFv2atNJSSrYfDJkwhEX27jSY=; b=nW9k4wvkivfJUu5+V32rAczZ2P +/7EPKtAjkjUEqwTb8jGnYySbJixBhVcgfC0/CNZ2g5IOnqlvi+9JzKi0R+W1lepkZ+GfAJFX0iHR nJU8Pbohj1egCRD/dipFSCZAr2a7a3t45HL7zEPCr1Mj+gPFh6XLRPoVNGLBIDPbUJsGmbMdMrM4w 4xzC1oolOERiknKqs/QiLwszDl0IOpJ4MQaLXMZaaNtwFYXNWi4Lnd8zFT2mbpY7BYsjS8zHLdQFd XkS5eSROOIpgcSoxP6yFCXdxDL4Ycx2UHWBDg89Rt73c8orLUMbOa5Jh3NQFdQB1UYvNqbKWKAtqC rWzaymlHYQpnfLjPKBWrT2SoV23PtU0eo2C2hPOYRtI4MSgQhVR2pdFPTAsbcP6XVNibQHuo/0/ug XyzySncr2LC/9A1HTrCLJLn9J5Nu9sjPpzl0N70EEathfs9iW4tuKWWQJkhLNwTe6i/mjruLrgEZR pUmMWviqZSfQODqwMdosgbtm7Pv883MRFQoUqNAI0NeUVpWNYj/aMGU67TM6agjlBCSM+p+r5gUXJ qnrkEM6G3LHVzwkNpGN1zlgMCO+VSVmU45sSiVnMpHJ5Z6sLZ4Yp520G7BY4LpwyqKk1UcBOcMi8+ 90Iqz5sUcibgUBk89jDB2lB1QZHqMzGvsF7XuitRw=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wla-0005pA-OL; Mon, 06 May 2024 12:44:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:46 +0100 Message-Id: <20240506114451.331311-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 07/12] target/sparc: Fix FEXPAND X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This is a 2-operand instruction, not 3-operand. Worse, we took the source from the wrong operand. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240502165528.244004-3-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/insns.decode | 2 +- target/sparc/translate.c | 20 +++++++++++++++++++- target/sparc/vis_helper.c | 6 +++--- 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b8087d0d2b..57ab755ffd 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -102,7 +102,7 @@ DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_1(fexpand, TCG_CALL_NO_RWG_SE, i64, i32) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2d26404cb2..e2d8a07dc4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -352,7 +352,7 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r - FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r + FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @r_r2 FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 571b3e3f03..dfcfe855a1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4358,6 +4358,25 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) +static bool do_df(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_i32)) +{ + TCGv_i64 dst; + TCGv_i32 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = tcg_temp_new_i64(); + src = gen_load_fpr_F(dc, a->rs); + func(dst, src); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FEXPAND, VIS1, do_df, a, gen_helper_fexpand) + static bool do_env_df(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) { @@ -4589,7 +4608,6 @@ TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16) TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) -TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand) TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 7763b16c24..db2e6dd6c1 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -260,13 +260,13 @@ uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fexpand(uint64_t src1, uint64_t src2) +uint64_t helper_fexpand(uint32_t src2) { VIS32 s; VIS64 d; - s.l = (uint32_t)src1; - d.ll = src2; + s.l = src2; + d.ll = 0; d.VIS_W64(0) = s.VIS_B32(0) << 4; d.VIS_W64(1) = s.VIS_B32(1) << 4; d.VIS_W64(2) = s.VIS_B32(2) << 4; From patchwork Mon May 6 11:44:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794987 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880080wra; Mon, 6 May 2024 04:47:36 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVrrddJIsZ7fnSE79d9+rGOOd13TAdocttzyU8VetHyuHtsCSb3nlopC5zGmlTFlZKROIqoc3pu/UgSLDu5DCuN X-Google-Smtp-Source: AGHT+IGaNVuia0WgIWBs/UEVT7nNIpsnGQse33aGLAehQoJQw0rPF2tX75yOPbhdMgXfKvZjYscx X-Received: by 2002:a9d:3e46:0:b0:6f0:2dd3:1d02 with SMTP id h6-20020a9d3e46000000b006f02dd31d02mr5375995otg.20.1714996056269; Mon, 06 May 2024 04:47:36 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id wi11-20020a05620a570b00b00790c8b4b8a8si8567522qkn.119.2024.05.06.04.47.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:47:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=1iwXMLli; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3woT-0003eq-SV; Mon, 06 May 2024 07:47:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wms-0002Hv-6M for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:44 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmn-00024u-8v for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=Y5M4mmYouEfYYTQYVwtEst5GlagcgUaUVsX9+atwWag=; b=1iwXMLliFz1iZ7jZX7STosT1/h H8rWdYsYmUaBxDyuR+i5VTzQMzG9A+HalnfRiUZrFd1ftcb9doeb1Vg0l5ddAA/5LSFbBpep6SFgD UOZB7Hm2Qwn2Ht8oeCTnV5SR22wApFRqXfOsK4blCsFFYQYWDh2TBNt7KTt9YzUur1lCdAEFzT8YL P0Sdzq0WtltPorQFRMjjdgkabpm2O8mGQDezoDzZosM6OZxF9+L3iBvUHrtPdOr2j8uAunaRFSN3J ornR2Z0qcp5/RtwPgxb4MNfb7yoOco1jWyc5U22tL58XIAMnVQvnQd6LcXNgTK0W8zHV9/fnaaDPw WufwGBGBY221Dq+siYxVuh+LNJJ+HJSQXknBSIVEqeSkTURfpkoPWldGP07pcm2TOHBPH9LeUA9Vj vJYMYUfvBONt+zzkpaSS0uZlv7IotuphSG6n3TruhjZUoV2qiHUfqGfPJ4AWo6N4YsWtdJaM66xAJ 0SR6XiwWde3mmJTjfR96M8OIWasufILf9uEnXotANwJDK41lsG1LBWzai+B7kjb8JsEDsSVeYSkY1 WxBVSrZcUf71f8FgJOuChkBN4fuMW8PUniJs1qLJ9O4bLzRIjL3J4LZvgrexL8d1oacT+lg2jMIRl mjVjauCcdWuK+nkg4beOp7XHhmKGE1y7OJMOOFWqw=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wle-0005pA-RQ; Mon, 06 May 2024 12:44:30 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:47 +0100 Message-Id: <20240506114451.331311-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 08/12] target/sparc: Fix FMUL8x16 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This instruction has f32 as source1, which alters the decoding of the register number, which means we've been passing the wrong data for odd register numbers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 21 ++++++++++++++++++++- target/sparc/vis_helper.c | 9 +++++---- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 57ab755ffd..27dc604cac 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -95,7 +95,7 @@ DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64) DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dfcfe855a1..c4adc148d2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4583,6 +4583,26 @@ TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) +static bool do_dfd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) +{ + TCGv_i64 dst, src2; + TCGv_i32 src1; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4600,7 +4620,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, return advance_pc(dc); } -TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16) TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au) TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al) TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index db2e6dd6c1..7728ffe9c6 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -94,16 +94,17 @@ uint64_t helper_fpmerge(uint64_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) { - VIS64 s, d; + VIS64 d; + VIS32 s; uint32_t tmp; - s.ll = src1; + s.l = src1; d.ll = src2; #define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ + tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \ if ((tmp & 0xff) > 0x7f) { \ tmp += 0x100; \ } \ From patchwork Mon May 6 11:44:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794988 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880118wra; Mon, 6 May 2024 04:47:42 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUTIz2DkMMvALm9OXuakH5tdTa6qo9PxJUrMqb2aj6SyjvMUEpqgMiQGe5QovMo82SHp2G/nxJB3+fGaVBhMmtB X-Google-Smtp-Source: AGHT+IGx5sK6fBhfeo5wWA9iQX8O1ohg4iah72ERRJJuyfJiUOEGRTj8+QbCB3HYiarJP5WCnaX0 X-Received: by 2002:a05:6830:71a5:b0:6f0:29cc:c545 with SMTP id el37-20020a05683071a500b006f029ccc545mr7024057otb.38.1714996062040; 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[209.51.188.17]) by mx.google.com with ESMTPS id br18-20020a05620a461200b007905dea846asi10201981qkb.452.2024.05.06.04.47.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:47:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=xxNFWUKa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3woe-0004Rr-Jc; Mon, 06 May 2024 07:47:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wnD-0002bH-JW for qemu-devel@nongnu.org; Mon, 06 May 2024 07:46:05 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmr-00025S-FA for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=WavmyVT0W+fmmIs670leuexf31sAnaVVyxTdQUL0QZU=; b=xxNFWUKaGq5YMCRqybi5uHCo+B SpOhZTRK7FCaN0CXjKCn8rfdVGkJR4ukMSC0hZka5DTzwVVNGCRWLvFflXjclfeBTsiGfvD2+Gqei E372VDStxz2gCF5daUhZ3Rx+QjdK/n4pm5nynbaZI1vTfbQSs2BQ2dwwkTwfW0mFZ9XtoaN3GKp1F JW4/Pcy2+4EJDYMeaAZxtB9d0Szpaa+OZ7Lf4LKw4rxKzAfS0DOf22tK1GQFmyZb1DGkSVBe48BMN wXIJDoiX4Y+OJ9l9x2kLbsD9/BlNOx7dZf+UJ/998PdZSKTPSErlKXVkacTGzYy9EAwDgbvjUyanH FNtzh1pMbV31OsmoKPS8iLn/pE2dpSY7k41Re1Q5z8yDiqp4r4M+ZIhvxrlNCoY/EtwTIOij0VUJc Ro3ID/+QqHFknquOeSOpK2ZSCrlDwF0KMcaGweVd/hQV75diwlnw4qHzsUalY0TCdR9RMbM1KCVf4 PxMyAdkbNHbsJhrQlWr4+3UPsuWwfYjbriEIb/E5KD66bPuAUBAeRvg/TfX1PNAB1ax7vEary1ZYU X9HgekWKQlvf6ctzoMTBQBbi5HFZmz/rhUAQMM52H6HVbJ5TF2iHb8Uzxrq175/XgaqvSkfkljkVm v78Ba0e5WYZg24ObYTTCswgpuLBb+tGlfUBcsNdyE=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wli-0005pA-UL; Mon, 06 May 2024 12:44:35 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:48 +0100 Message-Id: <20240506114451.331311-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 09/12] target/sparc: Fix FMUL8x16A{U,L} X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson These instructions have f32 inputs, which changes the decode of the register numbers. While we're fixing things, use a common helper for both insns, extracting the 16-bit scalar in tcg beforehand. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240502165528.244004-5-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/helper.h | 3 +-- target/sparc/translate.c | 38 +++++++++++++++++++++++++++---- target/sparc/vis_helper.c | 47 +++++++++++---------------------------- 3 files changed, 48 insertions(+), 40 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 27dc604cac..9cde2b69a5 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -96,8 +96,7 @@ DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) -DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16a, TCG_CALL_NO_RWG_SE, i64, i32, s32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c4adc148d2..a8ada6934a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -45,6 +45,7 @@ # define gen_helper_clear_softint(E, S) qemu_build_not_reached() # define gen_helper_done(E) qemu_build_not_reached() # define gen_helper_flushw(E) qemu_build_not_reached() +# define gen_helper_fmul8x16a(D, S1, S2) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_restored(E) qemu_build_not_reached() @@ -72,8 +73,6 @@ # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL; }) -# define gen_helper_fmul8x16al ({ qemu_build_not_reached(); NULL; }) -# define gen_helper_fmul8x16au ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; }) @@ -719,6 +718,18 @@ static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) #endif } +static void gen_op_fmul8x16al(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) +{ + tcg_gen_ext16s_i32(src2, src2); + gen_helper_fmul8x16a(dst, src1, src2); +} + +static void gen_op_fmul8x16au(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) +{ + tcg_gen_sari_i32(src2, src2, 16); + gen_helper_fmul8x16a(dst, src1, src2); +} + static void finishing_insn(DisasContext *dc) { /* @@ -4583,6 +4594,27 @@ TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) +static bool do_dff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i32, TCGv_i32)) +{ + TCGv_i64 dst; + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + func(dst, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au) +TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al) + static bool do_dfd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) { @@ -4620,8 +4652,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, return advance_pc(dc); } -TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au) -TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al) TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 7728ffe9c6..ff2f43c23f 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -119,44 +119,23 @@ uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fmul8x16al(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16a(uint32_t src1, int32_t src2) { - VIS64 s, d; - uint32_t tmp; - - s.ll = src1; - d.ll = src2; - -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; - - PMUL(0); - PMUL(1); - PMUL(2); - PMUL(3); -#undef PMUL - - return d.ll; -} - -uint64_t helper_fmul8x16au(uint64_t src1, uint64_t src2) -{ - VIS64 s, d; + VIS32 s; + VIS64 d; uint32_t tmp; - s.ll = src1; - d.ll = src2; + s.l = src1; + d.ll = 0; -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; +#define PMUL(r) \ + do { \ + tmp = src2 * (int32_t)s.VIS_B32(r); \ + if ((tmp & 0xff) > 0x7f) { \ + tmp += 0x100; \ + } \ + d.VIS_W64(r) = tmp >> 8; \ + } while (0) PMUL(0); PMUL(1); From patchwork Mon May 6 11:44:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794989 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880578wra; 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[209.51.188.17]) by mx.google.com with ESMTPS id j22-20020ac85f96000000b0043ab24a0b17si6869837qta.295.2024.05.06.04.49.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:49:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=AJJfiv62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3wok-0004fG-F7; Mon, 06 May 2024 07:47:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wnD-0002bI-IU for qemu-devel@nongnu.org; Mon, 06 May 2024 07:46:05 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmr-00025W-SR for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=NVY+DInK6e9c7Rfod3udmjYDPm6WHRlbkoobfpkday0=; b=AJJfiv620T+8S/6UmLQL8dX5L3 LWIi3XFQaE4CVpHBRpTH4KWo8uE0cTa9Qt8S8za5yfdxdEYC9eWFpAzxHd2Hi79p6t72oug3fjr9w b4vLuNe5VX+vwd9fghk48jYaBWIcCPGkOnF+/pLD2u5ld55k6Q/Ow5U8GkEKpMLLcpPviST+4vGrR pu0I2grH/QJlpEUgiwqyqTliIKMjunORuDWGOZjaQIxhLjU1/3zfyxpaeZ/wGWs0PmvOrg8hp51x6 I+IHBVz8sutSHdGGjxBWqn0aZ9HA77DgiZsdQHnuoLZFA5ah7uZzM9YhiuU8v2KG/tiPgbEDJrNw7 Lpint4/dCE6miLddt/1IRzgW6Lo4ev/vGAK6Tc01/JjJ340n6cVCQj692mT0DnxSI2hDVXXvl0CSh V6j9xacGJBH09a5vOBEKuryIfB1KPMyn0pWQlDh5ziah5rPgCPF3SxV8Y8AxXMgHYL5HD/v+SlO7f U/3lyqSjZhbMREwikicg9Y418H5+TbKMzlQpYM8EwKIIxDuHlChEas3wmUEvR/M3W1MR8ygwHL4wr puS7K6P2iMt4DKEb9XTq8RsLirnkZ2wThaz1bMh2MTnAJ4M4Xs8C4Ism78SnWHwdvFYQ7KjJNVA/6 eb4enEojEkL6f7GgZ7yQ0eabYP1olFuF6jFWohEn8=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wln-0005pA-4f; Mon, 06 May 2024 12:44:35 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:49 +0100 Message-Id: <20240506114451.331311-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 10/12] target/sparc: Fix FMULD8*X16 X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Not only do these instructions have f32 inputs, they also do not perform rounding. Since these are relatively simple, implement them properly inline. Signed-off-by: Richard Henderson Message-Id: <20240502165528.244004-6-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 -- target/sparc/translate.c | 48 +++++++++++++++++++++++++++++++++++---- target/sparc/vis_helper.c | 46 ------------------------------------- 3 files changed, 44 insertions(+), 52 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 9cde2b69a5..fcb9c617b7 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -99,8 +99,6 @@ DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16a, TCG_CALL_NO_RWG_SE, i64, i32, s32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_1(fexpand, TCG_CALL_NO_RWG_SE, i64, i32) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a8ada6934a..8a2894bb9f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -74,8 +74,6 @@ # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; }) -# define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; }) -# define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL; }) @@ -730,6 +728,48 @@ static void gen_op_fmul8x16au(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) gen_helper_fmul8x16a(dst, src1, src2); } +static void gen_op_fmuld8ulx16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + tcg_gen_ext8u_i32(t0, src1); + tcg_gen_ext16s_i32(t1, src2); + tcg_gen_mul_i32(t0, t0, t1); + + tcg_gen_extract_i32(t1, src1, 16, 8); + tcg_gen_sextract_i32(t2, src2, 16, 16); + tcg_gen_mul_i32(t1, t1, t2); + + tcg_gen_concat_i32_i64(dst, t0, t1); +} + +static void gen_op_fmuld8sux16(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + /* + * The insn description talks about extracting the upper 8 bits + * of the signed 16-bit input rs1, performing the multiply, then + * shifting left by 8 bits. Instead, zap the lower 8 bits of + * the rs1 input, which avoids the need for two shifts. + */ + tcg_gen_ext16s_i32(t0, src1); + tcg_gen_andi_i32(t0, t0, ~0xff); + tcg_gen_ext16s_i32(t1, src2); + tcg_gen_mul_i32(t0, t0, t1); + + tcg_gen_sextract_i32(t1, src1, 16, 16); + tcg_gen_andi_i32(t1, t1, ~0xff); + tcg_gen_sextract_i32(t2, src2, 16, 16); + tcg_gen_mul_i32(t1, t1, t2); + + tcg_gen_concat_i32_i64(dst, t0, t1); +} + static void finishing_insn(DisasContext *dc) { /* @@ -4614,6 +4654,8 @@ static bool do_dff(DisasContext *dc, arg_r_r_r *a, TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au) TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al) +TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16) +TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16) static bool do_dfd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) @@ -4654,8 +4696,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) -TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) -TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16) TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index ff2f43c23f..61c61c7fea 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -194,52 +194,6 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2) return d.ll; } -uint64_t helper_fmuld8sux16(uint64_t src1, uint64_t src2) -{ - VIS64 s, d; - uint32_t tmp; - - s.ll = src1; - d.ll = src2; - -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_L64(r) = tmp; - - /* Reverse calculation order to handle overlap */ - PMUL(1); - PMUL(0); -#undef PMUL - - return d.ll; -} - -uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2) -{ - VIS64 s, d; - uint32_t tmp; - - s.ll = src1; - d.ll = src2; - -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_L64(r) = tmp; - - /* Reverse calculation order to handle overlap */ - PMUL(1); - PMUL(0); -#undef PMUL - - return d.ll; -} - uint64_t helper_fexpand(uint32_t src2) { VIS32 s; From patchwork Mon May 6 11:44:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794990 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880672wra; Mon, 6 May 2024 04:49:23 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXJMkzniHdk75SvX0NH8xGbphJTPR3Ng6VKzxe2GSDphomQHUMFOii4vPBnfzdNrrQQav2015Rahj1ioCTzImfZ X-Google-Smtp-Source: AGHT+IGxsKD+awqBtst24PIgXypYhmZojpriGN7ezCDuuI96a3j2i4CdL90OaQHTE22iEdklQ/Fc X-Received: by 2002:ac8:7c54:0:b0:43b:8bd:6a7a with SMTP id o20-20020ac87c54000000b0043b08bd6a7amr10839335qtv.2.1714996162954; Mon, 06 May 2024 04:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714996162; cv=none; d=google.com; s=arc-20160816; b=DH7wnRB8VY3Yr1ZB4fXwAEXOp6ogoEv2x96rjzT/f//R7fv735aEGLS3t0Bix+N0Mx 2rv+4gZ608/KjU1n58X69+8WDMxH+1IO+yAdJKTlKq8EkaK+R3Gy4gCIB6+H6ptX7F3H FyiMNumXjBzyLvoIKo2OloM2Mh1QQANH+X1vmiOXM60mcsngo091riGxPWBL6fEbmd5C kPfeTAexYNS6dhCcS06uI4puGWGUb7KRIrONLknpgVlXIYbqNUluC8jw36vqVNPF5n3Q /4PIqGBEU9QFcAbu3WsGuebohkSWYmnqDa44de66463nLTuLTZpTtkS733TBAUZqPwFG kJhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+nWXIBRD4JwFRlPQUPhOrXxE5sdDw1a50waOf4VxWsU=; fh=n+s/UmlNdAcpkwZHkfPfDfNjQ/P7HHEaFIgb3Ls+s2Y=; b=rZFnsm+IWt1vkwOjNa46ZZQ5VqC6+VeZ2L8kktzYTOaYV9hNOCDlg+MvcxSqTMPfyL OsecwdGRnvjr4DmSzoYukKv2x3kmsGQUaNg3tUQgL0ltKg0T6lutx5p6MeKI6r8sQ8+g zB3HU5tyj+d8sGWni1k0/TfQ1EneI3HNykGR/A+0N3CoRsNbiffoXFZv8jbwQnZSwCqE 8ygbm7j/5hzVuKF87fnGp+AYX6/WkSyoAXFy9oVhWgptfBu2yHi73Rm1sY5vlXKeIS7e 4OQHAPjvLNVNXVVYoZb+wgO+IOcFm1i4peKtCY9ELgeJw+28YMIJDJf4QUEOmLtHMe4o nvXA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b="g/WoWmHS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d21-20020ac85ad5000000b0043ae8436d82si9579867qtd.333.2024.05.06.04.49.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:49:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b="g/WoWmHS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3wov-00057w-AW; Mon, 06 May 2024 07:47:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wnD-0002bJ-J8 for qemu-devel@nongnu.org; Mon, 06 May 2024 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wmw-00026A-57 for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=+nWXIBRD4JwFRlPQUPhOrXxE5sdDw1a50waOf4VxWsU=; b=g/WoWmHSHwrT15PtlpLQHgXNfk N7oWyHjeAvTGjV+vLX2JMPs22ZbiI9Cvra0d4nHYGsbFd6uGIA0WS0WfA4oDlYKMADgaoG8FAev2f 9L0peKwqDHh259QItx543UWjdSUBOwjdMHMFs0S7a+ipst8SHuV44oKkwPN0cZdEhMJH700MmdrUj fm6I1hr/YeMg9juejLRlHa3wQm3W9TLlLla8mmTjEtOkfI5uPmTSBLlL6irhSm2Yk2OHlI9HJRorH OPbCkZRAoPsneCKpTC+arQmhXoMwX9PwqD5/QWP8z8oYZyXc6JH6RtN5Z2HhJss+qeubx3b6uCo3+ h46esu6Q5OjSIrtBAvlJPsdyWlcOrpisVIX6yD0H6VN9L3ZF9I/zO0uByFGytq/808l1QlJWZaOgw Xm9J08eh9PQlO/Bjgl8yz7StsSTRwFnyYKUjzrL6k/BVZpE0xmCSBVZE3BPItNk6ahHRjiPxJPN3Y 2moUbqVDk7AzLMbykNX+H+32mwPZBBTalnYK1DnBjdzzQOiFOKTrLHzR7Vo/sdBKiAkeKpu+Dov7a MAEl3WEq0NDCw5ms6oxsI6epLEU4nvHCzBNWEerIRPBsgDnFfYb/vJwpOBSOmVlu5O3S7ilxqhcZM lwxOkXfFd2Px981cojTYJOe04+51hMUScgA7b+CpM=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wln-0005pA-LB; Mon, 06 May 2024 12:44:39 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:50 +0100 Message-Id: <20240506114451.331311-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 11/12] target/sparc: Fix FPMERGE X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This instruction has f32 inputs, which changes the decode of the register numbers. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240502165528.244004-7-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 2 +- target/sparc/vis_helper.c | 27 ++++++++++++++------------- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index fcb9c617b7..97fbf6f66c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -94,7 +94,7 @@ DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_WG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_WG, s64, env, f64) DEF_HELPER_FLAGS_2(fqtox, TCG_CALL_NO_WG, s64, env, i128) -DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16a, TCG_CALL_NO_RWG_SE, i64, i32, s32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8a2894bb9f..99c6f3cc72 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4656,6 +4656,7 @@ TRANS(FMUL8x16AU, VIS1, do_dff, a, gen_op_fmul8x16au) TRANS(FMUL8x16AL, VIS1, do_dff, a, gen_op_fmul8x16al) TRANS(FMULD8SUx16, VIS1, do_dff, a, gen_op_fmuld8sux16) TRANS(FMULD8ULx16, VIS1, do_dff, a, gen_op_fmuld8ulx16) +TRANS(FPMERGE, VIS1, do_dff, a, gen_helper_fpmerge) static bool do_dfd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i32, TCGv_i64)) @@ -4696,7 +4697,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) -TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 61c61c7fea..14c665cad6 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -74,22 +74,23 @@ typedef union { float32 f; } VIS32; -uint64_t helper_fpmerge(uint64_t src1, uint64_t src2) +uint64_t helper_fpmerge(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; - s.ll = src1; - d.ll = src2; + s1.l = src1; + s2.l = src2; + d.ll = 0; - /* Reverse calculation order to handle overlap */ - d.VIS_B64(7) = s.VIS_B64(3); - d.VIS_B64(6) = d.VIS_B64(3); - d.VIS_B64(5) = s.VIS_B64(2); - d.VIS_B64(4) = d.VIS_B64(2); - d.VIS_B64(3) = s.VIS_B64(1); - d.VIS_B64(2) = d.VIS_B64(1); - d.VIS_B64(1) = s.VIS_B64(0); - /* d.VIS_B64(0) = d.VIS_B64(0); */ + d.VIS_B64(7) = s1.VIS_B32(3); + d.VIS_B64(6) = s2.VIS_B32(3); + d.VIS_B64(5) = s1.VIS_B32(2); + d.VIS_B64(4) = s2.VIS_B32(2); + d.VIS_B64(3) = s1.VIS_B32(1); + d.VIS_B64(2) = s2.VIS_B32(1); + d.VIS_B64(1) = s1.VIS_B32(0); + d.VIS_B64(0) = s2.VIS_B32(0); return d.ll; } From patchwork Mon May 6 11:44:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 794991 Delivered-To: patch@linaro.org Received: by 2002:adf:a453:0:b0:34e:ceec:bfcd with SMTP id e19csp880794wra; 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[209.51.188.17]) by mx.google.com with ESMTPS id w18-20020ac857d2000000b004375a94cea3si9331993qta.91.2024.05.06.04.49.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 May 2024 04:49:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=xgVmHfct; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s3wox-0005R3-TK; Mon, 06 May 2024 07:47:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wnD-0002bM-JY for qemu-devel@nongnu.org; Mon, 06 May 2024 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s3wn0-00026a-0c for qemu-devel@nongnu.org; Mon, 06 May 2024 07:45:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=DIhcn+chzbw/OhcdHLU14KIEmrpThVyUGELVh9DW21U=; b=xgVmHfctoPamA2KpnDbvPlGJbq iL0Bt4C0B2utOXCb6qXvZUq98Ka+POgvMVMNCqvAMBmSP4ajij56wMPG7+4Lhf0PvDimi27vvptJ1 IjSbwXK+kBAW+N4wTBwPOfcM+iFSM9sqVE+dyJpqCkuQpPEOTp5afMk9nq48WUZe/evI01bvggO58 4UgkfIT5uPahFqkYxtr2l47vRiE2cR1rD+e9/qFRUAnC8HXgooEDe1xUbYZlntwv5UPAQUKNjYWI9 bV7jsQHJ+ZaOcG+whUst+ff2c6FBo+Bw724HiCz7K++bZY/QgWwHILNG08O8K5weY7hPIAADaXlGI GXm/cvNytSFZgfb9vI8r6GYYT+gyI87SZSFMrthmECWyYZouijWOFOcYhvlQaor0SkLbw9LUUio/R uNIAov6wzBVvzvYanATweFfltpjVfH0IfEZI9eJjjoBhcmFgaLgtQ75zJOWLjTKBG7CE6xWnYxYvm CIGnBC/4c5nQniCHZRpz8uOqcqLBaU4PJj0dtqqfxo8ktBmSFu9T+6qWsUZMinTwK2ihIMLwhnz2q EE/OjPim0qQgtptFmRkRbmyHtlat2/m6qDbibkCLjKjUdOUVR5vZYUlB976JWmqVl+qGBC76HolkS eF4eqISfdpHlSEZ5r4msGu7EpGrxmK4qz/8hfwzhM=; Received: from [2a00:23c4:8bb4:4000:b60d:a162:d698:c802] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1s3wlr-0005pA-Nr; Mon, 06 May 2024 12:44:43 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, richard.henderson@linaro.org Date: Mon, 6 May 2024 12:44:51 +0100 Message-Id: <20240506114451.331311-13-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> References: <20240506114451.331311-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:b60d:a162:d698:c802 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 12/12] target/sparc: Split out do_ms16b X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson The unit operation for fmul8x16 and friends is described in the manual as "MS16b". Split that out for clarity. Improve rounding with an unconditional addition of 0.5 as a fixed-point integer. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240502165528.244004-8-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/vis_helper.c | 78 ++++++++++++--------------------------- 1 file changed, 24 insertions(+), 54 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 14c665cad6..e15c6bb34e 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -44,6 +44,7 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) #if HOST_BIG_ENDIAN #define VIS_B64(n) b[7 - (n)] +#define VIS_SB64(n) sb[7 - (n)] #define VIS_W64(n) w[3 - (n)] #define VIS_SW64(n) sw[3 - (n)] #define VIS_L64(n) l[1 - (n)] @@ -51,6 +52,7 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) #define VIS_W32(n) w[1 - (n)] #else #define VIS_B64(n) b[n] +#define VIS_SB64(n) sb[n] #define VIS_W64(n) w[n] #define VIS_SW64(n) sw[n] #define VIS_L64(n) l[n] @@ -60,6 +62,7 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) typedef union { uint8_t b[8]; + int8_t sb[8]; uint16_t w[4]; int16_t sw[4]; uint32_t l[2]; @@ -95,27 +98,23 @@ uint64_t helper_fpmerge(uint32_t src1, uint32_t src2) return d.ll; } +static inline int do_ms16b(int x, int y) +{ + return ((x * y) + 0x80) >> 8; +} + uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) { VIS64 d; VIS32 s; - uint32_t tmp; s.l = src1; d.ll = src2; -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; - - PMUL(0); - PMUL(1); - PMUL(2); - PMUL(3); -#undef PMUL + d.VIS_W64(0) = do_ms16b(s.VIS_B32(0), d.VIS_SW64(0)); + d.VIS_W64(1) = do_ms16b(s.VIS_B32(1), d.VIS_SW64(1)); + d.VIS_W64(2) = do_ms16b(s.VIS_B32(2), d.VIS_SW64(2)); + d.VIS_W64(3) = do_ms16b(s.VIS_B32(3), d.VIS_SW64(3)); return d.ll; } @@ -124,25 +123,14 @@ uint64_t helper_fmul8x16a(uint32_t src1, int32_t src2) { VIS32 s; VIS64 d; - uint32_t tmp; s.l = src1; d.ll = 0; -#define PMUL(r) \ - do { \ - tmp = src2 * (int32_t)s.VIS_B32(r); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; \ - } while (0) - - PMUL(0); - PMUL(1); - PMUL(2); - PMUL(3); -#undef PMUL + d.VIS_W64(0) = do_ms16b(s.VIS_B32(0), src2); + d.VIS_W64(1) = do_ms16b(s.VIS_B32(1), src2); + d.VIS_W64(2) = do_ms16b(s.VIS_B32(2), src2); + d.VIS_W64(3) = do_ms16b(s.VIS_B32(3), src2); return d.ll; } @@ -150,23 +138,14 @@ uint64_t helper_fmul8x16a(uint32_t src1, int32_t src2) uint64_t helper_fmul8sux16(uint64_t src1, uint64_t src2) { VIS64 s, d; - uint32_t tmp; s.ll = src1; d.ll = src2; -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; - - PMUL(0); - PMUL(1); - PMUL(2); - PMUL(3); -#undef PMUL + d.VIS_W64(0) = do_ms16b(s.VIS_SB64(1), d.VIS_SW64(0)); + d.VIS_W64(1) = do_ms16b(s.VIS_SB64(3), d.VIS_SW64(1)); + d.VIS_W64(2) = do_ms16b(s.VIS_SB64(5), d.VIS_SW64(2)); + d.VIS_W64(3) = do_ms16b(s.VIS_SB64(7), d.VIS_SW64(3)); return d.ll; } @@ -174,23 +153,14 @@ uint64_t helper_fmul8sux16(uint64_t src1, uint64_t src2) uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2) { VIS64 s, d; - uint32_t tmp; s.ll = src1; d.ll = src2; -#define PMUL(r) \ - tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp += 0x100; \ - } \ - d.VIS_W64(r) = tmp >> 8; - - PMUL(0); - PMUL(1); - PMUL(2); - PMUL(3); -#undef PMUL + d.VIS_W64(0) = do_ms16b(s.VIS_B64(0), d.VIS_SW64(0)); + d.VIS_W64(1) = do_ms16b(s.VIS_B64(2), d.VIS_SW64(1)); + d.VIS_W64(2) = do_ms16b(s.VIS_B64(4), d.VIS_SW64(2)); + d.VIS_W64(3) = do_ms16b(s.VIS_B64(6), d.VIS_SW64(3)); return d.ll; }