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bh=1VfiQpZYlW8Jz9iznM6Lb0b8iBrF/nSrwHwBI9Xs9Do=; b=A4SX3XtiNXWhUX4VGGbZoGHSqSoOAJr9OapEi4oXGpmRc/2gJ9sx396NHctcC9TQ7Z 94fyXqaVnkQTY7JA9ikOmtWELoevCQwX/wp5hAHiiDFaLBPtX4rq4G+ZvAOqKm+vLB2A zzeWsnOPPeRjrECbLBHtPTo9yGR89YSUUeqpW3XHOcxc2TRngl+ZJV3Mw7ZdkalMzbYy i3uXVFvawiGzgvT253F8DjVX8RhpzXqZElG7OWmEJkV2cFlP9aG8CSaXz2uA5Hjsr4B5 AjwH+1QCBn3Jc/E/kQffNW9Ak5GblhTR+0W8vvklOy3HSDN4UbWGvwkUrHL1dVPL5SE/ ysLA== X-Gm-Message-State: AOJu0YwISgxlxuFUWZrOlephFZo18rkPGmf98DPoRrrlKNZUwik4KuBL vkYgFSFlqsq7J3W7ESzd8cf0qpEgNsq7tTQ55rklYd0TULRrwdtNR/6KrOvTvcTzVyhHN6mXRmp W X-Received: by 2002:a17:90a:af86:b0:2b5:91d1:3ae8 with SMTP id 98e67ed59e1d1-2b6c711009cmr2623785a91.14.1715318656119; Thu, 09 May 2024 22:24:16 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8470:9d31:c7dc:c8bd:73d9]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b67158c39dsm2380391a91.35.2024.05.09.22.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 22:24:15 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Cc: Christophe Lyon , Luis Machado Subject: [PATCH v3 1/5] gdb/aarch64: Disable displaced single-step for MOPS instructions Date: Fri, 10 May 2024 02:24:04 -0300 Message-ID: <20240510052408.2173579-2-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240510052408.2173579-1-thiago.bauermann@linaro.org> References: <20240510052408.2173579-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patch=linaro.org@sourceware.org The AArch64 MOPS (Memory Operation) instructions provide a standardised instruction sequence to perform a memset, memcpy or memmove. A sequence is always composed of three instructions: a prologue instruction, a main instruction and an epilogue instruction. As an illustration, here are the implementations of these memory operations in glibc 2.39: (gdb) disassemble/r Dump of assembler code for function __memset_mops: => 0x0000fffff7e8d780 <+0>: d503201f nop 0x0000fffff7e8d784 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8d788 <+8>: 19c10443 setp [x3]!, x2!, x1 0x0000fffff7e8d78c <+12>: 19c14443 setm [x3]!, x2!, x1 0x0000fffff7e8d790 <+16>: 19c18443 sete [x3]!, x2!, x1 0x0000fffff7e8d794 <+20>: d65f03c0 ret End of assembler dump. (gdb) disassemble/r Dump of assembler code for function __memcpy_mops: => 0x0000fffff7e8c580 <+0>: d503201f nop 0x0000fffff7e8c584 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8c588 <+8>: 19010443 cpyfp [x3]!, [x1]!, x2! 0x0000fffff7e8c58c <+12>: 19410443 cpyfm [x3]!, [x1]!, x2! 0x0000fffff7e8c590 <+16>: 19810443 cpyfe [x3]!, [x1]!, x2! 0x0000fffff7e8c594 <+20>: d65f03c0 ret End of assembler dump. (gdb) disassemble/r Dump of assembler code for function __memmove_mops: => 0x0000fffff7e8d180 <+0>: d503201f nop 0x0000fffff7e8d184 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8d188 <+8>: 1d010443 cpyp [x3]!, [x1]!, x2! 0x0000fffff7e8d18c <+12>: 1d410443 cpym [x3]!, [x1]!, x2! 0x0000fffff7e8d190 <+16>: 1d810443 cpye [x3]!, [x1]!, x2! 0x0000fffff7e8d194 <+20>: d65f03c0 ret End of assembler dump. The Arm Architecture Reference Manual says that "the prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory". Therefore this patch disables displaced stepping on them. PR tdep/31666 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31666 --- gdb/aarch64-tdep.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) Change in v3: - Remove aarch64_software_single_step_mops function and the change to call it from aarch64_software_single_step, since Luis clarified that it is in fact possible to single step through MOPS sequences. No change in v2. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 8d0553f3d7cd..05ecd421cd0e 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -3808,10 +3808,12 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return NULL; - /* Look for a Load Exclusive instruction which begins the sequence. */ - if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) + /* Look for a Load Exclusive instruction which begins the sequence, + or for a MOPS instruction. */ + if ((inst.opcode->iclass == ldstexcl && bit (insn, 22)) + || AARCH64_CPU_HAS_FEATURE (*inst.opcode->avariant, MOPS)) { - /* We can't displaced step atomic sequences. */ + /* We can't displaced step atomic sequences nor MOPS instructions. */ return NULL; } From patchwork Fri May 10 05:24:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 796030 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp668909wra; Thu, 9 May 2024 22:25:03 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCWOmRZvSi4db0OG0gpYc/3ae7ndn6E/4QyHaj+JUqpuyKj6LUXqVXpTGsdL7BrK9NDMXbjc8Wc517nEaBrySrnS X-Google-Smtp-Source: AGHT+IHW971PDSntMTvwuipXajvERq0kL2fGMbNkcHDuJYef+RKBTY3ajHRyunxdMCsYKbGsQhC+ X-Received: by 2002:a05:6102:6cf:b0:47d:8561:99aa with SMTP id ada2fe7eead31-48077db7181mr2284628137.4.1715318702971; Thu, 09 May 2024 22:25:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1715318702; cv=pass; d=google.com; s=arc-20160816; b=rF49Vj2846AH8Q2QtUHeDA6FIspMVz7ClfYondl/bX1bjfunn80j09zjnLYrNRp39t pk9Qz5EuAhHeBJJWcZ0qQe9nRJy1zQ2h24aSeeYH5xxHsZxavkJxgdhdHjGtfy+ohqpt 6P829Y1L9MatBUpUlRN/JZ39idhk12xFba8s5Fc1rhiG8Ho4kErI5dltUskOHLpjoQps UwTs7chuZ9GM/TacEumLE0DwgpKex/+1SZavonjco7ZkGzm0t4gXV1AKh3afYVO5hYV9 Gu6BdDF+ylGNo3GVtX4pIz3opJXbx+VRW2YPoCQUjYBElLEXWpRpbdKkq7VrhaWIiIaP yiZg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=c47GaQK384qi+52Wc9yQ+x60wpMF23cl14HCLkeB8Rg=; fh=fCgs51ICTgFk+vSt57NFPMWoUahXD4XhqjP2ci5WYSU=; b=t3AT/KRrXke4Zg83kZKQsjB1/b+B4QPE6LGsvJoxvXHNtCe1rFWPTbPWd0ZVuG804l ac5aECYjc79owQe0ZeY3qs3NrXNNftKEhfSZckLSQ/0fMc2SvpzG80UvYKKY4Iodanap tlhPGhh70VzWCQGnsT2AHZq8ulTTwtdbVJsFtd1Cpk2/io451doZQHTmLT8b2+RHRRim 8vrkgaf3hwMxw1nyHl5LgIieFcoCrrHtNDCrFUZkEnuNyHNnBx+h/PlOW+nrwCKPnTG5 T72ccoCrsWXPJChbnFcXfYM2c27RjjTeurl6kgmnry7aQmQoodfFZpjcCfKnlOYR/unR 1h8Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tKNbaXnd; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gdb-patches-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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Date: Fri, 10 May 2024 02:24:05 -0300 Message-ID: <20240510052408.2173579-3-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240510052408.2173579-1-thiago.bauermann@linaro.org> References: <20240510052408.2173579-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patch=linaro.org@sourceware.org There are two kinds of MOPS instructions: set instructions and copy instructions. Within each group there are variants with minor differences in how they read or write to memory — e.g., non-temporal read and/or write, unprivileged read and/or write and permutations of those — but they work in the same way in terms of the registers and regions of memory that they modify. PR tdep/31666 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31666 --- gdb/aarch64-tdep.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) No change since v1. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 05ecd421cd0e..a9a67107675c 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -5188,6 +5188,86 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) return AARCH64_RECORD_SUCCESS; } +/* Record handler for Memory Copy and Memory Set instructions. */ + +static unsigned int +aarch64_record_memcopy_memset (aarch64_insn_decode_record *aarch64_insn_r) +{ + if (record_debug) + debug_printf ("Process record: memory copy and memory set\n"); + + uint8_t op1 = bits (aarch64_insn_r->aarch64_insn, 22, 23); + uint8_t op2 = bits (aarch64_insn_r->aarch64_insn, 12, 15); + uint32_t reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); + uint32_t reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); + uint32_t record_buf[3]; + uint64_t record_buf_mem[4]; + + if (op1 != 3) + { + /* Copy instructions. */ + uint32_t reg_rs = bits (aarch64_insn_r->aarch64_insn, 16, 20); + + record_buf[0] = reg_rd; + record_buf[1] = reg_rn; + record_buf[2] = reg_rs; + aarch64_insn_r->reg_rec_count = 3; + + ULONGEST dest_addr; + regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rd, + &dest_addr); + ULONGEST source_addr; + regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rs, + &source_addr); + LONGEST length; + regcache_raw_read_signed (aarch64_insn_r->regcache, reg_rn, + &length); + + /* In a processor using algorithm option A, the length in Rn has an + inverted sign. */ + if (length < 0) + length *= -1; + + record_buf_mem[0] = length; + record_buf_mem[1] = dest_addr; + record_buf_mem[2] = length; + record_buf_mem[3] = source_addr; + aarch64_insn_r->mem_rec_count = 2; + } + else if ((op1 == 3 && op2 < 12) || (op1 == 3 && op2 < 12)) + { + /* Set instructions. */ + record_buf[0] = reg_rd; + record_buf[1] = reg_rn; + aarch64_insn_r->reg_rec_count = 2; + + ULONGEST address; + regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rd, + &address); + + LONGEST length; + regcache_raw_read_signed (aarch64_insn_r->regcache, reg_rn, + &length); + + /* In a processor using algorithm option B, the length in Rn has an + inverted sign. */ + if (length < 0) + length *= -1; + + record_buf_mem[0] = length; + record_buf_mem[1] = address; + aarch64_insn_r->mem_rec_count = 1; + } + else + return AARCH64_RECORD_UNKNOWN; + + MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, + record_buf_mem); + REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, + record_buf); + return AARCH64_RECORD_SUCCESS; +} + /* Record handler for load and store instructions. */ static unsigned int @@ -5465,6 +5545,10 @@ aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r) if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; } + /* Memory Copy and Memory Set instructions. */ + else if ((insn_bits24_27 & 1) == 1 && insn_bits28_29 == 1 + && insn_bits10_11 == 1 && !insn_bit21) + return aarch64_record_memcopy_memset (aarch64_insn_r); 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This test is similar to gdb.base/memops-watchpoint.exp, but specifically for MOPS instructions rather than whatever instructions are used in the libc's implementation of memset/memcpy/memmove. There's a separate watched variable for each set of instructions so that the testcase can test whether GDB correctly identified the watchpoint that triggered in each case. --- .../gdb.arch/aarch64-mops-watchpoint.c | 66 ++++++++++++++++ .../gdb.arch/aarch64-mops-watchpoint.exp | 79 +++++++++++++++++++ gdb/testsuite/lib/gdb.exp | 61 ++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.c create mode 100644 gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.exp No change since v1. diff --git a/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.c b/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.c new file mode 100644 index 000000000000..b981f033d210 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.c @@ -0,0 +1,66 @@ +/* This test program is part of GDB, the GNU debugger. + + Copyright 2024 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +int +main (void) +{ + char source[40] __attribute__ ((aligned (8))) + = "This is a relatively long string..."; + char a[40] __attribute__ ((aligned (8))) + = "String to be overwritten with zeroes"; + char b[40] __attribute__ ((aligned (8))) + = "Another string to be memcopied..."; + char c[40] __attribute__ ((aligned (8))) + = "Another string to be memmoved..."; + char *p, *q; + long size, zero; + + /* Break here. */ + p = a; + size = sizeof (a); + zero = 0; + /* memset implemented in MOPS instructions. */ + __asm__ volatile ("setp [%0]!, %1!, %2\n\t" + "setm [%0]!, %1!, %2\n\t" + "sete [%0]!, %1!, %2\n\t" + : "+&r"(p), "+&r"(size) + : "r"(zero) + : "memory"); + + p = b; + q = source; + size = sizeof (b); + /* memmove implemented in MOPS instructions. */ + __asm__ volatile ("cpyp [%0]!, [%1]!, %2!\n\t" + "cpym [%0]!, [%1]!, %2!\n\t" + "cpye [%0]!, [%1]!, %2!\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + p = c; + q = source; + size = sizeof (c); + /* memcpy implemented in MOPS instructions. */ + __asm__ volatile ("cpyfp [%0]!, [%1]!, %2!\n\t" + "cpyfm [%0]!, [%1]!, %2!\n\t" + "cpyfe [%0]!, [%1]!, %2!\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.exp b/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.exp new file mode 100644 index 000000000000..9e210602d800 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-mops-watchpoint.exp @@ -0,0 +1,79 @@ +# Copyright 2024 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test a binary that uses MOPS (Memory Operations) instructions. +# This test is similar to gdb.base/memops-watchpoint.exp, but specifically +# tests MOPS instructions rather than whatever instructions are used in the +# system libc's implementation of memset/memcpy/memmove. + +require allow_hw_watchpoint_tests allow_aarch64_mops_tests + +standard_testfile + +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \ + [list debug additional_flags=-march=armv9.3-a]] } { + return -1 +} + +set linespec ${srcfile}:[gdb_get_line_number "Break here"] +if ![runto ${linespec}] { + return -1 +} + +gdb_test "watch -location a\[28\]" \ + "(Hardware w|W)atchpoint ${decimal}: -location a\\\[28\\\]" \ + "set watch on a" +gdb_test "watch -location b\[28\]" \ + "(Hardware w|W)atchpoint ${decimal}: -location b\\\[28\\\]" \ + "set watchpoint on b" +gdb_test "watch -location c\[28\]" \ + "(Hardware w|W)atchpoint ${decimal}: -location c\\\[28\\\]" \ + "set watchpoint on c" + +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Hardware watchpoint ${decimal}: -location a\\\[28\\\]" \ + "" \ + "Old value = 104 'h'" \ + "New value = 0 '\\\\000'" \ + "$hex in main \\(\\) at .*aarch64-mops-watchpoint.c:$decimal" \ + "${decimal}\\s+__asm__ volatile \\(\"setp.*\\\\n\\\\t\""] \ + "continue until set watchpoint hits" + +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Hardware watchpoint ${decimal}: -location b\\\[28\\\]" \ + "" \ + "Old value = 101 'e'" \ + "New value = 114 'r'" \ + "$hex in main \\(\\) at .*aarch64-mops-watchpoint.c:$decimal" \ + "${decimal}\\s+__asm__ volatile \\(\"cpyp.*\\\\n\\\\t\""] \ + "continue until cpy watchpoint hits" + +gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Hardware watchpoint ${decimal}: -location c\\\[28\\\]" \ + "" \ + "Old value = 100 'd'" \ + "New value = 114 'r'" \ + "$hex in main \\(\\) at .*aarch64-mops-watchpoint.c:$decimal" \ + "${decimal}\\s+__asm__ volatile \\(\"cpyfp.*\\\\n\\\\t\""] \ + "continue until cpyf watchpoint hits" diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp index 0d78691c381b..25b272fdaabc 100644 --- a/gdb/testsuite/lib/gdb.exp +++ b/gdb/testsuite/lib/gdb.exp @@ -4497,6 +4497,67 @@ proc aarch64_supports_sme_svl { length } { return 1 } +# Run a test on the target to see if it supports Aarch64 MOPS (Memory +# Operations) extensions. Return 0 if so, 1 if it does not. Note this causes +# a restart of GDB. + +gdb_caching_proc allow_aarch64_mops_tests {} { + global srcdir subdir gdb_prompt inferior_exited_re + + set me "allow_aarch64_mops_tests" + + if { ![is_aarch64_target]} { + return 0 + } + + # ARMv9.3-A contains the MOPS extension. The test program doesn't use it, + # but take the opportunity to check whether the toolchain knows about MOPS. + set compile_flags "{additional_flags=-march=armv9.3-a}" + + # Compile a program that tests the MOPS feature. + set src { + #include + #include + + #ifndef HWCAP2_MOPS + #define HWCAP2_MOPS (1UL << 43) + #endif + + int main() { + bool mops_supported = getauxval (AT_HWCAP2) & HWCAP2_MOPS; + + return !mops_supported; + } + } + + if {![gdb_simple_compile $me $src executable $compile_flags]} { + return 0 + } + + # Compilation succeeded so now run it via gdb. + clean_restart $obj + gdb_run_cmd + gdb_expect { + -re ".*$inferior_exited_re with code 01.*${gdb_prompt} $" { + verbose -log "\n$me mops support not detected" + set allow_mops_tests 0 + } + -re ".*$inferior_exited_re normally.*${gdb_prompt} $" { + verbose -log "\n$me: mops support detected" + set allow_mops_tests 1 + } + default { + warning "\n$me: default case taken" + set allow_mops_tests 0 + } + } + gdb_exit + remote_file build delete $obj + + verbose "$me: returning $allow_mops_tests" 2 + return $allow_mops_tests +} + # A helper that compiles a test case to see if __int128 is supported. proc gdb_int128_helper {lang} { return [gdb_can_simple_compile "i128-for-$lang" { From patchwork Fri May 10 05:24:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thiago Jung Bauermann X-Patchwork-Id: 796032 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp669154wra; Thu, 9 May 2024 22:25:48 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCV0ijg+Nt5Dx1E0+Eo/AMLq1ufAkqagv4Kf7pjRsMMQ3U/m23/1k53rPHTAsGlyk9/w2uenmgUzLBbkUHC3luUi X-Google-Smtp-Source: AGHT+IHvSWRBaeVMOLiUJ8E4i4CFb6htwrh42ddvmDye6XNZe+w9KwPuGWbZUr2t/0+5oksy4KIo X-Received: by 2002:a05:620a:ec6:b0:792:8f3a:b663 with SMTP id af79cd13be357-792c75f4787mr154366185a.55.1715318747979; Thu, 09 May 2024 22:25:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1715318747; cv=pass; d=google.com; s=arc-20160816; b=lMugz8W4gJqvRx9z+AHpy9Fhh2TtYHapxtXyGvuFIoYAHqii4t2wYbn5JtRpz5gRbL mhQ1bm/LwW/l0exEoeC1fC9kKoUZhLJ3/tmFH3rwFpGeQyQcyf1pRlc8aUzdzF3Y41qB /+N53yBDeZdKo7HykHUfQKp3nr6WFRS3g7wm8ShdlPZgtwYV9jMdjYU0e3IUlHkzrK6E gTBRehPi+glv20HkGkuBviTN1DQyzhdKMOGChpNFnHoc1/HZJWRs7oHd9OMvbFc/k+NI 8LbskWHeUIh6navWITFOcrXQtB5WFt1zTFOLAc5CdqAtdwFgSiIENOB/JewF42ghMFOo Fb3A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=fiMeF04crUGxuDNIIhOyUXBmvAAisQd3aevx/17A7U0=; fh=fCgs51ICTgFk+vSt57NFPMWoUahXD4XhqjP2ci5WYSU=; b=E4CNMX5U5nSbE+kIRr5TpJuOQl7FMfp5ZIJ9O7guMKUnR8TDxlpeD5iciHexXhZmHH XRH1CDk82tetxWqd5BpkYiq3of7YpBL9MVBliQQRbw/gFvTb5+14Yl1W/VuWdMlSMKQw N6eNQbtStG7PwwhTp5p3cSj583upl9GZX7H15chL5MjkoP7BatlfvPI6ebgw4/72KBx0 5tn9gOaqu9h9OwCqIDTG5wssAjyHF8vKCJ9EVKS0DXy38CmzVFVAj9Wz04TYiJzyhnQL TovUb6MD9UVNpUWCaECvqcKvp73J6ju2CVolfdMzITlxD+I4MKlyufmPRDDoe1RY2iEc QyZA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hgbU8TI7; arc=pass (i=1); spf=pass (google.com: domain of gdb-patches-bounces+patch=linaro.org@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gdb-patches-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. 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This bug didn't affect the effectiveness of the test. Changes in v2: - Add prfm instruction after each MOPS sequence and look for it in the testcase to verify that the sequence was stepped through (Suggested by Christophe). diff --git a/gdb/testsuite/gdb.arch/aarch64-mops-single-step.c b/gdb/testsuite/gdb.arch/aarch64-mops-single-step.c new file mode 100644 index 000000000000..4a27867d4b57 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-mops-single-step.c @@ -0,0 +1,73 @@ +/* This file is part of GDB, the GNU debugger. + + Copyright 2024 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#define TEST_STRING "Just a test string." +#define BUF_SIZE sizeof(TEST_STRING) + +int +main (void) +{ + char source[BUF_SIZE] = TEST_STRING; + char dest[BUF_SIZE]; + char *p, *q; + long size, zero; + + /* Note: The prfm instruction in the asm statements below is there just + to allow the testcase to recognize when the PC is at the instruction + right after the MOPS sequence. */ + + p = dest; + size = sizeof (dest); + zero = 0; + /* Break memset. */ + /* memset implemented in MOPS instructions. */ + __asm__ volatile ("setp [%0]!, %1!, %2\n\t" + "setm [%0]!, %1!, %2\n\t" + "sete [%0]!, %1!, %2\n\t" + "prfm pldl3keep, [%0, #0]\n\t" + : "+&r"(p), "+&r"(size) + : "r"(zero) + : "memory"); + + p = dest; + q = source; + size = sizeof (dest); + /* Break memcpy. */ + /* memcpy implemented in MOPS instructions. */ + __asm__ volatile ("cpyfp [%0]!, [%1]!, %2!\n\t" + "cpyfm [%0]!, [%1]!, %2!\n\t" + "cpyfe [%0]!, [%1]!, %2!\n\t" + "prfm pldl3keep, [%0, #0]\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + + p = dest; + q = source; + size = sizeof (dest); + /* Break memmove. */ + /* memmove implemented in MOPS instructions. */ + __asm__ volatile ("cpyp [%0]!, [%1]!, %2!\n\t" + "cpym [%0]!, [%1]!, %2!\n\t" + "cpye [%0]!, [%1]!, %2!\n\t" + "prfm pldl3keep, [%0, #0]\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + + return 0; +} diff --git a/gdb/testsuite/gdb.arch/aarch64-mops-single-step.exp b/gdb/testsuite/gdb.arch/aarch64-mops-single-step.exp new file mode 100644 index 000000000000..a6390d4bff7e --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-mops-single-step.exp @@ -0,0 +1,132 @@ +# Copyright 2024 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# This file is part of the GDB testsuite. + +# Test single stepping through MOPS (memory operations) instruction sequences. + +require allow_aarch64_mops_tests + +standard_testfile +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \ + [list debug additional_flags=-march=armv9.3-a]] } { + return -1 +} + +# INSTRUCTION should be just its mnemonic, without any arguments. +proc is_at_instruction { instruction } { + global gdb_prompt hex + + set test "pc points to $instruction" + gdb_test_multiple {x/i $pc} $test { + -re -wrap "=> $hex \[^\r\n\]+:\t$instruction\t\[^\r\n\]+" { + return 1 + } + -re "\r\n$gdb_prompt $" { + return 0 + } + } + + return 0 +} + +proc arrive_at_instruction { instruction } { + set count 0 + + while { [is_at_instruction $instruction] != 1 } { + gdb_test -nopass "stepi" ".*__asm__ volatile.*" \ + "stepi #$count to reach $instruction" + incr count + + if { $count > 50 } { + fail "didn't reach $instruction" + return 0 + } + } + + return 1 +} + +# If the inferior is reschedule to another CPU while a main or epilogue +# instruction is executed, the OS resets the inferior back to the prologue +# instruction, so we need to allow for that possibility. +proc step_through_sequence { prefix } { + set count 0 + + while { [is_at_instruction ${prefix}p] == 1 && $count < 50 } { + incr count + + # The stepi output isn't useful to detect whether we stepped over + # the instruction. + gdb_test "stepi" "\[^\r\n\]+" "step over ${prefix}p" + if { [is_at_instruction ${prefix}m] == 1 } { + pass "stepped over ${prefix}p" + } else { + fail "stepped over ${prefix}e" + return 0 + } + + gdb_test "stepi" "\[^\r\n\]+" "step over ${prefix}m" + if { [is_at_instruction ${prefix}e] == 1 } { + pass "stepped over ${prefix}m" + } elseif { [is_at_instruction ${prefix}p] == 1 } { + # The inferior was rescheduled to another CPU. + pass "${prefix}m: reset back to prologue" + continue + } else { + fail "stepped over ${prefix}m" + return 0 + } + + gdb_test "stepi" "\[^\r\n\]+" "step over ${prefix}e" + if { [is_at_instruction prfm] == 1 } { + pass "stepped over ${prefix}e" + return 1 + } elseif { [is_at_instruction ${prefix}p] == 1 } { + # The inferior was rescheduled to another CPU. + pass "${prefix}e: reset back to prologue" + continue + } + } + + fail "step through $prefix sequence" + return 0 +} + +if ![runto_main] { + return -1 +} + +gdb_breakpoint ${srcfile}:[gdb_get_line_number "Break memset"] +gdb_breakpoint ${srcfile}:[gdb_get_line_number "Break memcpy"] +gdb_breakpoint ${srcfile}:[gdb_get_line_number "Break memmove"] + +gdb_continue_to_breakpoint "memset breakpoint" + +if { [arrive_at_instruction setp] } { + step_through_sequence set +} + +gdb_continue_to_breakpoint "memcpy breakpoint" + +if { [arrive_at_instruction cpyfp] } { + step_through_sequence cpyf +} + +gdb_continue_to_breakpoint "memmove breakpoint" + +if { [arrive_at_instruction cpyp] } { + step_through_sequence cpy +} From patchwork Fri May 10 05:24:08 2024 Content-Type: text/plain; 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bh=eNgr8QBqk40xJ5H8ax7gu6F3/0FDwEJj//6MPJSjrWo=; b=jdFC+xZtucrTs8Xw7Vf+qVmo75C45/eioC1HmvPcaVSZDaFQ4vCOL1FiCPcHjNyi3c PnlsBiAD52ZrZ1EznI5penGd6DxSzcWKQ14ME5mYV2ka6Bc+6m/EPf0kn689RxRS0Fhb bFLRG3xxLF5ZVe1XROKEpW5mE2lv351RW8y+Rjt7bnCAO8mMmIetWxZPbYfH0g3y0t1l uYpN34ot8lTMHzMicAxQIuKpWJ34BQJFa0/S0oLO0wSy4Di2Au4mpf26Ji9fcMWmkpIK fwlyYA41ENAPa9YQKxkWE7NMU7qMAeTioRWbGBRdK6R4A4dWr6oFqarFXP9vt3Ot/ZPZ WhSg== X-Gm-Message-State: AOJu0YzTH2U5ocXGPo0I4YS+0mMZkspTLBkotjwXV3l2zh6kdS+NR+Ft gzz0YZD4KD1rPprI2jsdwejzvkJJQkMe+W+6/6fgaMXQ8ViGPfgZ6uWA3wzbENZqH6ger5oDPW5 m X-Received: by 2002:a05:6a00:1892:b0:6f0:b53c:dfb1 with SMTP id d2e1a72fcca58-6f4e029bae3mr1637387b3a.1.1715318669083; Thu, 09 May 2024 22:24:29 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8470:9d31:c7dc:c8bd:73d9]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2b373e5sm2168661b3a.219.2024.05.09.22.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 22:24:28 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Cc: Christophe Lyon , Luis Machado Subject: [PATCH v3 5/5] gdb/testsuite: Add gdb.reverse/aarch64-mops.exp Date: Fri, 10 May 2024 02:24:08 -0300 Message-ID: <20240510052408.2173579-6-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240510052408.2173579-1-thiago.bauermann@linaro.org> References: <20240510052408.2173579-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patch=linaro.org@sourceware.org The testcase verifies that MOPS instructions are recorded and correctly reversed. Not all variants of the copy and set instructions are tested, since there are many and the record and replay target processes them in the same way. --- gdb/testsuite/gdb.reverse/aarch64-mops.c | 71 +++++++++ gdb/testsuite/gdb.reverse/aarch64-mops.exp | 171 +++++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 gdb/testsuite/gdb.reverse/aarch64-mops.c create mode 100644 gdb/testsuite/gdb.reverse/aarch64-mops.exp No change since v1. diff --git a/gdb/testsuite/gdb.reverse/aarch64-mops.c b/gdb/testsuite/gdb.reverse/aarch64-mops.c new file mode 100644 index 000000000000..513f324b9dd6 --- /dev/null +++ b/gdb/testsuite/gdb.reverse/aarch64-mops.c @@ -0,0 +1,71 @@ +/* This test program is part of GDB, the GNU debugger. + + Copyright 2024 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#define TEST_STRING "Just a test string." +#define BUF_SIZE sizeof(TEST_STRING) + +int +main (void) +{ + char dest[BUF_SIZE]; + char source[BUF_SIZE] = TEST_STRING; + register char *p asm ("x19"); + register char *q asm ("x20"); + register long size asm ("x21"); + register long zero asm ("x22"); + + p = dest; + size = BUF_SIZE; + zero = 0; + /* Before setp. */ + /* memset implemented in MOPS instructions. */ + __asm__ volatile ("setp [%0]!, %1!, %2\n\t" + "setm [%0]!, %1!, %2\n\t" + "sete [%0]!, %1!, %2\n\t" + : "+&r"(p), "+&r"(size) + : "r"(zero) + : "memory"); + + /* After sete. */ + p = dest; + q = source; + size = BUF_SIZE; + /* Before cpyp. */ + /* memmove implemented in MOPS instructions. */ + __asm__ volatile ("cpyp [%0]!, [%1]!, %2!\n\t" + "cpym [%0]!, [%1]!, %2!\n\t" + "cpye [%0]!, [%1]!, %2!\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + /* After cpye. */ + p = dest; + q = source; + size = BUF_SIZE; + /* Before cpyfp. */ + /* memcpy implemented in MOPS instructions. */ + __asm__ volatile ("cpyfp [%0]!, [%1]!, %2!\n\t" + "cpyfm [%0]!, [%1]!, %2!\n\t" + "cpyfe [%0]!, [%1]!, %2!\n\t" + : "+&r" (p), "+&r" (q), "+&r" (size) + : + : "memory"); + /* After cpyfe. */ + p = dest; + + return 0; +} diff --git a/gdb/testsuite/gdb.reverse/aarch64-mops.exp b/gdb/testsuite/gdb.reverse/aarch64-mops.exp new file mode 100644 index 000000000000..f9c1257e0b11 --- /dev/null +++ b/gdb/testsuite/gdb.reverse/aarch64-mops.exp @@ -0,0 +1,171 @@ +# Copyright 2024 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test instruction record for AArch64 FEAT_MOPS instructions. +# Based on gdb.reverse/ppc_record_test_isa_3_1.exp +# +# The basic flow of the record tests are: +# 1) Stop before executing the instructions of interest. Record +# the initial value of the registers that the instruction will +# change, i.e. the destination register. +# 2) Execute the instructions. Record the new value of the +# registers that changed. +# 3) Reverse the direction of the execution and execute back to +# just before the instructions of interest. Record the final +# value of the registers of interest. +# 4) Check that the initial and new values of the registers are +# different, i.e. the instruction changed the registers as expected. +# 5) Check that the initial and final values of the registers are +# the same, i.e. GDB record restored the registers to their +# original values. + +require allow_aarch64_mops_tests + +standard_testfile + +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \ + [list debug additional_flags=-march=armv9.3-a]] } { + return -1 +} + +if ![runto_main] { + return -1 +} + +gdb_test_no_output "record full" + +proc do_test { insn_prefix } { + global decimal hex + + set before_seq [gdb_get_line_number "Before ${insn_prefix}p"] + set after_seq [gdb_get_line_number "After ${insn_prefix}e"] + + with_test_prefix $insn_prefix { + gdb_test "break $before_seq" \ + "Breakpoint $decimal at $hex: file .*/aarch64-mops.c, line $decimal\\." \ + "break before instruction sequence" + gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Breakpoint $decimal, main \\(\\) at .*/aarch64-mops.c:$decimal" \ + "$decimal\[ \t\]+__asm__ volatile \\(\"${insn_prefix}p \[^\r\n\]+\""] \ + "about to execute instruction sequence" + + # Record the initial register values. + set x19_initial [capture_command_output "info register x19" ""] + set x21_initial [capture_command_output "info register x21" ""] + + # The set instructions use the ZERO variable, but not Q, and the other + # instructions are the opposite. + if {[string compare $insn_prefix "set"] == 0} { + set x22_initial [capture_command_output "info register x22" ""] + } else { + set x20_initial [capture_command_output "info register x20" ""] + } + + gdb_test "break $after_seq" \ + "Breakpoint $decimal at $hex: file .*/aarch64-mops.c, line $decimal\\." \ + "break after instruction sequence" + gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Breakpoint $decimal, main \\(\\) at .*/aarch64-mops.c:$decimal" \ + "$decimal\[ \t\]+p = dest;"] \ + "executed instruction sequence" + + # Record the new register values. + set x19_new [capture_command_output "info register x19" ""] + set x21_new [capture_command_output "info register x21" ""] + + if {[string compare $insn_prefix "set"] == 0} { + set x22_new [capture_command_output "info register x22" ""] + } else { + set x20_new [capture_command_output "info register x20" ""] + } + + # Execute in reverse to before the instruction sequence. + gdb_test_no_output "set exec-direction reverse" + + gdb_test "continue" \ + [multi_line \ + "Continuing\\." \ + "" \ + "Breakpoint $decimal, main \\(\\) at .*/aarch64-mops.c:$decimal" \ + "$decimal\[ \t\]+__asm__ volatile \\(\"${insn_prefix}p \[^\r\n\]+\""] \ + "reversed execution of instruction sequence" + + # Record the final register values. + set x19_final [capture_command_output "info register x19" ""] + set x21_final [capture_command_output "info register x21" ""] + + if {[string compare $insn_prefix "set"] == 0} { + set x22_final [capture_command_output "info register x22" ""] + } else { + set x20_final [capture_command_output "info register x20" ""] + } + + # Check initial and new values of x19 are different. + gdb_assert [string compare $x19_initial $x19_new] \ + "check x19 initial value versus x19 new value" + + # Check initial and new values of x21 are different. + gdb_assert [string compare $x21_initial $x21_new] \ + "check x21 initial value versus x21 new value" + + if {[string compare $insn_prefix "set"] == 0} { + # Check initial and new values of x22 are the same. + # The register with the value to set shouldn't change. + gdb_assert ![string compare $x22_initial $x22_new] \ + "check x22 initial value versus x22 new value" + } else { + # Check initial and new values of x20 are different. + gdb_assert [string compare $x20_initial $x20_new] \ + "check x20 initial value versus x20 new value" + } + + # Check initial and final values of x19 are the same. + gdb_assert ![string compare $x19_initial $x19_final] \ + "check x19 initial value versus x19 final value" + + # Check initial and final values of x21 are the same. + gdb_assert ![string compare $x21_initial $x21_final] \ + "check x21 initial value versus x21 final value" + + if {[string compare $insn_prefix "set"] == 0} { + # Check initial and final values of x22 are the same. + # The register with the value to set shouldn't change. + gdb_assert ![string compare $x22_initial $x22_final] \ + "check x22 initial value versus x22 final value" + } else { + # Check initial and final values of x20 are the same. + gdb_assert ![string compare $x20_initial $x20_final] \ + "check x20 initial value versus x20 final value" + } + + # Restore forward execution and go to end of recording. + gdb_test_no_output "set exec-direction forward" + gdb_test "record goto end" \ + [multi_line \ + "Go forward to insn number $decimal" \ + "#0 main \\(\\) at .*/aarch64-mops.c:$decimal" \ + "$decimal\[ \t\]+p = dest;"] + } +} + +do_test "set" +do_test "cpy" +do_test "cpyf"